CN113838939A - 一种包含自对准金属硅化物的半导体器件及其制备方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 title claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 14
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- 150000002500 ions Chemical class 0.000 claims description 21
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052724 xenon Inorganic materials 0.000 claims description 5
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 25
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
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- 241001391944 Commicarpus scandens Species 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- -1 germanium ions Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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Abstract
本发明公开了提供一种包含自对准金属硅化物的半导体器件，包含：P型衬底；形成于所述P型衬底上方的轻掺杂N阱；形成于所述轻掺杂N阱上方的自对准金属硅化物；其中，所述轻掺杂N阱邻近所述自对准金属硅化物处包含表面改性区。该半导体器件有助于提高沉积金属的均匀性，消除自对准金属硅化物形成过程中的孔洞，从根本上改善击穿电压掉点的问题。本发明同时提供一种包含自对准金属硅化物的半导体器件的制备方法。
Description
技术领域
本发明涉及半导体技术领域，特别涉及一种包含自对准金属硅化物的半导体器件及其制备方法。
背景技术
肖特基势垒二极管又称载流子二极管，通常包含P型衬底(P-SUB)、形成于所述P型衬底上方的轻掺杂N阱(low dose N type well)以及形成于所述轻掺杂N阱上方的自对准金属硅化物(salicide)。然而，现有自对金属准硅化物多存在分布不够均匀甚至包含贯穿自对金属准硅化物的孔洞等问题，使得肖特基二极管很容易被击穿，引起击穿电压掉点等问题。
因此，如何改善击穿电压掉点问题成为半导体器件制备领域亟待解决的技术问题。
发明内容
为了解决现有的技术问题本发明通过在金属沉积前以植入大原子量离子的方式对轻掺杂N阱进行表面改性处理，使得硅表面多晶化形成表面改性区，有助于提高沉积金属的均匀性，消除自对准金属硅化物形成过程中的孔洞，从根本上改善击穿电压掉点的问题。
依据本发明，提供一种包含自对准金属硅化物的半导体器件，包含：
P型衬底；
形成于所述P型衬底上方的轻掺杂N阱；
形成于所述轻掺杂N阱上方的自对准金属硅化物；
其中，所述轻掺杂N阱与所述自对准金属硅化物邻近处包含表面改性区。
依据本发明的一个实施例，所述表面改性区的厚度为0.1-330。
依据本发明的一个实施例，所述轻掺杂N阱被植入离子以形成所述表面改性区，所述离子包含锗、砷、氙、铟中的至少一种。
依据本发明的一个实施例，所述离子的植入能量为5-15Kev。
依据本发明的一个实施例，所述离子的植入剂量为2E14-2E15个/cm2。
依据本发明，提供一种包含自对准金属硅化物的半导体器件的制备方法，包含以下步骤：
步骤一，使用氧化物阻挡层对轻掺杂N阱的表面进行蚀刻以形成限定自对准金属硅化物区域的凹槽；
步骤二，通过植入离子对轻掺杂N阱进行表面改性处理，以形成表面改性区；
步骤三，在所述表面改性区上方沉积金属；
步骤四，执行至少一次快速热处理工序，以形成自对准金属硅化物。
依据本发明的一个实施例，所述离子包含锗、砷、氙、铟中的至少一种。
依据本发明的一个实施例，所述离子的植入能量为5-15Kev。
依据本发明的一个实施例，所述离子的植入剂量为2E14-2E15个/cm2。
依据本发明的一个实施例，所述步骤三包含在所述表面改性区上方依次沉积氮化钛和钴。
由于采用以上技术方案，本发明与现有技术相比具有如下优点：本发明通过在金属沉积前以植入大原子量离子的方式对轻掺杂N阱进行表面改性处理，使得硅表面多晶化形成表面改性区，有助于提高沉积金属的均匀性，消除自对准金属硅化物形成过程中的孔洞，从根本上改善击穿电压掉点的问题。
附图说明
图1示出了依据本发明的包含自对准金属硅化物的半导体器件一个实施例的示意图；
图2示出了依据本发明的包含自对准金属硅化物的半导体器件的制备方法的流程图；
图3示出了现有的包含自对准金属硅化物的半导体器件的击穿电压测试结果；
图4示出了依据本发明的包含自对准金属硅化物的半导体器件的击穿电压测试结果。
图中，
100P型衬底，200轻掺杂N阱，210表面改性区，300自对准金属硅化物。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面结合实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
图1和图2分别示出了依据本发明的半导体器件一个实施例的示意图及其制备方法的流程图。如图1所示，含有自对准金属硅化物的半导体器件具有P型衬底100、形成于P型衬底100上方的轻掺杂N阱200以及形成于轻掺杂N阱上方两个P+区域之间的自对准金属硅化物300。自对准金属硅化物300的填充过程具体包含如图2所示的以下步骤：
步骤一，使用覆盖于轻掺杂N阱200表面上的氧化物阻挡层(oxide)对轻掺杂N阱200进行蚀刻以形成限定自对准金属硅化物300所在区域的凹槽；
步骤二，通过植入离子对轻掺杂N阱200进行表面改性处理，以在邻近凹槽上表面的区域形成表面改性区210，其中，表面改性区210的厚度优选为
步骤三，在表面改性区210上方沉积金属，在本发明的一个实施例中，可依次沉积氮化钛(TiN)和钴(Co)；
步骤四，执行至少依次快速热处理工序(RTP)，以形成自对准金属硅化物300。
优选地，步骤二中被植入的离子优选为包含锗(Ge)、砷(As)、氙(Xe)、铟(In)中的至少一种在内的大原子量的离子，以利于在植入过程中轰击硅表面使其多晶化，从而实现表面改性的目的；离子的植入能量可以是5-15Kev；离子的植入剂量为2E14-2E15个/cm2。本领域技术人员也可依据实际工况对上述植入参数进行调整。
图3和图4分别示出了现有的半导体器件和依据本发明的半导体器件的击穿电压测试结果。其中，图3分别在9个现有半导体器件上各自选取50个测试点进行了击穿电压检测，图4则在3个在沉积金属前通过植入锗离子在邻近凹槽上表面的区域形成表面改性区210的半导体器件上分别选取50个测试点进行了击穿电压检测。附图3-4中，横坐标均代表测试用半导体器件的击穿电压(observed value)，纵坐标则表示被击穿的半导体器件所占比例(normal probability)。如图3所示，现有半导体器件的击穿电压主要分布于22.5-25V之间——该击穿电压可视为半导体器件的有效击穿电压，而几乎每个半导体器件都存在少数测试点的击穿电压分布于5-20V之间(参见方框内的部分)，明显低于有效击穿电压，即出现击穿电压的掉点问题。如图4所示，依据本发明的方法的半导体器件上所有测试点的击穿电压均分布于37-38V之间。二者相比，本发明的半导体器件至少具有如下优点：
1.有效克服了击穿电压的掉点问题；
2.半导体器件整体击穿电压有所提高；以及
3.半导体器件不同点处的击穿电压之间的差值减小，即击穿电压至分布更加均衡。
以上实施例仅表达了本发明的实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。
Claims (10)
1.包含自对准金属硅化物的半导体器件，其特征在于，包含：
P型衬底；
形成于所述P型衬底上方的轻掺杂N阱；
形成于所述轻掺杂N阱上方的自对准金属硅化物；
其中，所述轻掺杂N阱与所述自对准金属硅化物邻近处包含表面改性区。
2.根据权利要求1所述的半导体器件，其特征在于，所述表面改性区的厚度为
3.根据权利要求1所述的半导体器件，其特征在于，所述轻掺杂N阱被植入离子以形成所述表面改性区，所述离子包含锗、砷、氙、铟中的至少一种。
4.根据权利要求3所述的半导体器件，其特征在于，所述离子的植入能量为5-15Kev。
5.根据权利要求3所述的半导体器件，其特征在于，所述离子的植入剂量为2E14-2E15个/cm2。
6.一种包含自对准金属硅化物的半导体器件的制备方法，其特征在于，包含以下步骤：
步骤一，使用氧化物阻挡层对轻掺杂N阱的表面进行蚀刻以形成限定自对准金属硅化物区域的凹槽；
步骤二，通过植入离子对轻掺杂N阱进行表面改性处理，以形成表面改性区；
步骤三，在所述表面改性区上方沉积金属；
步骤四，执行至少一次快速热处理工序，以形成自对准金属硅化物。
7.根据权利要求6所述的制备方法，其特征在于，所述离子包含锗、砷、氙、铟中的至少一种。
8.根据权利要求6所述的制备方法，其特征在于，所述离子的植入能量为5-15Kev。
9.根据权利要求6所述的制备方法，其特征在于，所述离子的植入剂量为2E14-2E15个/cm2。
10.根据权利要求6所述的制备方法，其特征在于，所述步骤三包含在所述表面改性区上方依次沉积氮化钛和钴。
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000031478A (ja) * | 1998-07-13 | 2000-01-28 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
| US20020105046A1 (en) * | 2001-02-02 | 2002-08-08 | Hironori Matsumoto | Integrated semiconductor circuit device, process of manufacturing the same, IC module and IC card |
| JP2004319592A (ja) * | 2003-04-11 | 2004-11-11 | Nec Electronics Corp | 半導体装置及びその製造方法 |
| US20050233506A1 (en) * | 2001-03-22 | 2005-10-20 | T-Ram Semiconductor, Inc. | Semiconductor device with leakage implant and method of fabrication |
| US20060231910A1 (en) * | 2005-04-15 | 2006-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming silicide and semiconductor device formed thereby |
| US20080149983A1 (en) * | 2006-12-20 | 2008-06-26 | International Business Machines Corporation | Metal-oxide-semiconductor (mos) varactors and methods of forming mos varactors |
-
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- 2020-06-23 CN CN202010581022.7A patent/CN113838939B/zh active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000031478A (ja) * | 1998-07-13 | 2000-01-28 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
| US20020105046A1 (en) * | 2001-02-02 | 2002-08-08 | Hironori Matsumoto | Integrated semiconductor circuit device, process of manufacturing the same, IC module and IC card |
| US20050233506A1 (en) * | 2001-03-22 | 2005-10-20 | T-Ram Semiconductor, Inc. | Semiconductor device with leakage implant and method of fabrication |
| JP2004319592A (ja) * | 2003-04-11 | 2004-11-11 | Nec Electronics Corp | 半導体装置及びその製造方法 |
| US20060231910A1 (en) * | 2005-04-15 | 2006-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming silicide and semiconductor device formed thereby |
| US20080149983A1 (en) * | 2006-12-20 | 2008-06-26 | International Business Machines Corporation | Metal-oxide-semiconductor (mos) varactors and methods of forming mos varactors |
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