CN113838869A - Display panel, manufacturing method thereof and display device - Google Patents
Display panel, manufacturing method thereof and display device Download PDFInfo
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- CN113838869A CN113838869A CN202111113508.9A CN202111113508A CN113838869A CN 113838869 A CN113838869 A CN 113838869A CN 202111113508 A CN202111113508 A CN 202111113508A CN 113838869 A CN113838869 A CN 113838869A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 54
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- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 142
- 239000010408 film Substances 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 8
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- 230000008878 coupling Effects 0.000 description 8
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- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
The embodiment of the first aspect of the application provides a display panel, a manufacturing method thereof and a display device. The display panel comprises a substrate base plate and a plurality of pixel units arranged on the substrate base plate, wherein each pixel unit comprises a thin film transistor, a pixel electrode connected with the thin film transistor and a common electrode arranged opposite to the pixel electrode in the thickness direction of the display panel, the thin film transistor comprises a grid electrode, a semiconductor active layer, a first pole and a second pole, the pixel electrode is connected with the first pole or the second pole, and the pixel electrode and the grid electrode are arranged on the same layer. In the manufacturing process of the display panel in the embodiment of the application, the pixel electrode and the grid electrode can be simultaneously manufactured through the same mask plate. In the related art, in the display panel manufacturing process, the pixel electrode and the gate electrode are respectively manufactured by one mask plate. Compared with the display panel in the related art, the display panel in the embodiment of the application can save one mask plate during manufacturing, and the manufacturing cost of the display panel can be reduced.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, and a display device.
Background
This section provides background information related to the present application and is not necessarily prior art.
With the continuous development of display panel technology, the display panel industry is more and more competitive, which enables manufacturers to continuously explore new technologies or new technologies to maintain market competitiveness. This technical competition and innovation is particularly reflected in high resolution, high color gamut, low power consumption, low cost, etc.
The organic film 6mask process in the related art is a mature display panel manufacturing process. As the name suggests, 6mask plates are needed in the process, so that the manufacturing cost of the display panel is high. How to reduce the manufacturing cost of the display panel is a problem to be solved at present.
Disclosure of Invention
An object of the present invention is to provide a display panel, a manufacturing method thereof, and a display device, which can reduce the manufacturing cost of the display panel. The specific technical scheme is as follows:
embodiments of a first aspect of the present application propose a display panel. The display panel comprises a substrate base plate and a plurality of pixel units arranged on the substrate base plate, wherein each pixel unit comprises a thin film transistor, a pixel electrode connected with the thin film transistor and a common electrode arranged opposite to the pixel electrode in the thickness direction of the display panel, the thin film transistor comprises a grid electrode, a semiconductor active layer, a first pole and a second pole, the pixel electrode is connected with the first pole or the second pole, and the pixel electrode and the grid electrode are arranged on the same layer.
In some embodiments of the present application, the display panel further includes gate lines and data lines arranged in a crisscross manner, the data lines are connected to one of the first pole and the second pole, the data lines are arranged in the same layer as the first pole and the second pole, the gate lines are connected to the gate electrodes, and the gate lines are arranged in the same layer as the gate electrodes.
In some embodiments of the present application, the display panel further includes an anti-interference film layer disposed between the gate line and the common electrode, and the anti-interference film layer is further disposed between the data line and the common electrode.
In some embodiments of the present application, the interference preventing film layer is not present in a region between the pixel electrode and the common electrode.
In some embodiments of the present application, the tamper-proof film layer is made of a material having a dielectric constant between 3 and 7.
In some embodiments of the present application, the display panel further includes a gate insulating layer disposed between the gate electrode and the semiconductor active layer, and the gate insulating layer is disposed to cover the pixel electrode.
In some embodiments of the present application, the display panel further includes a protective layer disposed between the gate insulating layer and the common electrode and covering the interference preventing film layer.
In some embodiments of the present application, a via hole is disposed on the gate insulating layer, and the pixel electrode is connected to the first pole or the second pole through the via hole.
The embodiment of the second aspect of the present application provides a manufacturing method of a display panel. The method for manufacturing the display panel comprises the following steps:
providing a substrate base plate;
forming a grid electrode and a pixel electrode of a thin film transistor on the substrate, and forming a grid line connected with the grid electrode, wherein the grid electrode, the grid line and the pixel electrode are arranged in the same layer;
manufacturing a semiconductor active layer, a first pole, a second pole and a data line of the thin film transistor;
and manufacturing a common electrode which is arranged opposite to the pixel electrode in the thickness direction of the display panel.
In some embodiments of the present application, after forming the gate electrode and the pixel electrode of the thin film transistor on the substrate, and forming the gate line connected to the gate electrode, the method further includes:
and manufacturing a grid insulation layer covering the grid, the pixel electrode and the grid line.
In some embodiments of the present application, after the fabricating the semiconductor active layer, the first electrode, the second electrode, and the data line of the thin film transistor, the method further includes:
and manufacturing an anti-interference film layer, wherein the anti-interference film layer is positioned between the grid line and the common electrode and between the data line and the common electrode, and the anti-interference film layer does not exist in the area between the pixel electrode and the common electrode.
In some embodiments of the present application, the fabricating an interference preventing film layer between the gate line and the common electrode and between the data line and the common electrode, and the interference preventing film layer being absent in a region between the pixel electrode and the common electrode, includes:
forming an anti-interference film layer on the gate insulating layer, wherein the anti-interference film layer covers the first pole, the second pole, the semiconductor active layer and the data line;
and etching away the part of the interference preventing film layer between the pixel electrode and the common electrode.
Embodiments of a third aspect of the present application provide a display device. The display device comprises the display panel in the embodiment of the first aspect.
The embodiment of the application has the following beneficial effects:
the embodiment of the application provides a display panel, a manufacturing method thereof and a display device. The display panel includes a substrate base plate and a plurality of pixel units disposed on the substrate base plate, and the pixel units include thin film transistors, pixel electrodes, and a common electrode. The pixel electrode and the grid electrode in the thin film transistor are arranged in the same layer. Therefore, in the manufacturing process of the display panel in the embodiment of the application, the pixel electrode and the gate electrode can be simultaneously manufactured through the same mask plate. In the related art, in the display panel manufacturing process, the pixel electrode and the gate electrode are respectively manufactured by one mask plate. Therefore, compared with the display panel in the related art, the display panel in the embodiment of the application can save one mask plate during manufacturing, so that the manufacturing cost of the display panel can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and it is also obvious for a person skilled in the art to obtain other embodiments according to the drawings.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view taken along section A-A of FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along section B-B of FIG. 1;
fig. 4 is a schematic flow chart illustrating a manufacturing method of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the description herein are intended to be within the scope of the present disclosure.
As shown in fig. 1, fig. 2 and fig. 3, an embodiment of the first aspect of the present application proposes a display panel 10. The display panel 10 includes a substrate base 100 and a plurality of pixel units disposed on the substrate base 100. Specifically, the pixel unit includes a thin film transistor 200, a pixel electrode 300 connected to the thin film transistor 200, and a common electrode 400 disposed opposite to the pixel electrode 300 in a thickness direction of the display panel 10, wherein the thin film transistor 200 includes a gate electrode 210, a semiconductor active layer 220, a first pole 230, and a second pole 240, the pixel electrode 300 is connected to the first pole 230 or the second pole 240, and the pixel electrode 300 and the gate electrode 210 are disposed in the same layer.
According to the display panel 10 in the embodiment of the present application, it includes the substrate 100 and a plurality of pixel units disposed on the substrate 100, the pixel units including the thin film transistors 200, the pixel electrodes 300, and the common electrode 400. The pixel electrode 300 and the gate electrode 210 in the thin film transistor 200 are disposed in the same layer. Therefore, in the manufacturing process of the display panel 10 in the embodiment of the present application, the pixel electrode 300 and the gate electrode 210 can be simultaneously manufactured by using the same mask. In the related art display panel manufacturing process, the pixel electrode 300 and the gate electrode 210 are respectively manufactured by a mask plate. Therefore, compared with the display panel in the related art, the display panel in the embodiment of the present application can save one mask plate during the manufacturing process, thereby reducing the manufacturing cost of the display panel 10.
It will be appreciated that the first pole 230 is one of a source and a drain, and correspondingly, the second pole 240 is the other of a source and a drain. Specifically, of the first and second electrodes 230 and 240, one connected to the pixel electrode 300 is a drain electrode.
In some embodiments of the present application, the display panel 10 further includes gate lines 500 and data lines 600 arranged in a crisscross manner, and two adjacent gate lines 500 and two adjacent data lines 600 together define a pixel region on the display panel 10. Specifically, the data line 600 is connected to one of the first and second poles 230 and 240, and the data line 600 is disposed in the same layer as the first and second poles 230 and 240; the gate line 500 is connected to the gate electrode 210, and the gate line 500 and the gate electrode 210 are disposed at the same layer. In the embodiment of the present invention, the gate line 500 is connected to the gate 210, and the gate line 500 and the gate 210 are disposed on the same layer, so that the gate line 500 and the gate 210 can also be manufactured by using the same mask plate, and the gate 210 and the pixel electrode 300 can be manufactured by using one mask plate, and thus it can be known that the gate 210, the gate line 500, and the pixel electrode 300 can be manufactured on the same layer by using the same mask plate. In addition, in the present embodiment, the data line 600, the first pole 230, and the second pole 240 are disposed on the same layer, and therefore, the data line 600, the first pole 230, and the second pole 240 can also be manufactured by the same mask.
In some embodiments of the present invention, the display panel 10 further includes an anti-interference film layer 700, the anti-interference film layer 700 being disposed between the gate line 500 and the common electrode 400, and the anti-interference film layer 700 being further disposed between the data line 600 and the common electrode 400. In the embodiment of the present application, the anti-interference film layer 700 is disposed between the gate line 500 and the common electrode 400, which is beneficial to reducing the coupling capacitance between the gate line 500 and the common electrode 400, thereby reducing the load of the gate line 500, reducing the power consumption, and reducing the adverse display effect caused by the coupling capacitance. Similarly, the interference prevention film layer 700 is disposed between the data line 600 and the common electrode 400, which is beneficial to reducing the coupling capacitance between the data line 600 and the common electrode 400, thereby reducing the load of the data line 600, reducing the power consumption, and in addition, reducing the display adverse effect caused by the coupling capacitance.
Further, the interference preventing film layer 700 is not present in the region between the pixel electrode 300 and the common electrode 400, so that the thickening of the insulating layer between the pixel electrode 300 and the common electrode 400 due to the arrangement of the interference preventing film layer 700 can be avoided, and thus, the storage capacitance between the pixel electrode 300 and the common electrode 400 is not affected, and further, the change of the pixel driving voltage is avoided.
In some embodiments of the present application, the tamper-proof film layer 700 is made of a material having a dielectric constant between 3 and 7. Through experimental verification, the interference preventing film layer 700 made of a material having a dielectric constant within the above range may significantly reduce the coupling capacitance between the gate line 500 and the common electrode 400 when disposed between the gate line 500 and the common electrode 400. Also, the interference preventing film layer 700, which is made of a material having a dielectric constant within the above-described range, may significantly reduce the coupling capacitance between the data line 600 and the common electrode 400 when disposed between the data line 600 and the common electrode 400. Specifically, the interference prevention film 700 in this embodiment may be an organic material film, a silicon nitride film, or a silicon oxide film.
In some embodiments of the present application, the display panel 10 further includes a gate insulating layer 800 disposed between the gate electrode 210 and the semiconductor active layer 220, and the gate insulating layer 800 is disposed to cover the pixel electrode 300. In the present embodiment, since the gate insulating layer 800 is disposed on the same layer as the pixel electrode 300, and the gate insulating layer 800 usually covers the gate electrode 210, the gate insulating layer 800 in the present embodiment also covers the pixel electrode 300.
In some embodiments of the present application, the display panel 10 further includes a protective layer 900, and the protective layer 900 is disposed between the gate insulating layer 800 and the common electrode 400 and covers the interference preventing film layer 700. The protection layer 900 is also called a Passivation layer (PVX) and is used to protect the semiconductor active layer 220, the first and second electrodes 230 and 240, and the interference prevention film 700, so as to inhibit or prevent a chemical reaction, such as an oxidation reaction, from occurring on the surface of the related structure.
In some embodiments of the present application, a via hole is disposed on the gate insulating layer 800, and the pixel electrode 300 is connected to the first pole 230 or the second pole 240 through the via hole. In the present embodiment, since the pixel electrode 300 and the gate electrode are disposed at the same layer, and the pixel electrode 300 is covered by the gate insulating layer 800, a via hole may be formed on the gate insulating layer 800, and the first electrode 230 or the second electrode 240 of the semiconductor transistor 200 and the pixel electrode 300 are connected by the via hole.
In order to better understand the beneficial effects of the present application, the following takes a 6mask process in the related art as an example to illustrate the improvement of the display panel in the embodiment of the present application in the manufacturing process. In the related art, the display panel 10 may be manufactured by HADS (High Advanced Super Dimension Switch, Advanced Super Dimension field switching with High aperture ratio), and the manufacturing process flow is as follows: a gate electrode 210, a gate insulating layer, a semiconductor active layer, a pixel electrode, a source drain layer, a passivation layer, and a common electrode are sequentially formed on the glass substrate. Specifically, different layers are manufactured on a glass substrate by using an HTM (half tone mask, semi-permeable membrane is also called as a mask) process, and in the manufacturing process of the display panel in the related art, six masks are required, wherein the first mask is used for forming a gate 210 on the glass substrate, the second mask is used for forming a semiconductor active layer and a source drain, the third mask is used for forming a semiconductor organic layer (relative to an anti-interference film layer), the fourth mask is used for forming a pixel electrode, the fifth mask is used for forming a passivation layer, and the sixth mask is used for forming a common electrode.
In the embodiment of the present invention, since the pixel electrode 300 and the gate 210 in the thin film transistor 200 are disposed on the same layer, the pixel electrode 300 and the gate 210 can be simultaneously manufactured by using one mask, and thus, in the embodiment, only five mask plates are required, where a first mask plate is used to form the gate 210 and the pixel electrode 300 on the glass substrate, a second mask plate is used to form the semiconductor active layer 220 and the source/drain electrodes (the first electrode 230 and the second electrode 240), a third mask plate is used to form the interference prevention film layer 700, a fourth mask plate is used to form the protection layer 900 (also referred to as a passivation layer), and a fifth mask plate is used to form the common electrode 400. Therefore, compared with the display panel 10 manufactured by using six mask plates in the related art, the display panel manufacturing method has better economic benefits so as to improve the competitive advantage of products.
As shown in fig. 4, in an embodiment of the second aspect of the present application, a manufacturing method of the display panel 10 is provided, where the manufacturing method includes the following steps:
step S101: providing a substrate base plate 100;
step S201: forming a gate electrode 210 and a pixel electrode 300 of the thin film transistor 200 and a gate line 500 connected to the gate electrode 210 on the substrate 100, wherein the gate electrode 210, the gate line 500 and the pixel electrode 300 are in the same layer;
step S301: manufacturing the semiconductor active layer 220, the first electrode 230, the second electrode 240 and the data line 600 of the thin film transistor 200;
step S401: the common electrode 400 is formed to be opposed to the pixel electrode 300 in the thickness direction of the display panel 10.
According to the manufacturing method of the display panel 10 in the embodiment of the present application, the gate electrode 210 and the pixel electrode 300 of the thin film transistor 200 are firstly manufactured on the provided substrate 100, and the gate line 500 connected to the gate electrode 210 is formed, wherein the gate electrode 210, the gate line 500 and the pixel electrode 300 are disposed in the same layer, then the semiconductor active layer 220, the first electrode 230, the second electrode 240 and the data line 600 of the thin film transistor 200 are manufactured, and finally, the common electrode 400 disposed opposite to the pixel electrode 300 in the thickness direction of the display panel 10 is manufactured. In the embodiment, the gate 210, the gate line 500, and the pixel electrode 300 of the thin film transistor 200 are disposed on the same layer, so that compared with the related process, the gate 210, the gate line 500, and the pixel electrode 300 can be manufactured by using the same mask, and compared with the manufacturing process of the display panel in the related art, one mask can be reduced in the present application, so as to reduce the manufacturing cost of the display panel 10.
In some embodiments of the present application, the substrate base material is sapphire. The main component of sapphire is alumina (Al)2O3). Of course, in other embodiments, the material of the substrate base material may also be silicon carbide (SiC), gallium nitride (GaN), or silicon.
In some application embodiments of the present application, after the steps of forming the gate electrode 210 and the pixel electrode of the thin film transistor on the substrate and forming the gate line connected to the gate electrode 210, the method further includes:
a gate insulating layer 800 covering the gate electrode 210, the pixel electrode 300, and the gate line 500 is manufactured.
In some embodiments of the present application, after the steps of fabricating the semiconductor active layer 220, the first electrode 230, the second electrode 240, and the data line 600 of the thin film transistor, the steps further include:
the interference preventing film layer 700 is fabricated such that the interference preventing film layer 700 is positioned between the gate line 500 and the common electrode 400 and between the data line 600 and the common electrode 400, and the interference preventing film layer 700 does not exist in a region between the pixel electrode 300 and the common electrode 400.
In the present embodiment, after the semiconductor active layer 220, the first electrode 230, the second electrode 240, and the data line 600 of the thin film transistor 200 are fabricated, the anti-interference film layer 700 is fabricated, and in the finally formed display panel 10, the anti-interference film layer 700 is located between the gate line 500 and the common electrode 400 and between the data line 600 and the common electrode 400, which is beneficial to reducing the coupling capacitance between the gate line 500 and the common electrode 400 and between the data line 600 and the common electrode 400, thereby reducing the load of the gate line 500 and the load of the data line 600 and reducing power consumption. In addition, the display adverse effect due to the coupling capacitance can be reduced. On the other hand, during the manufacturing process, it is also ensured that no anti-interference film layer 700 exists in the region between the pixel electrode 300 and the common electrode 400, so that the increase of the insulating layer between the pixel electrode 300 and the common electrode 400 due to the arrangement of the anti-interference film layer 700 can be avoided, and therefore, the storage capacitance between the pixel electrode 300 and the common electrode 400 is not affected, and further, the change of the pixel driving voltage is avoided.
In some embodiments of the present application, the fabricating the interference preventing film layer 700, the interference preventing film layer 700 being between the gate line 500 and the common electrode 400 and between the data line 600 and the common electrode 400, and the step of having no interference preventing film layer in a region between the pixel electrode 300 and the common electrode 400 further includes:
forming an interference preventing film 700 on the gate insulating layer 800, the interference preventing film 700 covering the first and second electrodes 230 and 240, the semiconductor active layer 220, and the data line 600;
a portion of the interference preventing film layer 700 between the pixel electrode 300 and the common electrode 400 is etched away.
In the embodiment of the present invention, the anti-interference film 700 covering the first electrode 230, the second electrode 240, the semiconductor active layer 220 and the data line 600 may be formed on the gate insulating layer 800, and then a portion of the anti-interference film 700 between the pixel electrode 300 and the common electrode 400 may be etched away, thereby ensuring that the anti-interference film 700 does not exist in a region between the pixel electrode 300 and the common electrode 400.
An embodiment of the third aspect of the present application proposes a display device, which includes the display panel 10 in any of the embodiments of the first aspect.
According to the display device in the embodiment of the present application, the display device includes the display panel 10 in any one of the embodiments of the first aspect described above. The display panel 10 includes a substrate 100 and a plurality of pixel units disposed on the substrate 100, the pixel units including a thin film transistor 200, a pixel electrode 300, and a common electrode 400. The pixel electrode 300 and the gate electrode 210 in the thin film transistor 200 are disposed in the same layer. Therefore, in the manufacturing process of the display panel 10 in the embodiment of the present application, the pixel electrode 300 and the gate electrode 210 can be simultaneously manufactured by using the same mask. In the related art display panel manufacturing process, the pixel electrode 300 and the gate electrode 210 are respectively manufactured by a mask plate. Therefore, compared with the display panel in the related art, the display panel in the embodiment of the present application can save one mask plate during the manufacturing process, thereby reducing the manufacturing cost of the display panel 10.
It is understood that, in the case where the manufacturing cost of the display panel 10 is reduced, the manufacturing cost of the display device in the embodiment of the present application can also be reduced.
The display device in this embodiment may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (13)
1. A display panel is characterized by comprising a substrate base plate and a plurality of pixel units arranged on the substrate base plate, wherein each pixel unit comprises a thin film transistor, a pixel electrode connected with the thin film transistor and a common electrode arranged opposite to the pixel electrode in the thickness direction of the display panel, the thin film transistor comprises a grid electrode, a semiconductor active layer, a first pole and a second pole, the pixel electrode is connected with the first pole or the second pole, and the pixel electrode and the grid electrode are arranged on the same layer.
2. The display panel according to claim 1, further comprising gate lines and data lines arranged in a crisscross manner, wherein the data lines are connected to one of the first and second poles, the data lines are arranged in the same layer as the first and second poles, the gate lines are connected to the gate electrodes, and the gate lines are arranged in the same layer as the gate electrodes.
3. The display panel according to claim 2, wherein the display panel further comprises an interference preventing film layer disposed between the gate line and the common electrode, and the interference preventing film layer is further disposed between the data line and the common electrode.
4. The display panel according to claim 3, wherein the interference preventing film layer is not present in a region between the pixel electrode and the common electrode.
5. The display panel of claim 3, wherein the tamper film layer is made of a material having a dielectric constant between 3 and 7.
6. The display panel according to claim 3, wherein the display panel further comprises a gate insulating layer provided between a gate electrode and the semiconductor active layer, and wherein the gate insulating layer is provided so as to cover the pixel electrode.
7. The display panel according to claim 6, further comprising a protective layer disposed between the gate insulating layer and the common electrode and covering the interference preventing film layer.
8. The display panel according to claim 6, wherein a via hole is provided in the gate insulating layer, and the pixel electrode is connected to the first pole or the second pole through the via hole.
9. A method for manufacturing a display panel is characterized by comprising the following steps:
providing a substrate base plate;
forming a grid electrode and a pixel electrode of a thin film transistor on the substrate, and forming a grid line connected with the grid electrode, wherein the grid electrode, the grid line and the pixel electrode are arranged in the same layer;
manufacturing a semiconductor active layer, a first pole, a second pole and a data line of the thin film transistor;
and manufacturing a common electrode which is arranged opposite to the pixel electrode in the thickness direction of the display panel.
10. The method of manufacturing a liquid crystal display device according to claim 9, wherein after the forming of the gate electrode and the pixel electrode of the thin film transistor on the substrate and the forming of the gate line connected to the gate electrode, further comprising:
and manufacturing a grid insulation layer covering the grid, the pixel electrode and the grid line.
11. The method of claim 10, further comprising, after the step of forming the semiconductor active layer, the first electrode, the second electrode, and the data line of the thin film transistor:
and manufacturing an anti-interference film layer, wherein the anti-interference film layer is positioned between the grid line and the common electrode and between the data line and the common electrode, and the anti-interference film layer does not exist in the area between the pixel electrode and the common electrode.
12. The method of manufacturing according to claim 11, wherein the manufacturing of the interference preventing film layer, which is located between the gate line and the common electrode and between the data line and the common electrode, and which is absent in a region between the pixel electrode and the common electrode, comprises:
forming an anti-interference film layer on the gate insulating layer, wherein the anti-interference film layer covers the first pole, the second pole, the semiconductor active layer and the data line;
and etching away the part of the interference preventing film layer between the pixel electrode and the common electrode.
13. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
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| CN101299122A (en) * | 2007-04-30 | 2008-11-05 | Lg.菲利浦Lcd株式会社 | Liquid crystal display panel and manufacture method thereof |
| CN202421681U (en) * | 2011-10-17 | 2012-09-05 | 京东方科技集团股份有限公司 | Pixel unit, array substrate, liquid crystal panel and display device |
| CN106896602A (en) * | 2017-03-14 | 2017-06-27 | 上海中航光电子有限公司 | Array base palte, display panel, display device and preparation method |
| CN109856870A (en) * | 2019-03-28 | 2019-06-07 | 惠科股份有限公司 | Display panel and display device |
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| CN101299122A (en) * | 2007-04-30 | 2008-11-05 | Lg.菲利浦Lcd株式会社 | Liquid crystal display panel and manufacture method thereof |
| CN202421681U (en) * | 2011-10-17 | 2012-09-05 | 京东方科技集团股份有限公司 | Pixel unit, array substrate, liquid crystal panel and display device |
| CN106896602A (en) * | 2017-03-14 | 2017-06-27 | 上海中航光电子有限公司 | Array base palte, display panel, display device and preparation method |
| CN109856870A (en) * | 2019-03-28 | 2019-06-07 | 惠科股份有限公司 | Display panel and display device |
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