CN113838834A - Semiconductor device, method for forming semiconductor device, and three-dimensional memory - Google Patents

Semiconductor device, method for forming semiconductor device, and three-dimensional memory Download PDF

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CN113838834A
CN113838834A CN202111110706.XA CN202111110706A CN113838834A CN 113838834 A CN113838834 A CN 113838834A CN 202111110706 A CN202111110706 A CN 202111110706A CN 113838834 A CN113838834 A CN 113838834A
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opening
dielectric layer
layer
semiconductor device
dielectric
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CN113838834B (en
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邹欣伟
石艳伟
邵铸
李威
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device, a method for forming the semiconductor device and a three-dimensional memory, wherein the method for forming the semiconductor device comprises the following steps: providing a substrate, wherein a first dielectric layer is formed on the substrate; forming an opening in the first dielectric layer; forming a second dielectric layer on the side wall of the opening, wherein the dielectric coefficient of the second dielectric layer is greater than that of the first dielectric layer; the opening is filled with a metal layer. According to the invention, the second dielectric layer with a larger dielectric coefficient is added between the first dielectric layer and the metal layer, so that the second dielectric layer and the first dielectric layer are compounded to be used as an actual insulating isolation layer, the VBD and TDDB performances of the insulating isolation layer are improved, and the reliability of the semiconductor device is improved.

Description

Semiconductor device, method for forming semiconductor device, and three-dimensional memory
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for forming the semiconductor device, and a three-dimensional memory.
Background
With the rapid development of integrated circuit manufacturing technology, people have higher and higher requirements on the integration level and performance of integrated circuits, and the feature size of corresponding semiconductor devices is also continuously reduced. In the conventional integrated circuit, the electrical connection in the semiconductor device is realized by the interconnection structure, and as the feature size is continuously reduced, the size of the interconnection structure is also reduced, and accordingly, the distance between interconnection lines constituting the interconnection structure is also reduced.
However, as the distance between the interconnection lines becomes shorter, the Time Dependent Dielectric Breakdown (TDDB) and Voltage Breakdown (VBD) performance of the dielectric layer cannot be satisfied, and the probability of dielectric layer breakdown increases. This may reduce the lifetime and reliability of the semiconductor device, and if the dielectric layer breaks down, the dielectric isolation of the dielectric layer may be lost, which may cause signal crosstalk and even short circuits in the semiconductor device, which may seriously affect the performance of the semiconductor device.
Therefore, the prior art has defects and needs to be improved and developed.
Disclosure of Invention
The invention provides a semiconductor device, a forming method of the semiconductor device and a three-dimensional memory, which effectively improve the reliability of the conventional semiconductor device.
In a first aspect, the present invention provides a semiconductor device comprising:
a substrate; a first dielectric layer on the substrate, the first dielectric layer having an opening formed therein; the second dielectric layer covers the side wall of the opening, and the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer; and the metal layer is filled in the opening.
Wherein the semiconductor device further comprises: and the transition layer is positioned on the surface of the second dielectric layer and the bottom surface of the opening.
Wherein the opening comprises a first sub-opening and a second sub-opening which are communicated with each other; the metal layer comprises a metal contact layer located in the first sub-opening and a metal interconnection layer located in the second sub-opening.
In a second aspect, the present invention provides a method of forming a semiconductor device, comprising: providing a substrate, wherein a first dielectric layer is formed on the substrate; forming an opening in the first dielectric layer; forming a second dielectric layer on the side wall of the opening, wherein the dielectric coefficient of the second dielectric layer is greater than that of the first dielectric layer; and filling a metal layer in the opening.
Wherein, the forming a second dielectric layer on the sidewall of the opening includes: depositing the second dielectric layer on the surface of the first dielectric layer, the bottom surface and the side wall of the opening; and removing the redundant second dielectric layer except the second dielectric layer on the side wall of the opening.
Removing the redundant second dielectric layer except the second dielectric layer on the side wall of the opening comprises the following steps: and anisotropically etching the second dielectric layer along the thickness direction of the substrate to remove the redundant second dielectric layers on the surface of the first dielectric layer and the bottom surface of the opening and retain the second dielectric layers on the side wall of the opening.
Wherein the opening comprises a first sub-opening and a second sub-opening; the filling of the metal layer in the opening includes: and filling the metal layer in the opening to form a metal contact layer and a metal interconnection layer in the first sub-opening and the second sub-opening respectively.
Wherein the filling of the metal layer in the opening includes: forming the metal layer on the surface of the first dielectric layer and in the opening; and removing the metal layer outside the opening by adopting a planarization process.
Wherein, after forming the second dielectric layer on the sidewall of the opening, the method further comprises: and forming a transition layer on the surface of the second dielectric layer and the bottom surface of the opening.
In a third aspect, the present invention further provides a three-dimensional memory including a memory cell array and a peripheral circuit, wherein the peripheral circuit includes the semiconductor device according to any one of the above-described embodiments.
The invention has the beneficial effects that: different from the prior art, the semiconductor device, the forming method of the semiconductor device and the three-dimensional memory provided by the invention have the advantages that the opening is formed in the first dielectric layer, the second dielectric layer is formed on the side wall of the opening, the metal layer is filled in the opening, the second dielectric layer and the first dielectric layer are compounded to be used as the actual insulating isolation layer, and the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer, so that the VBD and TDDB performances corresponding to the insulating isolation layer are improved, and the reliability of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.
Fig. 1 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 2 is a flow chart of another method for forming a semiconductor device according to an embodiment of the present invention;
fig. 3 is a flow chart of a method for forming a semiconductor device according to another embodiment of the present invention;
fig. 4a to 4g are schematic cross-sectional views of stages in forming a semiconductor device according to an embodiment of the present invention.
Fig. 5a to 5c are schematic cross-sectional views of stages in forming another semiconductor device according to an embodiment of the present invention.
FIG. 6 is a schematic diagram of a semiconductor device according to the present invention;
fig. 7 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention, and the specific flow of the method for forming the semiconductor device may be as follows:
step S101: a substrate is provided, and a first dielectric layer is formed on the substrate.
Fig. 4a shows a schematic cross-sectional structure after step S101 is completed.
Specifically, the substrate 10 may be made of a semiconductor material such as Silicon, germanium, or Silicon-On-Insulator (SOI)The material of the first dielectric layer 11 may be an oxide or a nitride, and specifically may be a silicon oxide or a silicon nitride. Specifically, when the material of the substrate 10 is silicon and the material of the first dielectric layer 11 is silicon oxide, the formation process of the first dielectric layer 11 on the substrate 10 is preferably a Chemical Vapor Deposition (CVD) process, and further, in the CVD process, Tetraethylorthosilicate (TEOS)/ozone (O) is used3) The system is used for depositing the silicon oxide film, and in the deposition process, because the viscosity coefficients of TEOS and silicon oxide are low, the silicon substrate has excellent covering capacity, and the formed silicon oxide film has good uniformity. The first dielectric layer 11 may also be a material with a dielectric coefficient smaller than that of silicon oxide (the dielectric coefficient K of silicon oxide is 3.9), i.e. a low-K dielectric material, which may be SiO2SiOF, SiCOH, SiCO, or SiCON.
Step S102, an opening is formed in the first dielectric layer.
Fig. 4b shows a schematic cross-sectional structure diagram after step S102 is completed.
Specifically, the aspect ratio of the opening 110 is generally 3: 1 or 4: 1 groove with high depth-width ratio. In this embodiment, the opening 110 may be formed by etching using an anisotropic etching method, for example, dry etching, for example, plasma etching, reactive ion etching, or the like, and the first dielectric layer 11 is etched from top to bottom to form the opening 110, it should be noted that, while the opening 110 is formed in the first dielectric layer 11, the first dielectric layer 11 may be selectively etched through, so that the substrate 10 is exposed, and at this time, the metal layer filled in the opening 110 also serves to be electrically connected to the source/drain in the substrate 10. In other embodiments, an etching barrier layer (not shown) is further formed on the substrate 10, and the etching barrier layer is used to protect the device structure in the substrate during the process of forming the opening 110, and the material of the etching barrier layer is SiN.
In the present embodiment, when the first dielectric layer 11 on the substrate 10 is silicon oxide, trifluoromethane (CHF) is used3) With chlorine (Cl)2) The mixed plasma is used for etching silicon oxide, wherein CHF3With a better selection ratio, canWhen the first dielectric layer 11 is made of silicon oxide, the opening 110 with a high aspect ratio is etched.
Step S103, a second dielectric layer is formed on the side wall of the opening.
Fig. 4d shows a schematic cross-sectional structure diagram after step S103 is completed.
In this embodiment, since the material of the first dielectric layer 11 may be silicon oxide or a material with a dielectric constant smaller than the dielectric constant K of silicon oxide, the second dielectric layer 12 is selected to be a material with a dielectric constant greater than 3.9 (i.e. a high-K dielectric layer), specifically selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO, in this embodiment, the second dielectric layer 12 is preferably HfO2. The second dielectric layer 12 and the first dielectric layer 11 are compounded to be used as an actual insulating isolation layer, and on the basis of the first dielectric layer 11, the second dielectric layer 12 with a larger dielectric coefficient is added, so that the VBD and TDDB performances corresponding to the actual insulating isolation layer are improved, and the reliability of the semiconductor device is improved.
Referring to fig. 2, fig. 2 is a flowchart of another method for forming a semiconductor device according to an embodiment of the present invention, where the step S103 may further include the following steps:
and S1031, depositing the second dielectric layer on the surface of the first dielectric layer, the bottom surface and the side wall of the opening.
Fig. 4c shows a schematic cross-sectional structure diagram after step S1031 is completed.
Specifically, in this embodiment, the second dielectric layer 12 is preferably deposited on the bottom surface and the sidewall of the opening 110 and the first dielectric layer 11 by an atomic layer deposition process, and the second dielectric layer 12 with a more uniform thickness can be formed on the first dielectric layer 11 by the atomic layer deposition process compared with a physical or chemical vapor deposition process. It is further preferred that the second dielectric layer 12 is deposited to a thickness in the range of 3nm to 5 nm.
Step 1032 is removing excess second dielectric layer except for the second dielectric layer on the sidewalls of the opening.
Fig. 4d shows a schematic cross-sectional structure diagram after step S1032 is completed. In this embodiment, the second dielectric layer 12 is to enhance the isolation and insulation of the first dielectric layer 11 to the metal interconnection lines between the layers, so that only the second dielectric layer on the sidewall of the opening 110 needs to be retained, and the excess second dielectric layer 12 except the second dielectric layer 12 on the sidewall of the opening 110 needs to be removed, thereby preventing the second dielectric layer 12 on the bottom surface of the opening 110 from affecting the metal contact or the conductive connection of the metal interconnection line subsequently filled in the opening 110. Wherein, step S1032 may be implemented by the following steps: and anisotropically etching the second dielectric layer along the thickness direction of the substrate to remove the redundant second dielectric layer on the surface of the first dielectric layer and the bottom surface of the opening and retain the second dielectric layer on the side wall of the opening.
As shown in fig. 4c, the second dielectric layer 12 is anisotropically etched along the thickness direction of the substrate 10, i.e., the y direction in fig. 4c, for example, the second dielectric layer 12 is etched from top to bottom by dry etching, e.g., plasma etching, reactive ion etching, etc., until the second dielectric layer 12 on the surface of the first dielectric layer 11 and the bottom surface 112 of the opening 110 are completely etched.
It should be noted that, since the second dielectric layer 12 is uniformly covered on the surfaces of the first dielectric layer 11 and the opening 110 by the atomic layer deposition process, the thickness of the second dielectric layer 12 distributed along the surfaces of the first dielectric layer 11 and the opening 110 is the same. When the second dielectric layer 12 on the surface of the first dielectric layer 11 and the bottom surface 112 of the opening 110 is completely etched away along the thickness direction of the substrate 10, the second dielectric layer 12 on the sidewall 111 is remained because the depth of the second dielectric layer 12 distributed on the sidewall 111 along the thickness direction of the substrate 10 is much greater than the thickness of the second dielectric layer 12 distributed along the surface of the first dielectric layer 11 and the bottom surface 112.
Step S105, filling a metal layer in the opening.
Fig. 4f shows a schematic cross-sectional structure after step S105 is completed.
Specifically, in this embodiment, the metal layer 13 is one of tungsten or copper material or a combination of the two. When the metal layer 13 is a copper layer, the metal layer 13 may be formed in the opening by a copper reflow process, specifically, a copper seed layer may be formed on the surface of the opening 110, and then the copper seed layer is heated to agglomerate the copper seed layer in the opening 110 to form the metal layer.
Referring to fig. 2, the step S105 further includes:
step S1051, forming the metal layer on the surface of the first dielectric layer and in the opening.
Fig. 4e shows a schematic cross-sectional structure diagram after step S1051 is completed.
In step S1052, a planarization process is used to remove the metal layer outside the opening.
Wherein, the planarization process is chemical mechanical polishing or etching back. More of the metal layer 13 outside the opening 110 in fig. 4e is removed by a planarization process to make the surface of the metal layer 13 level with the surface of the first dielectric layer 11 in preparation for the next interconnect layer.
Referring to fig. 3, fig. 3 is a flowchart illustrating a method for forming a semiconductor device according to another embodiment of the present invention, and as shown in fig. 3, after step 103, the method further includes:
and step S104, forming a transition layer on the surface of the second dielectric layer and the bottom surface of the opening.
In this embodiment, in consideration of the diffusion effect of metal, especially when the substrate 10 and the first dielectric layer 11 are silicon-based materials, when the metal layer 13 is copper, the copper is easily diffused into the silicon-based materials, thereby damaging the electrical properties of the semiconductor device, and therefore, please refer to fig. 4g, which is a schematic cross-sectional structure diagram of the semiconductor device formed after adding the transition layer. As shown in fig. 4g, a transition layer 14 may be disposed between the copper layer and the dielectric layer to prevent the diffusion of copper in the first dielectric layer 11, wherein the material of the transition layer 14 may be one of tantalum nitride (TaN) and tantalum (Ta), and the thickness is preferably between 2nm and 4nm, when the thickness of the transition layer 14 is in the preferred range, the transition layer can better block the diffusion of copper, and at the same time, the resistivity thereof is controlled to be within a suitable range, and a low-resistance ohmic contact is formed with copper, which has a small influence on the electrical characteristics of the semiconductor device. When the metal layer 13 is made of tungsten, the transition layer 14 has a stacked structure of titanium (Ti) and titanium nitride (TiN).
In addition, as shown in fig. 5a to 5c, the forming method is also applicable to a dual damascene process, and particularly refers to a method capable of simultaneously forming an interconnect in a trench and a top-bottom stacked structure of plugs (plugs) in a via, where the top-bottom stacked structure refers to a stacked structure formed by electrically connecting one interconnect with one or more plugs therebelow, and the interconnect and the plugs are used for electrically connecting different elements and wires between layers in a semiconductor device and are isolated from other devices by surrounding dielectric layers.
As shown in fig. 5a, the opening 110 includes a first sub-opening 1101 and a second sub-opening 1102 which are communicated with each other, the first sub-opening 1101 may be a through hole, and the second sub-opening 1102 may be a trench. Specifically, a hard mask layer (not shown) having second sub-openings 1102 may be formed on the first dielectric layer 11, and then a first sub-opening 1101 is formed in the first dielectric layer 11 between the second sub-openings 1102, where the depth of the first sub-opening 1101 is smaller than the thickness of the first dielectric layer 11, the first sub-opening 1101 is located within the range of the second sub-opening 1102, and the hard mask layer is used as a mask to etch the first dielectric layer 11 to form a via and a trench. Thereafter, as shown in fig. 5b, the second dielectric layer 12 is anisotropically etched along the thickness direction of the substrate, so that the surface of the first dielectric layer 11 and the second dielectric layer 12 on the bottom surfaces of the first sub-opening 1101 and the second sub-opening 1102 are all etched, and the second dielectric layer on the sidewalls of the first sub-opening 1101 and the second sub-opening 1102 is remained. As shown in fig. 5c, filling the metal layer 13 in the opening 110 includes: and filling the metal layer in the opening to form a metal contact layer and a metal interconnection layer in the first sub-opening and the second sub-opening respectively.
The first dielectric layer 11 has other multi-layered interconnect structures (not shown in fig. 5a to 5 c) formed therein, wherein the metal contact layer can function to connect the metal interconnect layer with the other multi-layered interconnect structures.
The invention has the beneficial effects that: different from the prior art, the method for forming the semiconductor device provided by the invention has the advantages that the opening is formed in the first dielectric layer, the second dielectric layer is formed on the side wall of the opening, the metal layer is filled in the opening, so that the second dielectric layer and the first dielectric layer are compounded to be used as the actual insulating isolation layer, and the dielectric coefficient of the second dielectric layer is greater than that of the first dielectric layer, so that the VBD and TDDB performances corresponding to the insulating isolation layer are improved, and the reliability of the semiconductor device is improved.
Referring to fig. 4f, the present invention further provides a semiconductor device including a substrate 10, a first dielectric layer 11, a second dielectric layer 12 and a metal layer 13. The first dielectric layer 11 is disposed on the substrate 10, and an opening 110 is formed in the first dielectric layer 11. The second dielectric layer 12 covers the sidewalls 111 of the opening 110. The metal layer 13 is filled in the opening 110.
Specifically, the substrate 10 may be made of semiconductor materials such as Silicon, germanium, or Silicon-On-Insulator (SOI), and the first dielectric layer 11 may be made of oxide or nitride, and specifically may be made of Silicon oxide or Silicon nitride. Specifically, when the material of the substrate 10 is silicon and the material of the first dielectric layer 11 is silicon oxide, the formation process of the first dielectric layer 11 on the substrate 10 is preferably a Chemical Vapor Deposition (CVD) process, and further, in the CVD process, tetraethyl orthosilicate (TEOS)/ozone (O) is used3) The system is used for depositing the silicon oxide film, and in the deposition process, because the viscosity coefficients of TEOS and silicon oxide are low, the silicon substrate has excellent covering capacity, and the formed silicon oxide film has good uniformity. The material of the first dielectric layer 11 may also be a material with a dielectric coefficient smaller than that of silicon oxide (the dielectric coefficient K of silicon oxide is 3.9), that is, a low-K dielectric material with a corresponding dielectric constant smaller than 3, where the low-K dielectric material may be SiO2, SiOF, SiCOH, SiCO, or SiCON.
Specifically, the aspect ratio of the opening 110 is generally 3: 1 or 4: 1 groove with high depth-width ratio. In this embodiment, the opening 110 may be formed by etching using an anisotropic etching method, for example, dry etching, for example, plasma etching, reactive ion etching, or the like, and the first dielectric layer 11 is etched from top to bottom to form the opening 110, it should be noted that, while the opening 110 is formed in the first dielectric layer 11, the first dielectric layer 11 may be selectively etched through, so that the substrate 10 is exposed, and at this time, the metal layer filled in the opening 110 also serves to be electrically connected to the source/drain in the substrate 10. In a specific embodiment, an etching barrier layer (not shown in the figure) is further formed on the substrate 10, and the etching barrier layer is used for protecting the device structure in the substrate during the process of forming the opening 110, and the material of the etching barrier layer is SiN.
In this embodiment, since the material of the first dielectric layer 11 may be silicon oxide or a material with a dielectric constant smaller than the dielectric constant K of silicon oxide, the second dielectric layer 12 is selected to be a material with a dielectric constant greater than 3.9 (i.e. a high-K dielectric layer), specifically selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO, in this embodiment, the second dielectric layer is preferably HfO2. The second dielectric layer 12 and the first dielectric layer 11 are compounded to be used as an actual insulating isolation layer, and on the basis of the first dielectric layer 11, the second dielectric layer 12 with a larger dielectric coefficient is added, so that the VBD and TDDB performances corresponding to the actual insulating isolation layer are improved, and the reliability of the semiconductor device is improved. Specifically, in the present embodiment, the metal layer 13 is one of tungsten and copper layers. When the metal layer 13 is a copper layer, the metal layer 13 can be formed in the opening by a copper reflow process, specifically, a copper seed layer can be formed on the surface of the opening 110, and then the copper seed layer is heated to agglomerate the copper seed layer in the opening 110 to form the metal layer.
The semiconductor device further includes a transition layer disposed on the surfaces of the first dielectric layer 11 and the second dielectric layer 12 and the bottom surface 112 of the opening 110.
In this embodiment, in consideration of the diffusion effect of metal, especially when the substrate 10 and the first dielectric layer 11 are silicon-based materials, when the metal layer 13 is copper, the copper is easily diffused into the silicon-based materials, thereby damaging the electrical properties of the semiconductor device, and therefore, please refer to fig. 4g, which is a schematic cross-sectional structure diagram of the semiconductor device formed after adding the transition layer. As shown in fig. 4g, a transition layer 14 may be disposed between the copper layer and the first dielectric layer 11 to prevent the diffusion of copper in the first dielectric layer 11, wherein the material of the transition layer 14 may be one of tantalum nitride (TaN) and tantalum (Ta), and the thickness is preferably between 2nm and 4nm, when the thickness of the transition layer 14 is in a preferred range, the transition layer can better block the diffusion of copper, and at the same time, the resistivity thereof is controlled to be within a suitable range, and a low-resistance ohmic contact is formed with copper, which has a small influence on the electrical characteristics of the semiconductor device. When the metal layer 13 is made of tungsten, the transition layer 14 has a stacked structure of Ti (titanium) and TiN (titanium nitride).
In addition, as shown in fig. 5c, the semiconductor device is also suitable for a dual damascene structure, and specifically refers to a stacked structure that can simultaneously form an interconnect in a trench and a plug (plug) in a via, where the stacked structure is formed by electrically connecting one interconnect with one or more plugs thereunder, and the interconnect and the plug are used to electrically connect different elements and wires between layers in the semiconductor device and are isolated from other devices by surrounding dielectric layers.
As shown in fig. 5a, the opening 110 includes a first sub opening 1101 and a second sub opening 1102 which are communicated with each other, the first sub opening 1101 corresponds to a position of the through hole, and the second sub opening 1102 corresponds to a position of the trench. As shown in fig. 5b, the second dielectric layer 12 is anisotropically etched along the thickness direction of the substrate 10, such that the second dielectric layer 12 on the surface of the first dielectric layer 11 and the bottom surfaces of the first sub-opening 1101 and the second sub-opening 1102 is completely etched, and the second dielectric layer 12 on the sidewalls of the first sub-opening 1101 and the second sub-opening 1102 is remained.
As shown in fig. 5c, the metal layer 13 filled in the first sub-opening 1101 serves as a metal contact layer, and the metal layer 13 filled in the second sub-opening 1102 serves as a metal interconnection layer.
Referring to fig. 6, fig. 6 shows the first dielectric layer 11 and a device structure, such as a MOS transistor, a multi-layer interconnect structure formed in the substrate 10. Therein, the multilayer interconnect structure 18 is connected not only to the metal layer shown in fig. 4f, but also to the source/drain regions in the substrate 10. As shown in fig. 6, a dielectric isolation layer 15 and a polysilicon gate 17 are also formed in the first dielectric layer 11. An ohmic contact layer 16 is also formed between the polysilicon gate 17 and the multi-layered interconnect structure 18, and similarly, an ohmic contact layer is also disposed between the source/drain regions on both sides of the polysilicon gate 17 and the multi-layered interconnect structure 18, and the ohmic contact layer 16 is selected to be a material containing nickel, so as to reduce the ohmic contact between the multi-layered interconnect structure 18 and the substrate 10.
According to the semiconductor device provided by the invention, the second dielectric layer and the first dielectric layer are compounded to be used as the actual insulating isolation layer, and the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer, so that the VBD and TDDB performances corresponding to the insulating isolation layer are improved, and the reliability of the semiconductor device is improved.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present invention, wherein the three-dimensional memory 700 includes a memory cell array 702 and a peripheral circuit 701, and the peripheral circuit 701 includes the semiconductor device. Specifically, the three-dimensional memory 700 may be a NAND chip.
In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.
In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
a first dielectric layer on the substrate, the first dielectric layer having an opening formed therein;
the second dielectric layer covers the side wall of the opening, and the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer;
and the metal layer is filled in the opening.
2. The semiconductor device according to claim 1, further comprising:
and the transition layer is positioned on the surface of the second dielectric layer and the bottom surface of the opening.
3. The semiconductor device according to claim 1, wherein the opening includes a first sub-opening and a second sub-opening which communicate with each other; the metal layer includes a plug located in the first sub-opening and an interconnect line located in the second sub-opening.
4. A method of forming a semiconductor device, comprising:
providing a substrate, wherein a first dielectric layer is formed on the substrate;
forming an opening in the first dielectric layer;
forming a second dielectric layer on the side wall of the opening, wherein the dielectric coefficient of the second dielectric layer is greater than that of the first dielectric layer;
and filling a metal layer in the opening.
5. The method of claim 4, wherein the forming a second dielectric layer on the sidewalls of the opening comprises:
depositing the second dielectric layer on the surface of the first dielectric layer, the bottom surface and the side wall of the opening;
and removing the redundant second dielectric layer except the second dielectric layer on the side wall of the opening.
6. The method of claim 5, wherein the removing the excess second dielectric layer except the second dielectric layer on the sidewalls of the opening comprises:
and anisotropically etching the second dielectric layer along the thickness direction of the substrate to remove the redundant second dielectric layers on the surface of the first dielectric layer and the bottom surface of the opening and retain the second dielectric layers on the side wall of the opening.
7. The method for forming a semiconductor device according to claim 4, wherein the opening includes a first sub-opening and a second sub-opening; the filling of the metal layer in the opening includes:
and filling the metal layer in the opening to form a metal contact layer and a metal interconnection layer in the first sub-opening and the second sub-opening respectively.
8. The method according to claim 4, wherein the filling of the opening with the metal layer comprises:
forming the metal layer on the surface of the first dielectric layer and in the opening;
and removing the metal layer outside the opening by adopting a planarization process.
9. The method of claim 4, further comprising, after forming a second dielectric layer on the sidewalls of the opening:
and forming a transition layer on the surface of the second dielectric layer and the bottom surface of the opening.
10. A three-dimensional memory comprising a memory cell array and peripheral circuits, wherein the peripheral circuits comprise the semiconductor device according to any one of claims 1 to 3.
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CN104299958A (en) * 2013-07-16 2015-01-21 中芯国际集成电路制造(上海)有限公司 Interconnection structure and forming method of interconnection structure
CN111834209A (en) * 2019-04-22 2020-10-27 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same
CN112928097A (en) * 2019-12-06 2021-06-08 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof

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CN101064251A (en) * 2006-04-24 2007-10-31 台湾积体电路制造股份有限公司 Method for forming semiconductor structure and semiconductor structure
CN103151303A (en) * 2013-03-14 2013-06-12 上海华力微电子有限公司 Method for forming Damascus copper metal layer
CN104299958A (en) * 2013-07-16 2015-01-21 中芯国际集成电路制造(上海)有限公司 Interconnection structure and forming method of interconnection structure
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