CN112928097A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN112928097A
CN112928097A CN201911239729.3A CN201911239729A CN112928097A CN 112928097 A CN112928097 A CN 112928097A CN 201911239729 A CN201911239729 A CN 201911239729A CN 112928097 A CN112928097 A CN 112928097A
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Prior art keywords
dielectric layer
groove
grooves
semiconductor structure
manufacturing
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CN201911239729.3A
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Chinese (zh)
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周震
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN201911239729.3A priority Critical patent/CN112928097A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present disclosure provides a semiconductor structure and a method of fabricating the same. The semiconductor structure includes: a substrate; the first dielectric layer is positioned on the substrate; the grooves are positioned in the first medium layer, and the size of the tops of the grooves is larger than that of the bottoms of the grooves; the second dielectric layer is positioned on the side wall of the groove; and the conductive plug is positioned in the groove. The semiconductor structure and the manufacturing method thereof can improve the filling effect of the conductive material for forming the conductive plug and the electrical property of the conductive material.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure capable of improving a filling effect and electrical properties and a method for manufacturing the same.
Background
The Memory contact plug is a conductive semiconductor structure used for connecting a transistor and a storage capacitor in a DRAM (Dynamic Random Access Memory) structure. With the continuous shrinking of the transistor size and the storage capacitor size, the process window of the storage contact plug becomes smaller and smaller, the filling difficulty of the conductive material is increased, and meanwhile, the mutual interference effect is enhanced and the electrical performance is reduced when the interval between the storage contact plugs is reduced.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a semiconductor structure and a method for fabricating the same, which overcome, at least to some extent, the problems of poor filling effect of a conductive material and reduced electrical properties during the fabrication of the semiconductor structure due to the limitations of the related art.
According to a first aspect of the present disclosure, there is provided a semiconductor structure comprising:
a substrate;
the first dielectric layer is positioned on the substrate;
the grooves are positioned in the first medium layer, and the size of the tops of the grooves is larger than that of the bottoms of the grooves;
the second dielectric layer is positioned on the side wall of the groove;
and the conductive plug is positioned in the groove.
In one exemplary embodiment of the present disclosure, the dielectric constant of the first dielectric layer is less than the dielectric constant of the second dielectric layer.
In an exemplary embodiment of the present disclosure, the side wall of the groove has any one or any combination of a diagonal shape, a step shape, and a curved shape.
In an exemplary embodiment of the present disclosure, the interval between the grooves is the same as the size of the top of the grooves.
In an exemplary embodiment of the present disclosure, an aspect ratio of the groove is greater than 3: 1 and/or less than 10: 1.
In an exemplary embodiment of the present disclosure, the cross-section of the groove is any one of square, polygonal, circular, or elliptical.
In an exemplary embodiment of the present disclosure, the plurality of grooves are arranged in an array.
In an exemplary embodiment of the present disclosure, the thickness of the second dielectric layer is less than 5 nm.
In an exemplary embodiment of the present disclosure, the semiconductor structure further includes a third dielectric layer located on an upper surface of the first dielectric layer.
According to a second aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, comprising:
providing a substrate, wherein a first dielectric layer is formed on the substrate;
forming a plurality of grooves in the first dielectric layer, wherein the top size of each groove is larger than the bottom size of each groove;
forming a second dielectric layer on the side wall of the groove;
and filling a conductive material in the groove.
In one exemplary embodiment of the present disclosure, the dielectric constant of the first dielectric layer is less than the dielectric constant of the second dielectric layer.
In an exemplary embodiment of the present disclosure, the side wall of the groove has any one or any combination of a diagonal shape, a step shape, and a curved shape.
In an exemplary embodiment of the present disclosure, the interval between the grooves is the same as the size of the top of the grooves.
In an exemplary embodiment of the present disclosure, the manufacturing method further includes:
and forming a third dielectric layer on the surface of the first dielectric layer before forming the groove.
In an exemplary embodiment of the present disclosure, the manufacturing method further includes, before filling the conductive material in the groove, further including: and cleaning the bottom and the side wall of the groove in situ.
In an exemplary embodiment of the present disclosure, the manufacturing method further includes back-etching the conductive material.
According to the embodiment of the disclosure, the filling effect and the electrical property of the conductive material can be improved by improving the appearance of the groove and the first dielectric layer with a low dielectric constant, so that the yield of the product is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic view illustrating an arrangement manner and a cross-sectional direction of storage contact plugs in an exemplary embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a semiconductor structure in an embodiment of the disclosure.
FIG. 3 is a flow chart of a method of fabricating the semiconductor structure of the embodiment of FIG. 2.
FIGS. 4A-4C are schematic process diagrams of the steps shown in FIG. 3.
Fig. 5 is a schematic diagram of a semiconductor structure in another embodiment of the present disclosure.
Fig. 6A-6B are schematic process diagrams of the semiconductor structure shown in fig. 5.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The embodiment of the disclosure provides a semiconductor structure capable of avoiding air gaps from being generated in the semiconductor structure and a manufacturing method thereof. The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 2 is a schematic diagram of a semiconductor structure provided by the present disclosure.
Referring to fig. 2, a semiconductor structure 200 includes:
a substrate 21;
a first dielectric layer 22 on the substrate 21;
a plurality of grooves 23 in the first dielectric layer 22, wherein the top dimension L1 of the grooves 23 is larger than the bottom dimension L2 of the grooves 23;
the second dielectric layer 24 is positioned on the side wall of the groove 23;
and a conductive plug 25 located in the groove 23.
In one embodiment, the substrate 21 is a semiconductor silicon substrate for a DRAM memory cell including an active region and a shallow trench isolation structure. As shown in fig. 1, the substrate 21 includes an active region 211 and a shallow trench isolation structure 212. In one embodiment, the conductive plug is a storage contact plug. The structures shown in fig. 2, 4A-4C, 5, 6A, and 6B of the present disclosure are all cross-sectional views taken along the a-a of the structure shown in fig. 1. In the DRAM structure shown in FIG. 1, the A-A locations are perpendicular to the Word Line (WL) and parallel to the Bit Line structure 11(Bit Line, BL). Under the word line, there is an isolation structure 12 mainly composed of a first dielectric layer 22 and a second dielectric layer 24, and a storage contact plug 25(SNC structure) is located between two adjacent isolation structures 12 and two adjacent bit line structures 11. Since the bit line structure 11 is parallel to the cross section of the embodiment of the present disclosure, it is not shown in other drawings, and those skilled in the art can understand that the bit line structure 11 exists in front of and behind the viewing directions of fig. 2, 4A to 4C, 5, 6A and 6B of the present disclosure.
In one embodiment, the sidewalls of the groove 23 may be any one or any combination of diagonal, stepped, and curved, for example, with the top dimension L1 of the groove 23 being greater than the bottom dimension L2 of the groove 23. The size of the top of the groove 23 is larger than that of the bottom of the groove 23, so that subsequent filling of the conductive material in the groove is facilitated, and filling defects such as gaps and the like are reduced.
In an embodiment, a cross-section of the groove 23 in a direction parallel to the substrate may be any one of a polygon, a circle, or an ellipse. Preferably, the cross section is quadrilateral, two opposite sides of the quadrilateral are in a linear shape, and the other two opposite sides are in an arc shape. The center of the arc-shaped edge protrudes towards the outside of the quadrangle, so that the area of the cross section of the quadrangle is enlarged, and a convenient condition is provided for the subsequent filling of the conductive material. More preferably, the extension direction of the arc-shaped side is approximately the same as the extension direction of the word line of the DRAM memory cell, so that the etching process window is increased by the isolation layer on the word line.
In one embodiment, the plurality of grooves 23 may be arranged in an array, and the array may be an aligned or staggered dot-like array.
In an embodiment, the spacing L3 between grooves 23 may be, for example, the same as the top dimension L1 of the grooves. The space L3 or the top dimension L1 may be the minimum dimension that can be resolved by a photolithography process, for example, to increase the arrangement density of the grooves and increase the storage capacity per unit area of the chip. Specifically, the above-mentioned dimensions L1, L3 in the mask may be set to the minimum dimension that can be exposed under specific process conditions including the lithography exposure illumination condition, the kind of the photoresist, and the like in the lithography process. Preferably, the spacing between the grooves is a characteristic dimension of the photoresist patterns defining the grooves, and the top dimension of the grooves is a dimension of a gap between the photoresist patterns defining the grooves. For example, the photoresist pattern defining the grooves is lines arranged at equal intervals, and the lines have characteristic dimensions and the size of gaps among the lines; and forming a groove in the first dielectric layer by using the line. The spacing between grooves may be understood as the characteristic dimension of the lines and the top dimension of the grooves may be understood as the dimension of the spaces between the lines.
In one embodiment, due to the high arrangement density of the grooves, the filling difficulty of the conductive material is increased if the aspect ratio of the grooves is too large. Therefore, considering the arrangement density of the grooves and the filling difficulty of the conductive material, the depth-to-width ratio of the grooves can be set to be more than 3: 1 and/or less than 10:1, and/or less than 10:1, for example 5.3: 1,4.8: 1, etc. The depth-to-width ratio of the groove is the ratio of the opening size of the groove to the depth of the groove, specifically, the opening size can be the top size, the middle size or the bottom size of the groove, and can be set according to the actual process requirements. In this embodiment, the aspect ratio of the groove is the ratio of the middle dimension of the groove to the depth of the groove.
In the disclosed embodiment, the first dielectric layer 22 and the second dielectric layer 24 are both insulators to facilitate electrical isolation between the conductive plug 25 and adjacent structures. In one embodiment, the dielectric constant of the first dielectric layer 22 is less than the dielectric constant of the second dielectric layer 24. The first dielectric layer with a low dielectric constant is advantageous for reducing the parasitic capacitance between the conductive plug 25 and the adjacent structure, and improving the electrical characteristics. For example, the first dielectric layer may be a low dielectric constant material such as silicon oxide, and the second dielectric layer may be silicon nitride (Si)3N4) And the like.
In one embodiment, the thickness of the second dielectric layer is, for example, less than 5nm, such as 2nm, 4nm, etc., preferably 2 to 4 nm. The second dielectric layer with the thickness of 2-4 nm can protect the first dielectric layer, and is beneficial to increasing the size of the conductive plug and reducing the contact resistance.
Fig. 3 is a flow chart of a method of fabricating the semiconductor structure shown in fig. 2.
Referring to fig. 3, a semiconductor structure fabrication method 300 may include:
step S31, providing a substrate, wherein a first dielectric layer is formed on the substrate;
step S32, forming a plurality of grooves in the first dielectric layer, wherein the size of the tops of the grooves is larger than that of the bottoms of the grooves;
step S33, forming a second dielectric layer on the side wall of the groove;
step S34, filling a conductive material in the groove.
In embodiments of the present disclosure, the first dielectric layer and the second dielectric layer are both insulators to facilitate electrical isolation between the conductive plug and an adjacent structure. In one embodiment, the dielectric constant of the first dielectric layer is less than the dielectric constant of the second dielectric layer. The first dielectric layer with low dielectric constant is beneficial to reducing the parasitic capacitance between the conductive plug and the adjacent structure and improving the electrical characteristics. For example, the first dielectric layer may be a low dielectric constant material such as silicon oxide, and the second dielectric layer may be silicon nitride (Si)4N3) And the like.
FIGS. 4A-4C are schematic process diagrams of the steps shown in FIG. 3.
Referring to fig. 4A, a substrate 21 is first provided, and a first dielectric layer 22 is formed on the substrate 21.
In one embodiment, the substrate 21 is a semiconductor silicon substrate for a DRAM memory cell including an active region and a shallow trench isolation structure. The first dielectric layer 22 is a low dielectric constant material, such as silicon oxide, etc., but the disclosure is not limited thereto.
As shown in fig. 4A, in step S32, a plurality of grooves 23 are formed in the first dielectric layer 22, the top dimension of the grooves being greater than the bottom dimension of the grooves.
In one embodiment, the plurality of recesses 23 may be formed in the first dielectric layer 22 by an etching process such as photolithography.
In an embodiment, the side walls of the groove may be any one or any combination of diagonal, stepped and curved.
In one embodiment, the aspect ratio of the groove is controlled to be greater than 2: 1 and/or less than 10: 1.
In one embodiment, the spacing between the grooves is the same size as the top of the grooves.
In addition, in the photolithography process of masking, exposing, etching, etc., the opening shape of the groove (i.e., the cross section of the groove) may be set to be square, so as to make the size of the groove smaller and improve the device density. The process method for making the square opening is, for example, SADP (Self-aligned Double imaging), that is, after one-time lithography is completed, non-lithography process steps (thin film deposition, etching, etc.) are successively used to realize spatial frequency doubling of the lithography pattern. Finally, the redundant pattern is removed by using another photoetching process.
In other embodiments of the present disclosure, the shape of the opening of the groove may also be set to be polygonal, circular, or elliptical, etc. to simplify the process requirements, which is not limited by the present disclosure.
Referring to fig. 4B, a second dielectric layer 24 is formed on the sidewalls of the recess 23 at step S32. Specifically, the second dielectric Layer may be formed on the sidewall and the bottom of the groove and on the upper surface of the first dielectric Layer 22 by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), and then the second dielectric Layer on the bottom of the groove and on the upper surface of the first dielectric Layer 22 is removed by using a dry etching process.
In embodiments of the present disclosure, the first dielectric layer and the second dielectric layer are both insulators to facilitate electrical isolation between the conductive plug and an adjacent structure. In one embodiment, the dielectric constant of the first dielectric layer is less than the dielectric constant of the second dielectric layer. The first dielectric layer with low dielectric constant is beneficial to reducing the parasitic capacitance between the conductive plug and the adjacent structure and improving the electrical characteristics. For example, the first dielectric layer may be a low dielectric constant material such as silicon oxide, and the second dielectric layer may be silicon nitride (Si)3N4) And the like.
As shown in fig. 4C, in step S34, the grooves are filled with a conductive material. Specifically, the groove may be filled with a conductive material such as tungsten, aluminum, cobalt, or polysilicon by PVD (Physical Vapor Deposition), epitaxial growth, or the like. The material and the specific deposition method of the conductive material can be set by those skilled in the art, and the disclosure is not limited thereto.
Fig. 5 is a schematic diagram of another semiconductor structure 500 provided by the embodiments of the present disclosure.
Fig. 6A and 6B are schematic views of a process for fabricating the semiconductor structure 500 shown in fig. 5. Referring to fig. 6A and 6B, a third dielectric layer 26 may be formed on the surface of the first dielectric layer 22 before forming the recess. The third dielectric layer 26 at least partially remains on the surface of the first dielectric layer 22 after the formation of the recess 23 to reduce damage to the first dielectric layer by etching ions used to remove the second dielectric layer at the bottom of the recess 23.
In one embodiment, the deposition thickness of the third dielectric layer 26 may be controlled such that the thickness of the third dielectric layer 26 deposited on top of the first dielectric layer 22 is the same as the thickness of the second dielectric layer 24 deposited on the sidewalls of the recess, or is thicker, to provide better isolation for the subsequent deposition of the conductive material.
Finally, the resulting semiconductor structure 500 as shown in fig. 5 has better surface characteristics.
In one embodiment, in order to avoid the influence of the residual impurities (natural oxide, etching residues) on the electrical properties of the conductive material deposition interface (such as the sidewall and the bottom of the second dielectric layer of the groove) and the interface damage caused during the formation of the second dielectric layer on the sidewall of the groove, the bottom and the sidewall of the groove may be cleaned in situ by dry cleaning or the like before the conductive material is filled, so as to repair the interface damage and ensure the purity of the interface.
In one embodiment, the conductive plug may be formed by etching back the conductive material after depositing the conductive material, so that the conductive plug has a flat upper surface and a suitable length.
In one embodiment, the conductive plug is a storage contact plug. After the formation of the memory contact plug, a metal interface Pad (bonding Pad) may be formed on the memory contact plug for subsequent fabrication of a capacitor on the interface Pad. Since the interface platform for connecting the metal material on the storage contact plug belongs to the manufacture of the metal-semiconductor contact structure, in another embodiment of the disclosure, after the groove is filled, metal can be simultaneously deposited on the conductive material surface of the metal-semiconductor contact structure corresponding to the transistor and the conductive material surface of the semiconductor structure. Namely, the Contact structure (Contact) of the interface platform and the MOS tube of the peripheral circuit is manufactured at the same time. Because the manufacturing conditions of the two are consistent, the metal is contacted with the plug, the manufacturing together can ensure that the process condition requirement is simpler, the performance of the contact structure is improved, and the manufacturing cost is reduced.
In summary, the second dielectric layer is deposited on the side wall of the groove to manufacture the trapezoidal spacer, so that the groove which is easier to operate can be provided for the deposition of the conductive material, the air gap generation rate in the deposition process of the conductive material is effectively reduced on the basis of saving the process flow and the materials, and the yield is improved.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (16)

1. A semiconductor structure, comprising:
a substrate;
the first dielectric layer is positioned on the substrate;
the grooves are positioned in the first medium layer, and the size of the tops of the grooves is larger than that of the bottoms of the grooves;
the second dielectric layer is positioned on the side wall of the groove;
and the conductive plug is positioned in the groove.
2. The method of claim 1, further comprising:
the dielectric constant of the first dielectric layer is smaller than that of the second dielectric layer.
3. The semiconductor structure of claim 1, further comprising:
the side wall of the groove is in any one or any combination of an oblique line shape, a step shape and a curve shape.
4. The semiconductor structure of claim 3, further comprising:
the spacing between the grooves is the same size as the top of the grooves.
5. The semiconductor structure of claim 1, wherein an aspect ratio of the recess is greater than 3: 1 and/or less than 10: 1.
6. The semiconductor structure of claim 1, wherein a cross-section of the recess is any one of a polygon, a circle, or an ellipse.
7. The semiconductor structure of claim 6, wherein the plurality of recesses are arranged in an array.
8. The semiconductor structure of claim 1, wherein the thickness of the second dielectric layer is less than 5 nm.
9. The semiconductor structure of claim 1, further comprising:
and the third dielectric layer is positioned on the upper surface of the first dielectric layer.
10. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein a first dielectric layer is formed on the substrate;
forming a plurality of grooves in the first dielectric layer, wherein the top size of each groove is larger than the bottom size of each groove;
forming a second dielectric layer on the side wall of the groove;
and filling a conductive material in the groove.
11. The method of manufacturing of claim 10, further comprising:
the dielectric constant of the first dielectric layer is smaller than that of the second dielectric layer.
12. The method of manufacturing of claim 10, further comprising:
the side wall of the groove is in any one or any combination of an oblique line shape, a step shape and a curve shape.
13. The method of manufacturing of claim 10, further comprising:
the spacing between the grooves is the same size as the top of the grooves.
14. The method of manufacturing of claim 10, further comprising:
and forming a third dielectric layer on the surface of the first dielectric layer before forming the groove.
15. The method of manufacturing of claim 10, further comprising, prior to filling the conductive material in the recess:
and cleaning the bottom and the side wall of the groove in situ.
16. The method of manufacturing of claim 10, further comprising: and carrying out back etching on the conductive material.
CN201911239729.3A 2019-12-06 2019-12-06 Semiconductor structure and manufacturing method thereof Pending CN112928097A (en)

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Application Number Priority Date Filing Date Title
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113838834A (en) * 2021-09-18 2021-12-24 长江存储科技有限责任公司 Semiconductor device, method for forming semiconductor device, and three-dimensional memory
CN117529097A (en) * 2023-12-28 2024-02-06 长鑫集电(北京)存储技术有限公司 Semiconductor structure and preparation method thereof
CN113838834B (en) * 2021-09-18 2024-05-24 长江存储科技有限责任公司 Semiconductor device, method for forming semiconductor device, and three-dimensional memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113838834A (en) * 2021-09-18 2021-12-24 长江存储科技有限责任公司 Semiconductor device, method for forming semiconductor device, and three-dimensional memory
CN113838834B (en) * 2021-09-18 2024-05-24 长江存储科技有限责任公司 Semiconductor device, method for forming semiconductor device, and three-dimensional memory
CN117529097A (en) * 2023-12-28 2024-02-06 长鑫集电(北京)存储技术有限公司 Semiconductor structure and preparation method thereof
CN117529097B (en) * 2023-12-28 2024-04-19 长鑫集电(北京)存储技术有限公司 Semiconductor structure and preparation method thereof

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