CN113838815B - Substrate and chip assembly - Google Patents
Substrate and chip assembly Download PDFInfo
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- CN113838815B CN113838815B CN202111116395.8A CN202111116395A CN113838815B CN 113838815 B CN113838815 B CN 113838815B CN 202111116395 A CN202111116395 A CN 202111116395A CN 113838815 B CN113838815 B CN 113838815B
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- 239000000758 substrate Substances 0.000 title claims abstract description 135
- 238000004806 packaging method and process Methods 0.000 claims abstract description 8
- 230000017525 heat dissipation Effects 0.000 abstract description 8
- 238000013021 overheating Methods 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The embodiment of the application discloses a substrate and a chip assembly. The substrate is used for packaging the chip. The substrate includes at least two signal regions, a ground pin and a power pin. A preset area is arranged between the at least two signal areas, and the preset area is used for setting the chip. The grounding pin is arranged in the preset area and is used for connecting the chip. The power pins are distributed in at least two signal areas. According to the embodiment of the application, the chip is arranged in the preset area and is connected with the grounding pin, so that the heat dissipation of the chip can be promoted, the chip temperature is prevented from being too high, and the service performance of the substrate is further improved. In addition, the preset area is arranged between the at least two signal areas, so that the power supply pins distributed in the at least two signal areas can be separated, the power supply pins are prevented from being distributed on the substrate too intensively, the current density of the substrate is reduced, the local overheating of the substrate is avoided, and the use reliability of the substrate is further improved.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to a substrate and a chip assembly.
Background
In the related art, a substrate is used to package a chip. The substrate typically includes power pins through which current flows into the substrate to power the chip.
However, in the related art, after the chip is packaged, the heat dissipation of the chip is difficult, and the service performance of the substrate is reduced.
Disclosure of Invention
In order to solve at least one of the above technical problems, embodiments of the present application provide a substrate and a chip assembly.
In a first aspect, an embodiment of the present application provides a substrate for packaging a chip. The substrate comprises at least two signal areas, a preset area is arranged between the at least two signal areas, and the preset area is used for setting a chip; the grounding pin is arranged in the preset area and is used for connecting the chip; and the power supply pins are distributed in at least two signal areas.
In one possible embodiment, the signal region includes at least two first signal regions, and at least one power pin having a current value greater than or equal to the first current threshold is included in any one of the first signal regions.
In a possible implementation manner, the signal area further comprises at least two second signal areas, and at least one power pin with a current value smaller than the first current threshold and greater than or equal to the second current threshold is included in any one of the second signal areas; wherein the first current threshold is greater than the second current threshold.
In a possible embodiment, the signal region further comprises at least two third signal regions, and at least one power pin having a current value smaller than the second current threshold value is included in any one of the third signal regions.
In one possible embodiment, the power pins in any one of the first signal regions, any one of the second signal regions, and any one of the third signal regions are connected to each other.
In one possible embodiment, the voltage value of the power supply pin in the first signal region is less than or equal to the first voltage threshold, and the voltage value of the power supply pin in the second signal region is greater than the first voltage threshold and less than or equal to the second voltage threshold; the first voltage threshold is smaller than the second voltage threshold, and the area of any one first signal area is larger than the area of any one second signal area.
In one possible embodiment, at least one power pin having a voltage value greater than the second voltage threshold is included in any one of the third signal regions; the area of any one of the second signal regions is larger than the area of any one of the third signal regions.
In one possible embodiment, the substrate is a rectangular substrate comprising opposing first and second edges, opposing third and fourth edges; at least one part of the first signal areas and the first edge form a closed area, and the other part of the first signal areas and the second edge form a closed area; at least one part of the second signal areas and the third edge form a closed area, and the other part of the second signal areas and the fourth edge form a closed area; at least two third signal areas are positioned in the first signal area, a part of the third signal areas and the first edge form a closed area, and the other part of the third signal areas and the second edge form a closed area.
In one possible embodiment, at least two first signal regions are symmetrical in a first direction and at least two third signal regions are symmetrical in the first direction; at least two second signal regions are symmetrical along a second direction; the at least two first signal areas are separated by a central area, and the central area extends to the top of the substrate through a separation area between the two second signal areas and between the first signal areas and the second signal areas so as to form a preset area.
In a second aspect, an embodiment of the present application provides a chip assembly, including a chip; the substrate of the first aspect, wherein the substrate is used for packaging a chip, and the chip is connected to a ground pin on the substrate.
The embodiment of the application has the following beneficial effects:
Because set up the ground pin in the district in predetermineeing, the heat that produces is less, so set up the chip in predetermineeing the district to be connected with the ground pin, can promote the chip to dispel the heat, avoid the chip temperature too high, further improve the performance of base plate.
In addition, the preset area is arranged between at least two signal areas, so that the power supply pins distributed in the at least two signal areas can be separated, the power supply pins are prevented from being distributed on the substrate too intensively, the current density of the substrate is reduced, the local overheating of the substrate is avoided, and the use reliability of the substrate is further improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of a substrate structure according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a second substrate structure according to an embodiment of the present application;
fig. 3 is a schematic diagram of a chip assembly according to an embodiment of the present application.
The correspondence between the reference numerals and the component names in fig. 1 to 3 is:
100: substrate, 101: signal area, 102: power pin, 103: first edge, 104: second edge, 105: third edge, 106: fourth edge, 110: first signal region, 120: second signal region, 130: third signal region, 140: preset area, 142: ground pin, chip assembly: 200, chip: 210.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, without conflict, the embodiments of the present application and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
In a first aspect, as shown in fig. 1, an embodiment of the present application provides a substrate 100. The substrate 100 is used for packaging a chip 210. The substrate 100 includes at least two signal regions 101, a ground pin 142, and a power pin 102. A preset area 140 is provided between the at least two signal areas 101, and the preset area 140 is used for setting the chip 210. The ground pin 142 is disposed in the predetermined area 140 and is used for connecting the chip 210. The power pins 102 are distributed within at least two signal areas 101.
In some examples, the substrate 100 may be a copper clad laminate for packaging the chip 210. In some examples, the substrate 100 may be square, circular, polygonal, etc., improving the applicability of the substrate 100.
The substrate 100 includes at least two signal regions 101, and it is understood that the shape and area of at least two first signal regions 110 may be the same or different. In some examples, a different number of signal regions 101 may be provided according to different usage requirements.
The power pins 102 are distributed within at least two signal areas 101, it being understood that the power pins 102 are used to power the chip 210. The number of power pins 102 is plural. In some examples, the current and voltage values of the plurality of power pins 102 are different from each other. In some examples, the current values of the plurality of power pins 102 are the same and the voltage values are different. In some examples, the current values are different and the voltage values are the same for the plurality of power pins 102. It will be appreciated that the greater the current value of the power pin 102, the higher the heat generated by the power pin 102.
At least two signal regions 101 have a predetermined region 140 therebetween, and ground pins 142 are distributed in the predetermined region 140. When the chip 210 is packaged on the substrate, the ground pins 142 are connected with the chip 210, so that heat dissipation can be effectively performed, and heat of the chip 210 can be reduced. It will be appreciated that the number of ground pins 142 is a plurality. The number of ground pins 142 may be the same as or different from the number of power pins 102. In some examples, the number of ground pins 142 is greater than the number of power pins 102, thereby increasing the heat dissipation, speeding up the heat dissipation, and improving the reliability of use of the substrate 100.
It will be appreciated that ground pin 142 is connected to ground such that the voltage value of ground pin 142 is small, and in some examples, the voltage value of ground pin 142 is zero. According to the calculation formula p=ui of power (where P is power, U is voltage, and I is current), when the current value is fixed, the smaller the voltage value is, the smaller the power is, and the smaller the power is, the smaller the generated heat is.
Since the grounding pins 142 are disposed in the preset area 140, less heat is generated, so that the chip 210 is disposed in the preset area 140 and connected with the grounding pins 142, heat dissipation of the chip 210 can be promoted, overhigh temperature of the chip 210 is avoided, and the service performance of the substrate 100 is further improved.
In some examples, chip 210 may be connected to ground pin 142 by bump bonding. In some examples, the chip 210 may be disposed at a central location of the substrate 100, improving structural regularity of the chip 210 assembly while avoiding curling of the substrate 100.
It is understood that the current density is the amount of electricity flowing through the substrate 100 per unit area per unit time. The greater the current density per unit area of the substrate 100, the higher the heat generated. The preset area 140 is arranged between the at least two signal areas 101, so that the power supply pins 102 distributed in the at least two signal areas 101 can be separated, the power supply pins 102 are prevented from being distributed on the substrate 100 too intensively, the current density of the substrate 100 is reduced, the local overheating of the substrate 100 is avoided, and the use reliability of the substrate 100 is further improved.
In some examples, the preset region 140 is disposed adjacent to at least two signal regions 101, so that a distance between the power pin 102 and the ground pin 142 can be reduced, a current return path can be shortened, interference during signal transmission can be reduced, accuracy of signal transmission can be improved, and a resistance value of the substrate 100 can be reduced, so that a voltage drop of the substrate 100 can be reduced.
In some examples, clock signal pins or data signal pins, etc., may also be distributed within the preset area 140, improving the applicability of the substrate 100. In addition, the clock signal pin and the data signal pin can be grounded through the grounding pin 142, so that the backflow path of the signal is shortened, the insertion loss and reflection of the signal are reduced, and the reliability of signal transmission is improved.
In some examples, the interconnection between the ground pins 142 within the predetermined area 140 further reduces the resistance of the predetermined area 140, thereby further reducing the voltage drop across the substrate 100.
In some examples, as shown in fig. 2, the signal region 101 includes at least two first signal regions 110. At least one power pin 102 having a current value greater than or equal to the first current threshold is included in any one of the first signal regions 110.
In some examples, the current values of the power pins 102 distributed within the at least two first signal regions 110 may be the same or different. The number of power pins 102 distributed within the at least two first signal regions 110 may be the same or different. In some examples, the current values of the power pins 102 distributed within any one of the first signal regions 110 may be the same or different.
In some examples, the shape and area between at least two first signal regions 110 may be the same or different.
The power pins 102 are distributed in at least two first signal areas 110, and at least one power pin 102 with a current value greater than or equal to a first current threshold value is included in any one first signal area 110, so that the preset area 140 is arranged between the at least two first signal areas 110, that is, the power pins 102 with the current value greater than or equal to the first current threshold value can be distributed in the at least two first signal areas 110 which are arranged at intervals, the power pins 102 with the current value greater than or equal to the first current threshold value are prevented from being distributed too intensively, the current density of the substrate 100 can be more uniform, the heating of a part of the area of the substrate 100 caused by the overlarge current density is avoided, and the use reliability of the substrate 100 is further ensured.
In some examples, the plurality of power pins 102 with the current value greater than or equal to the first current threshold may be included in any one of the first signal areas 110, and the plurality of power pins 102 with the current value greater than or equal to the first current threshold distributed in any one of the first signal areas 110 may be centrally disposed or may be disposed at intervals.
It will be appreciated that different first current thresholds may be set depending on the different substrates 100 and chips 210. In some examples, the first current threshold may be between 10A and 13A, in particular, the first current threshold may be 11a,12a, 12.5A, or the like.
In some examples, different numbers of the first signal regions 110 may be provided according to different substrates 100 and chips 210, improving the flexibility of use of the substrate 100. In some examples, as shown in fig. 2, the number of first signal regions 110 may be two.
In some examples, as shown in fig. 2, the signal region 101 further includes at least two second signal regions 120. At least one power pin 102 having a current value less than the first current threshold and greater than or equal to the second current threshold is included in any one of the second signal regions 120. Wherein the first current threshold is greater than the second current threshold.
In some examples, the shape and area of the first signal region 110 and the second signal region 120 may be the same or different. In some examples, the number of power pins 102 distributed within the first signal region 110 may be the same as or different from the number of power pins 102 distributed within the second signal region 120. In some examples, the number of first signal regions 110 and second signal regions 120 may be the same or different.
In some examples, the current values of the power pins 102 distributed within the at least two second signal regions 120 may be the same or different. The number of power pins 102 distributed within the at least two second signal regions 120 may be the same or different. In some examples, the current values of the power pins 102 distributed within any one of the second signal regions 120 may be the same or different.
In some examples, the shape and area between at least two second signal regions 120 may be the same or different.
The power pins 102 are distributed in the second signal areas 120, and at least one power pin 102 with a current value smaller than the first current threshold and greater than or equal to the second current threshold is included in any one of the second signal areas 120. As can be appreciated, the preset area 140 is disposed between the first signal area 110 and the second signal area 120, and between at least two second signal areas 120, so that the current value is smaller than the first current threshold, and the power pins 102 with the current value greater than or equal to the second current threshold can be spaced from the power pins 102 with the current value greater than or equal to the first current threshold, and the power pins 102 with the current value smaller than the first current threshold and greater than or equal to the second current threshold are spaced from each other, which further avoids heating the substrate 100 caused by excessive current density of a partial area of the substrate 100, so that the current density of the substrate 100 can be more uniform, and the use reliability of the substrate 100 is improved.
In some examples, the plurality of power pins 102 having the current value smaller than the first current threshold and greater than or equal to the second current threshold may be included in any one of the second signal regions 120, and the plurality of power pins 102 having the current value smaller than the first current threshold and greater than or equal to the second current threshold may be collectively disposed or may be disposed at intervals.
In some examples, a different second current threshold may be set according to a different substrate 100 and a different chip 210. In some examples, the second current threshold may be between 5A and 7A. Specifically, the second current threshold may be 5.5A, 6A, 6.5A, or the like.
In some examples, different numbers of second signal regions 120 may be provided according to different substrates 100 and chips 210, improving the flexibility of use of the substrate 100. In some examples, as shown in fig. 2, the number of second signal regions 120 may be four.
In some examples, as shown in fig. 2, the signal region 101 further includes at least two third signal regions 130. At least one power pin 102 having a current value less than the second current threshold is included in any of the third signal regions 130.
In some examples, the shape and area of the third signal region 130 may be the same as the shape and area of the first and second signal regions 110 and 120, or may be different from the shape and area of the first and second signal regions 110 and 120.
In some examples, the number of power pins 102 distributed within the third signal region 130 may be the same as the number of power pins 102 distributed within the first and second signal regions 110, 120, or may be different from the number of power pins 102 distributed within the first and second signal regions 110, 120.
In some examples, the number of third signal regions 130 may be the same as or different from the number of first signal regions 110 or second signal regions 120.
In some examples, the current values of the power pins 102 distributed within the at least two third signal regions 130 may be the same or different. The number of power pins 102 distributed within the at least two third signal regions 130 may be the same or different. In some examples, the current values of the power pins 102 distributed within any one of the third signal regions 130 may be the same or different.
In some examples, the shape and area between at least two third signal regions 130 may be the same or different.
The power pins 102 are distributed in the third signal areas 130, and at least one power pin 102 with a current value smaller than the second current threshold value is included in any one of the third signal areas 130, and as can be appreciated, the preset area 140 is arranged between at least two third signal areas 130, so that the power pins 102 with a current value smaller than the second current threshold value can be arranged at intervals, the current density on the substrate 100 is further prevented from being too high, the current density of the substrate 100 is uniform, and the use reliability of the substrate 100 is improved.
In some examples, the preset region 140 is disposed between the first signal region 110, the second signal region 120, and the third signal region 130, and further serves to separate the power pins 102 of different current values, so that the current density of the substrate 100 can be more uniform.
In some examples, the plurality of power pins 102 having the current value smaller than the second current threshold may be included in any one of the third signal areas 130, and the plurality of power pins 102 having the current value smaller than the second current threshold in any one of the third signal areas 130 may be disposed in a concentrated manner or may be disposed at intervals.
In some examples, a different number of third signal regions 130 may be provided according to different substrates 100 and chips 210. In some examples, as shown in fig. 2, the number of third signal regions 130 is at least two.
In some examples, as shown in fig. 2, the power pins within any one of the first signal regions 110, any one of the second signal regions 120, and any one of the third signal regions 130 are connected to each other.
In some examples, the power pins 102 distributed within any one of the first signal regions 110, the power pins 102 distributed within any one of the second signal regions 120, and the power pins 102 distributed within any one of the third signal regions 130 may be respectively connected to each other by copper sheets.
Specifically, taking the first signal region 110 as an example, when the current flowing through the power pins 102 distributed in the first signal region 110 is dc, the resistance of the first signal region 110 isWhere R is a resistance value, L is a distance between the power pins 102 and the ground pins 142 distributed in the first signal area 110, T is a copper sheet thickness of the first signal area 110, and W is a copper sheet width of the first signal area 110.
The power pins 102 distributed in any one of the first signal areas 110 are connected to each other, that is, the copper sheet width W of the first signal area 110 is increased, so that the resistance R of the first signal area 110 can be reduced, and the voltage drop caused by the first signal area 110 can be reduced.
Taking the first signal region 110 as an example again, when the current flowing through the power pins 102 distributed in the first signal region 110 is ac, the first signal region 110 and the ground plane can be regarded as a plate capacitor, and the equivalent capacitance of the plate capacitor isWhere C is the equivalent capacitance, ε 0 is the dielectric constant of free space, εr is the relative dielectric constant of the medium, a is the overlap area of the first signal region 110 and the ground plane, and H is the separation distance between the first signal region 110 and the ground plane.
The power pins 102 distributed in any one of the first signal regions 110 are connected with each other, i.e. the overlapping area A of the first signal region 110 and the ground plane is increased, so that the equivalent capacitance C is increased, and the calculation formula of the impedance is adoptedWhere Xc is the impedance of the capacitor, f is the frequency of the alternating current, C is the capacitance value, and the larger the capacitance value C is, the smaller the impedance Xc is, so that the smaller the alternating noise of the capacitor is, the resistance value of the capacitor is reduced, and the voltage drop caused by the first signal region 110 is reduced.
By providing the power pins 102 distributed in any one of the first signal regions 110, the power pins 102 distributed in any one of the second signal regions 120, and the power pins 102 distributed in any one of the third signal regions 130, respectively, the resistance values of the first signal regions 110, the second signal regions 120, and the third signal regions 130 are reduced, the voltage drops caused by the first signal regions 110, the second signal regions 120, and the third signal regions 130 are reduced, and the use performance of the substrate 100 is improved.
In some examples, as shown in fig. 2, the voltage value of the power pin 102 within the first signal region 110 is less than or equal to the first voltage threshold. The voltage value of the power pin 102 within the second signal region 120 is greater than the first voltage threshold and less than or equal to the second voltage threshold. Wherein the first voltage threshold is smaller than the second voltage threshold, and the area of any one of the first signal regions 110 is larger than the area of any one of the second signal regions 120.
In some examples, the voltage values of the power pins 102 distributed within the first signal region 110 may be the same or different. The voltage values of the power pins 102 distributed in the second signal region 120 may be the same or different.
It will be appreciated that when the resistances are the same, the smaller the voltage value of the power pin 102, the greater the voltage ratio of the resistor, and the greater the influence of the resistor on the power pin 102.
The area of any one of the first signal regions 110 is set to be larger than the area of any one of the second signal regions 120 so that the resistance value of any one of the first signal regions 110 can be smaller than the resistance value of any one of the second signal regions 120. Meanwhile, the voltage value of the power supply pin 102 in any one of the first signal areas 110 is set to be smaller than or equal to the first voltage threshold, the voltage value of the power supply pin 102 in any one of the second signal areas 120 is set to be larger than the first voltage threshold and smaller than or equal to the second voltage threshold, and the first voltage threshold is smaller than the second voltage threshold, that is, the power supply pin 102 with smaller voltage value is set in the first signal area 110 with smaller resistance value, and the power supply pin 102 with larger voltage value is set in the second signal area 120 with larger resistance value, so that the influence of the resistance value on the power supply pin 102 is reduced, and the service performance of the substrate 100 is further improved.
In some examples, different first and second voltage thresholds may be set according to different substrates 100 and different chips 210, providing suitability of the substrate 100.
In some examples, the first voltage threshold may be between 1.1V and 1.3V, in particular, the first voltage threshold may be 1.15V, 1.2V, or 1.25V. The second voltage threshold may be between 1.7V and 1.9V, in particular the second voltage threshold may be 1.75V,1.8V or 1.85V.
In some examples, as shown in fig. 2, at least one power pin 102 having a voltage value greater than the second voltage threshold is included within any one of the third signal regions 130. The area of any one of the second signal regions 120 is larger than the area of any one of the third signal regions 130.
In some examples, the voltage values of the power pins 102 distributed within the third signal region 130 may be the same or different.
The area of any one of the second signal regions 120 is larger than the area of any one of the third signal regions 130, so that the resistance value of any one of the second signal regions 120 can be smaller than the resistance value of any one of the third signal regions 130. Meanwhile, the voltage value of the power supply pin 102 in any one of the third signal areas 130 is set to be greater than the second voltage threshold, that is, the power supply pin 102 with a larger voltage value is set in the third signal area 130 with a larger resistance value, so that the influence of the resistance value on the power supply pin 102 is reduced, and the service performance of the substrate 100 is further improved.
In some examples, as shown in fig. 2, the substrate 100 is a rectangular substrate 100. The substrate 100 includes opposing first 103 and second 104 edges, opposing third 105 and fourth 106 edges. At least two first signal regions 110 have a portion of the first signal regions 110 forming a closed region with the first edge 103 and another portion of the first signal regions 110 forming a closed region with the second edge 104. At least a portion of the second signal regions 120 of the at least two second signal regions 120 form a closed region with the third edge 105 and another portion of the second signal regions 120 form a closed region with the fourth edge 106. At least two third signal regions 130 are located in the first signal region 110, a part of the third signal regions 130 and the first edge 103 form a closed region, and another part of the third signal regions 130 and the second edge 104 form a closed region.
It will be appreciated that the substrate 100 is rectangular, the first edge 103 and the second edge 104 are the same length and parallel to each other, and the third edge 105 and the fourth edge 106 are the same length and parallel to each other.
A part of the first signal regions 110 of the at least two first signal regions 110 forms a closed region with the first edge 103, and another part of the first signal regions 110 forms a closed region with the second edge 104, i.e. the at least two first signal regions 110 can be arranged opposite each other and adjacent to the first edge 103 and the second edge 104, respectively.
A part of the second signal regions 120 of the at least two second signal regions 120 forms a closed region with the third edge 105, and another part of the second signal regions 120 forms a closed region with the fourth edge 106, i.e. the at least two second signal regions 120 can be arranged opposite each other and adjacent to the third edge 105 and the fourth edge 106, respectively.
Through the arrangement, the power pins distributed in the signal area 101 can be further separated, so that the current density of the substrate 100 is uniform, local overheating of the substrate 100 is avoided, and the use reliability of the substrate 100 is improved. In addition, the first signal area 110 and the second signal area 120 are adjacent to the edge of the rectangular substrate 100, so that the power pins 102 in the first signal area 110 and the second signal area 120 can be conveniently connected with a PCB (Printed Circuit Board ) or other components, and the use flexibility of the substrate 100 is improved.
Meanwhile, at least two third signal regions 130 are located in the first signal region 110, a part of the third signal regions 130 and the first edge 103 form a closed region, and another part of the third signal regions 130 and the second edge 104 form a closed region, so that the area utilization rate of the substrate 100 can be improved on the basis of uniform current density of the substrate 100. And the power pins 102 in the third signal area 130 are convenient to connect with a PCB board (Printed Circuit Board ) or other components, so that the flexibility of using the substrate 100 is further improved.
In some examples, as shown in fig. 2, at least two first signal regions 110 are symmetrical in a first direction and at least two third signal regions 130 are symmetrical in the first direction. At least two second signal regions 120 are symmetrical in a second direction. Wherein, at least two first signal regions 110 are separated by a central region, and the central region extends to the vertex of the substrate 100 through a separation region between two second signal regions 120 and between the first signal regions 110 and the second signal regions 120 to form a preset region 140.
It will be appreciated that the first direction is perpendicular to the second direction. In some examples, the first direction is parallel to the first edge 103 and the second direction is parallel to the third edge 105. In some examples, the first direction is parallel to the third edge 105 and the second direction is parallel to the first edge 103.
At least two first signal regions 110 are symmetrical in a first direction, at least two third signal regions 130 are symmetrical in the first direction, and at least two second signal regions 120 are symmetrical in a second direction, thereby improving the regularity of the distribution of the signal regions 101 on the substrate 100.
In addition, at least two first signal regions 110 are separated by a central region, and the central region extends to the top of the substrate 100 through a separation region between two second signal regions 120 and between the first signal regions 110 and the second signal regions 120, so as to form a preset region 140, so that the preset region 140 can extend from the center of the substrate 100 to the first edge 103, the second edge 104, the third edge 105 and the fourth edge 106 of the substrate 100, further increasing the area of the preset region 140 and improving the heat dissipation effect of the chip 210.
Meanwhile, the preset area 140 extends to the top of the substrate 100 through the interval area between the two second signal areas 120 and between the first signal area 110 and the second signal area 120, so that the distance between the power pin 102 and the ground pin 142 can be reduced, the return path of the signal can be shortened, the interference during signal transmission can be reduced, the accuracy of signal transmission can be improved, the resistance of the substrate 100 can be reduced, and the voltage drop of the substrate 100 can be reduced.
In a second aspect, as shown in fig. 3, an embodiment of the present application provides a chip assembly 200, including a chip 210 and a substrate 100 as described above in the first aspect. The substrate 100 is used for packaging the assembly 200, and the chip 210 is connected to the ground pin 142 on the substrate 100, so that all the advantages of the first aspect are provided, and will not be described herein.
In one embodiment, as shown in fig. 1 and 3, a substrate 100 is provided, the substrate 100 being used to package a chip 210. Specifically, the substrate 100 is square.
As shown in fig. 2, the substrate 100 includes a plurality of signal regions 101, and power pins 102 are distributed in the signal regions 101. The plurality of signal areas 101 are spaced apart, and the preset area 140 is distributed between the plurality of signal areas 101 and adjacent to the plurality of signal areas 101. The ground pins 142 are distributed within the predetermined area 140.
The chip 210 is disposed at the center of the preset area 140, and the heat generated by the preset area 140 is small, so that the heat dissipation of the chip 210 can be promoted, and the service performance of the substrate 100 can be improved.
Specifically, the signal region 101 includes a first signal region 110, a second signal region 120, and a third signal region 130. The area of the preset region 140 is larger than the area of the first signal region 110, the area of the first signal region 110 is larger than the area of the second signal region 120, and the area of the second signal region 120 is larger than the area of the third signal region 130.
The number of ground pins 142 is greater than the number of power pins 102. The number of distributed power pins 102 in the first signal area 110 is greater than the number of distributed power pins 102 in the second signal area 120, and the number of distributed power pins 102 in the second signal area 120 is greater than the number of distributed power pins 102 in the third signal area 130.
Specifically, the number of the first signal areas 110 is two, and the first edge 103 and the second edge 104 are adjacently disposed, respectively. By disposing the two first signal regions 110 opposite to each other, the ground pin 142 can be disposed between the two first signal regions 110, shortening the current return path and reducing the voltage drop of the substrate 100.
The power supply pins 102 with the current value greater than or equal to the first current threshold are arranged in the two first signal areas 110, so that the problem that the power supply pins 102 with the larger current value are distributed too intensively, so that the current density of the substrate 100 is too high, and the substrate 100 heats is avoided. Specifically, the first current threshold may be 10A.
In addition, the power pins 102 distributed in the first signal area 110 are connected with each other through copper sheets, the power pins 102 distributed in the second signal area 120 are connected with each other through copper sheets, the power pins 102 distributed in the third signal area 130 are connected with each other through copper sheets, and the ground pins 142 distributed in the preset area 140 are connected with each other through copper sheets, so that the resistance values of the first signal area 110, the second signal area 120, the third signal area 130 and the preset area 140 are further reduced, and the voltage drop of the substrate 100 is reduced.
Meanwhile, the power pins 102 with the voltage value smaller than or equal to the first voltage threshold are arranged in the two first signal areas 110, and the power pins 102 with the smaller voltage value are arranged in the first signal areas 110 due to the smaller resistance value of the first signal areas 110, so that the influence of the first signal areas 110 on the power pins 102 is reduced, and the use reliability of the substrate 100 is improved.
Specifically, the first voltage threshold may be 1.2V.
As shown in fig. 2, the number of the second signal areas 120 is four, and the second signal areas are disposed adjacent to the third edge 105 and the fourth edge 106, respectively. The four second signal regions 120 are disposed at intervals, and the four second signal regions 120 are disposed at intervals with the first signal region 110, so that the distance between the power pin 102 and the ground pin 142 in the second signal region 120 is shortened, thereby shortening the current return path and reducing the voltage drop of the substrate 100.
The power pins 102 with the current value smaller than the first current threshold and larger than or equal to the second current threshold are arranged in the second signal area 120, so that the current density of the substrate 100 is further reduced, and the substrate 100 is prevented from heating due to the overlarge current density on the substrate 100. Specifically, the second current threshold may be 5A.
Meanwhile, the voltage value is smaller than the first voltage threshold, and the power pin 102 larger than or equal to the second voltage threshold is disposed in the second signal area 120, so that the use reliability of the substrate 100 is further improved.
Specifically, the second voltage threshold may be 1.8V.
As shown in fig. 2, the number of the third signal regions 130 is two, and the third signal regions are disposed in the first signal region 110 and adjacent to the first edge 103 and the second edge 104, respectively, so as to improve the area utilization of the substrate 100.
The power pins 102 having a current value less than the second current threshold are distributed in the third signal region 130, further homogenizing the current density on the substrate 100.
The power supply pins 102 with the voltage value larger than the second voltage threshold are arranged in the third signal area 130, so that the influence of the resistor on the power supply pins 102 is reduced, and the use reliability of the substrate 100 is improved.
The preset area 140 is disposed adjacent to the first signal area 110 and the second signal area 120, so that the distance between the ground pin 142 and the power pin 102 is shortened, the resistance value of the substrate 100 is further reduced, and the voltage drop caused by the substrate 100 is reduced.
In the present invention, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more, unless expressly defined otherwise. The terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; "coupled" may be directly coupled or indirectly coupled through intermediaries. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "front", "rear", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or units referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present invention.
In the description of the present specification, the terms "one embodiment," "some embodiments," "particular embodiments," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A substrate for packaging a chip, the substrate comprising:
The chip comprises at least two signal areas, wherein a preset area is arranged between the at least two signal areas and is used for setting a chip;
the grounding pin is arranged in the preset area and is used for connecting the chip;
the power supply pins are distributed in at least two signal areas;
The signal region comprises at least two first signal regions and at least two second signal regions;
The substrate is a rectangular substrate and comprises a first edge, a second edge, a third edge and a fourth edge which are opposite to each other;
at least two first signal areas, wherein part of the first signal areas and the first edges form closed areas, and the other part of the first signal areas and the second edges form closed areas;
at least two second signal areas, wherein part of the second signal areas and the third edges form closed areas, and the other part of the second signal areas and the fourth edges form closed areas;
The central area extends to the top of the substrate through a spacing area between the two second signal areas and between the first signal areas and the second signal areas so as to form the preset area;
the preset area forms a closed area with part of the first edge, part of the second edge, part of the third edge and part of the fourth edge respectively, and the preset area comprises a corner area of the substrate.
2. The substrate of claim 1, wherein at least one of the power pins having a current value greater than or equal to a first current threshold is included in any of the first signal regions.
3. The substrate of claim 2, wherein at least one of the power pins having a current value less than the first current threshold and greater than or equal to a second current threshold is included in any of the second signal regions;
wherein the first current threshold is greater than the second current threshold.
4. The substrate of claim 3, wherein the signal region further comprises:
at least two third signal areas, wherein any one of the third signal areas comprises at least one power pin with a current value smaller than the second current threshold value.
5. The substrate of claim 4, wherein the power pins in any one of the first signal regions, any one of the second signal regions, and any one of the third signal regions are connected to each other.
6. The substrate of claim 4, wherein a voltage value of the power pin in the first signal region is less than or equal to a first voltage threshold, and a voltage value of the power pin in the second signal region is greater than the first voltage threshold and less than or equal to a second voltage threshold;
The first voltage threshold is smaller than the second voltage threshold, and the area of any one of the first signal areas is larger than the area of any one of the second signal areas.
7. The substrate of claim 6, wherein any one of the third signal regions includes at least one of the power pins having a voltage value greater than the second voltage threshold;
the area of any one of the second signal regions is larger than the area of any one of the third signal regions.
8. The substrate according to claim 4, wherein,
At least two third signal areas are located in the first signal area, a part of the third signal areas and the first edge form a closed area, and the other part of the third signal areas and the second edge form a closed area.
9. The substrate of claim 8, wherein at least two of the first signal regions are symmetrical in a first direction and at least two of the third signal regions are symmetrical in the first direction;
at least two of the second signal regions are symmetrical in a second direction.
10. A chip assembly, comprising:
A chip;
The substrate of any one of claims 1 to 9, for packaging the chip, the chip being connected to a ground pin on the substrate.
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| CN202111116395.8A CN113838815B (en) | 2021-09-23 | 2021-09-23 | Substrate and chip assembly |
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| JP2013161959A (en) * | 2012-02-06 | 2013-08-19 | Sharp Corp | Semiconductor integrated circuit and electronic apparatus |
| CN104851863A (en) * | 2015-04-17 | 2015-08-19 | 华为技术有限公司 | Integrated circuit, lead bonding packaging chip and flip packaging chip |
| CN209981206U (en) * | 2019-07-09 | 2020-01-21 | 珠海奔图电子有限公司 | Chip packaging substrate, chip and image forming device |
| WO2020093277A1 (en) * | 2018-11-07 | 2020-05-14 | 北京比特大陆科技有限公司 | Chip and electrical equipment |
| CN113079634A (en) * | 2020-05-29 | 2021-07-06 | 新华三技术有限公司合肥分公司 | Circuit board and preparation process thereof |
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| TWI539565B (en) * | 2014-01-29 | 2016-06-21 | 森富科技股份有限公司 | Memory and layout method of memory ball pads |
| US10629533B2 (en) * | 2018-03-13 | 2020-04-21 | Toshiba Memory Corporation | Power island segmentation for selective bond-out |
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| JP2013161959A (en) * | 2012-02-06 | 2013-08-19 | Sharp Corp | Semiconductor integrated circuit and electronic apparatus |
| CN104851863A (en) * | 2015-04-17 | 2015-08-19 | 华为技术有限公司 | Integrated circuit, lead bonding packaging chip and flip packaging chip |
| WO2020093277A1 (en) * | 2018-11-07 | 2020-05-14 | 北京比特大陆科技有限公司 | Chip and electrical equipment |
| CN209981206U (en) * | 2019-07-09 | 2020-01-21 | 珠海奔图电子有限公司 | Chip packaging substrate, chip and image forming device |
| CN113079634A (en) * | 2020-05-29 | 2021-07-06 | 新华三技术有限公司合肥分公司 | Circuit board and preparation process thereof |
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Address after: 710075 4th floor, block a, No.38, Gaoxin 6th Road, Zhangba Street office, Gaoxin District, Xi'an City, Shaanxi Province Patentee after: Xi'an Ziguang Guoxin Semiconductor Co.,Ltd. Country or region after: China Address before: 710075 4th floor, block a, No.38, Gaoxin 6th Road, Zhangba Street office, Gaoxin District, Xi'an City, Shaanxi Province Patentee before: XI''AN UNIIC SEMICONDUCTORS Co.,Ltd. Country or region before: China |