CN113838800A - Metal interconnection structure and preparation method thereof, peripheral circuit, memory and system thereof - Google Patents

Metal interconnection structure and preparation method thereof, peripheral circuit, memory and system thereof Download PDF

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Publication number
CN113838800A
CN113838800A CN202111114268.4A CN202111114268A CN113838800A CN 113838800 A CN113838800 A CN 113838800A CN 202111114268 A CN202111114268 A CN 202111114268A CN 113838800 A CN113838800 A CN 113838800A
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layer
mandrel
memory
metal
forming
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颜丙杰
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

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Abstract

The application provides a preparation method of a metal interconnection structure, the metal interconnection structure, a peripheral circuit, an electronic device, a memory and a storage system, wherein the preparation method of the metal interconnection structure comprises the following steps: forming a plurality of mandrels arranged at intervals on a substrate, and forming side walls on two sides of the mandrels; forming a dielectric layer covering the mandrel and the side wall; removing part of the dielectric layer to expose the top surface of the side wall; removing the side wall to form a groove; and filling the trench with a metal layer. Compared with the conventional method of etching the substrate waiting etching layer by taking the residual side wall as the mask after the mandrel is etched to form the groove, the preparation method of the metal interconnection structure provided by the application can reduce the etching times, simplify the process steps, reduce the manufacturing cost and improve the yield of the finally formed semiconductor device product by removing the side wall used as the sacrificial layer to form the groove for accommodating the metal layer.

Description

Metal interconnection structure and preparation method thereof, peripheral circuit, memory and system thereof
Technical Field
The present disclosure relates to the field of semiconductor design and manufacturing, and more particularly, to a metal interconnection structure and a method for manufacturing the same, a peripheral circuit, a memory system, and an electronic device.
Background
After the semiconductor manufacturing technology enters the technology node of 24nm and below, it is often difficult to define the pattern size by photolithography, so that it is necessary to define the pattern size by using methods such as Self-Aligned Double Patterning (SADP), Self-Aligned quad Patterning (SAQP), and the like.
However, the conventional method for manufacturing the metal interconnection structure has some problems. For example, if the minimum feature size (CD) of a semiconductor device is to be further reduced to meet the requirements of a higher density semiconductor integrated circuit, it is necessary to rely on the development of more advanced photolithography techniques; in addition, the existing preparation method of the metal interconnection structure has more etching times and complicated process steps, and the yield of device products needs to be further improved.
Therefore, how to improve the production efficiency, simplify the process steps, and improve the product precision and yield is an urgent problem to be solved by the current method for manufacturing a metal interconnection structure.
Disclosure of Invention
The present application provides a metal interconnect structure and a method of manufacturing the same, a peripheral circuit, a memory system, and an electronic device that can at least partially solve the above-mentioned problems in the related art.
One aspect of the present application provides a method for manufacturing a metal interconnection structure, the method including: forming a plurality of mandrels arranged at intervals on a substrate, and forming side walls on two sides of the mandrels; forming a dielectric layer covering the mandrel and the side wall; removing part of the dielectric layer to expose the top surface of the side wall; removing the side wall to form a groove; and filling the trench with a metal layer.
In an embodiment of the present application, in a direction parallel to the arrangement of the mandrels, the thickness of the side wall is less than or equal to the thickness of the mandrel.
In one embodiment of the present application, removing a portion of the dielectric layer includes: and removing part of the dielectric layer by adopting a chemical mechanical polishing process, wherein the polishing operation for removing part of the dielectric layer is stopped at the surface of the mandrel far away from the substrate.
In one embodiment of the present application, forming the side walls on both sides of the mandrel includes: forming a preparation layer by adopting an atomic layer deposition process, wherein the preparation layer covers the mandrel; and removing the parts, located on the top surface of the mandrel and between the side walls of the mandrels, of the preparation layer to form the side walls.
In an embodiment of the present application, the sidewall has an etching selectivity greater than a set value with respect to the mandrel, so as to retain the mandrel when the sidewall is removed.
In one embodiment of the present application, the sidewall spacer includes at least one of a silicon nitride layer, a titanium nitride layer, and a titanium oxide layer.
In an embodiment of the present application, removing the sidewall spacers to form the trench includes: and removing the side wall by adopting a wet etching process or an atomic layer etching process.
In one embodiment of the present application, forming a plurality of mandrels with a predetermined interval therebetween on a substrate includes: forming a mandrel layer on the substrate; forming an etching mask layer covering the mandrel layer; patterning the etching mask layer to form a plurality of patterns of the mandrel; and etching the mandrel layer by taking the patterned etching mask layer as a mask to form a plurality of mandrels arranged at intervals.
In one embodiment of the present application, filling the trench with a metal layer includes: filling the groove; and removing a portion of the metal layer so that a top surface of the metal layer is flush with a top surface of the mandrel.
In one embodiment of the present application, filling the trench includes: and filling the groove by adopting at least one or any combination process of electroplating, chemical vapor deposition and physical vapor deposition.
In one embodiment of the present application, removing a portion of the metal layer includes: and removing part of the metal layer by adopting a chemical mechanical polishing process.
In an embodiment of the present application, in an arrangement direction parallel to the mandrel, the sidewall has a thickness W1, where: w1 is more than or equal to 20nm and less than or equal to 30 nm.
In one embodiment of the present application, the mandrel has a thickness W2 in a direction parallel to the alignment of the mandrel, wherein: w2 is more than or equal to 30nm and less than or equal to 50 nm.
Another aspect of the present application provides a metal interconnection structure, including: a substrate; and an interconnect layer disposed on the substrate and including: the device comprises a metal layer, a mandrel and an interlayer dielectric layer, wherein a groove is formed between the mandrel and the interlayer dielectric layer; the metal layer is arranged in the groove; and the metal layer has a uniform thickness in a direction parallel to the arrangement direction of the mandrels.
In one embodiment of the present application, the metal layer has a thickness equal to or less than a thickness of the mandrel in an arrangement direction parallel to the mandrel.
In one embodiment of the present application, the metal layer has a thickness W3 in a direction parallel to the alignment of the mandrels, wherein: w3 is more than or equal to 20nm and less than or equal to 30 nm.
Yet another aspect of the present application provides a peripheral circuit for connection with a memory circuit, the peripheral circuit comprising: a plurality of semiconductor devices arranged in an array; and the metal interconnection structure provided by the other aspect of the application is used for connecting the semiconductor device and the memory circuit.
Yet another aspect of the present application provides a memory, comprising: a storage array; and peripheral circuitry coupled to the memory array, wherein the peripheral circuitry includes a metal interconnect structure provided in another aspect of the present application.
In one embodiment of the present application, the memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.
Yet another aspect of the present application provides a storage system, including: a controller and a memory provided by yet another aspect of the present application, the controller coupled to the memory and configured to control the memory to store data.
In yet another aspect, an electronic device is provided that includes a memory as provided in yet another aspect of the present application.
In one embodiment of the present application, the electronic device includes at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.
Compared with a conventional method for etching a layer to be etched, such as a substrate, by using the remaining side wall as a mask after the mandrel is etched to form a groove, the metal interconnection structure and the preparation method thereof, the peripheral circuit, the electronic device, the memory and the storage system provided by at least one embodiment of the application can reduce the etching times, simplify the process steps, reduce the manufacturing cost and improve the yield of the finally formed semiconductor device product by removing the side wall serving as the sacrificial layer to form the groove for accommodating the metal layer.
In addition, the metal interconnection structure formed by the conventional method has a metal layer with a generally wide top and narrow bottom thickness (which can be understood as a thickness in an arrangement direction parallel to the mandrel), and the sidewall, the dielectric layer and the mandrel are prepared by different materials (for example, dielectric materials with different etching rates), so that the trench for accommodating the metal layer can be formed by only removing the sidewall without damaging the dielectric layer and the mandrel, and the metal layer of the metal interconnection structure provided by at least one embodiment of the present application has a uniform thickness (which can be understood as a thickness in an arrangement direction parallel to the mandrel). Therefore, the wiring density of the semiconductor integrated circuit is increased, the miniaturization of the semiconductor integrated circuit is realized, and the stability and the electrical property of the finally formed semiconductor device are improved.
Further, according to the metal interconnection structure and the manufacturing method thereof, the peripheral circuit, the electronic device, the memory, and the memory system according to at least one embodiment of the present application, in a direction parallel to the arrangement of the mandrels, the thickness of the sidewall is less than or equal to the thickness of the mandrels, so that the requirement of reducing the minimum feature size (CD) of a semiconductor device product to realize a higher density semiconductor integrated circuit can be satisfied without increasing additional production cost and process steps.
In addition, in at least one embodiment of the present application, a Chemical Mechanical Polishing (CMP) process is used to replace a conventional etching process in the step of removing a portion of the dielectric layer to expose the top surface of the sidewall, so that the roughness of the surfaces of the remaining dielectric layer, the sidewall and the mandrel can meet the requirements of the subsequent process steps, and the conductivity and yield of the finally formed semiconductor device product can be improved.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:
FIG. 1 is a flow chart of a method of fabricating a metal interconnect structure according to one embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of a structure formed after forming a mandrel layer on a substrate according to one embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a structure formed after forming an etch mask layer on a mandrel layer according to a method of fabricating a metal interconnect structure in accordance with one embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of a structure formed after patterning an etch mask layer in accordance with a method of fabricating a metal interconnect structure in accordance with one embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a structure formed after forming a plurality of mandrels spaced apart on a substrate according to a method of making a metal interconnect structure in accordance with an embodiment of the present application;
FIG. 6 is a schematic cross-sectional view of a structure formed after forming a preliminary layer covering a mandrel, in accordance with one embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a structure formed after forming sidewalls on both sides of a mandrel according to a method of forming a metal interconnect structure in accordance with one embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a structure formed after forming a dielectric layer covering a mandrel and sidewalls according to a method of forming a metal interconnect structure in accordance with an embodiment of the present application;
FIG. 9 is a schematic cross-sectional view of a structure formed after removing a portion of a dielectric layer to form a remaining dielectric layer in accordance with a method of forming a metal interconnect structure in accordance with one embodiment of the present application;
FIG. 10 is a schematic cross-sectional view of a structure formed after removing sidewalls to form a trench according to a method of fabricating a metal interconnect structure in accordance with an embodiment of the present application;
FIG. 11 is a schematic cross-sectional view of a structure formed after forming a metal layer in a trench according to a method of fabricating a metal interconnect structure in accordance with an embodiment of the present application;
FIG. 12 is a schematic cross-sectional view of a metal interconnect structure formed after removing a portion of a metal layer according to a method of forming a metal interconnect structure in accordance with one embodiment of the present application;
FIGS. 13A to 13F are schematic views illustrating a conventional method for fabricating a metal interconnection structure;
FIG. 14 is a schematic cross-sectional diagram of a peripheral circuit configuration according to one embodiment of the present application;
FIG. 15 is a schematic cross-sectional view of a memory structure according to an embodiment of the present application;
FIG. 16 is a schematic diagram of a storage system architecture according to an embodiment of the present application; and
fig. 17 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order.
In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
Further, in this document, when it is described that one portion is "on" another portion, the meanings of "on … …", "above … …" and "above … …", for example, should be interpreted in the broadest way such that "on … …" not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "on … …" or "above … …" does not absolutely mean above with reference to the direction of gravity, nor only means "above something" or "above something", but may also include the meaning of "above something" or "above something" with no intermediate features or layers therebetween (i.e., directly on something).
It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.
At least one embodiment of the application provides a metal interconnection structure and a preparation method thereof, a peripheral circuit, a memory, a storage system and an electronic device. The method comprises the steps of forming a plurality of mandrels arranged at intervals on a substrate, forming side walls on two sides of the mandrels, forming dielectric layers covering the mandrels and the side walls, removing part of the dielectric layers to expose the top surfaces of the side walls, removing the side walls to form grooves for containing metal layers, and filling the grooves with the metal layers to form the metal interconnection structure. In contrast to the conventional metal interconnection structure preparation method, the preparation method provided by the embodiment of the application can prepare the side wall, the dielectric layer and the mandrel by using different materials (for example, dielectric materials with different etching rates), and the side wall is used as a sacrificial layer, so that the etching times can be reduced, the process steps can be simplified, the manufacturing cost can be reduced, and the yield of the finally formed semiconductor device product can be improved by only removing the groove for accommodating the metal layer for forming the side wall.
In addition, the metal layer of the metal interconnection structure can be made to have a uniform thickness (which can be understood as a thickness in an arrangement direction parallel to the mandrel) by forming the trench for accommodating the metal layer only by removing the sidewall without damaging the dielectric layer and the mandrel. Therefore, the wiring density of the semiconductor integrated circuit is increased, the miniaturization of the semiconductor integrated circuit is realized, and the stability and the electrical property of the finally formed semiconductor device are improved.
In some embodiments, the dielectric material of the dielectric layer is formed using a low dielectric material, such that the formed dielectric layer has a low power saving constant. In some embodiments, the thickness of the sidewall is less than or equal to the thickness of the mandrel, so that the requirement of reducing the minimum feature size (CD) of a semiconductor device product to realize a higher density semiconductor integrated circuit can be met without increasing additional production cost and process steps.
In some embodiments, a Chemical Mechanical Polishing (CMP) process is used to replace the conventional etching process, and a portion of the dielectric layer is removed to expose the top surface of the sidewall, so that the roughness of the surfaces of the remaining dielectric layer, the sidewall and the mandrel can meet the requirements of the subsequent process steps, and the conductivity and yield of the finally formed semiconductor device product can be improved.
Fig. 1 is a flow chart of a method 1000 of fabricating a metal interconnect structure according to one embodiment of the present application. As shown in fig. 1, a method 1000 for fabricating a metal interconnect structure may include:
and S1, forming a plurality of mandrels arranged at intervals on the substrate, and forming side walls on two sides of the mandrels.
And S2, forming a dielectric layer covering the mandrel and the side wall.
And S3, removing part of the dielectric layer to expose the top surfaces of the side walls.
And S4, removing the side wall to form a groove.
And S5, filling the groove with a metal layer.
The specific processes of the steps of the method 1000 for manufacturing the metal interconnect structure will be described in detail with reference to fig. 2 to 12.
Step S1
Fig. 2 is a schematic cross-sectional view of a structure formed after forming a mandrel layer 200 on a substrate 100 according to a method of fabricating a metal interconnect structure in accordance with an embodiment of the present application. Fig. 3 is a schematic cross-sectional view of a structure formed after forming an etch mask layer 300 on the mandrel layer 200 according to a method of fabricating a metal interconnect structure in accordance with an embodiment of the present application. Fig. 4 is a schematic cross-sectional view of a structure formed after patterning an etch mask layer 300 according to a method of fabricating a metal interconnect structure in accordance with an embodiment of the present application. Fig. 5 is a schematic cross-sectional view of a structure formed after a plurality of mandrels 210 arranged at intervals are formed on a substrate 100 according to a method for manufacturing a metal interconnection structure in an embodiment of the present application. Fig. 6 is a schematic cross-sectional view of a structure formed after forming a preliminary layer 220 covering a mandrel 210 according to a method of fabricating a metal interconnect structure in accordance with an embodiment of the present application. Fig. 7 is a schematic cross-sectional view of a structure formed after forming sidewalls 230 on both sides of a mandrel 210 according to a method for fabricating a metal interconnect structure according to an embodiment of the present disclosure.
As shown in fig. 2 to 7, the step S1 of forming a plurality of mandrels arranged at intervals on the substrate and forming sidewalls on two sides of the mandrels may include: forming a mandrel layer 200 on a substrate 100; forming an etching mask layer 300 on the mandrel layer 200; patterning the etching mask layer 300; forming a plurality of mandrels 210 arranged at intervals; and forming a preparation layer 220 covering the mandrel 210, and forming side walls 230 on both sides of the mandrel 210.
Specifically, in one embodiment of the present application, a stacked structure may be formed first, and as an option, the stacked structure may be, in order from bottom to top: the semiconductor device includes a substrate 100, a mandrel layer 200, an etching mask layer 300, and a photoresist layer (not shown), wherein the mandrel layer 200 may be a spin-on carbon-containing material (SoC) layer, a silicon oxide layer, or the like, the etching mask layer 300 may be a hard mask layer, and further, the etching mask layer 300 may be selected from at least one of a polysilicon layer, a silicon oxynitride layer, and a silicon nitride layer. The above-mentioned laminated structure may further include other layers, and in addition, the above-mentioned substrate, mandrel layer, etching mask layer and photoresist layer may also be composite layers, and fig. 2 to 7 provided in this application simplify the structure of the above-mentioned layers, and it should be understood by those skilled in the art that the structural composition and specific structure of the above-mentioned layers may be changed to obtain the various results and advantages described in this specification without departing from the technical solution claimed in this application.
As shown in fig. 2 and 3, the above-described stacked structure including the substrate 100, the mandrel layer 200, the etch mask layer 300, and the photoresist layer in this order may be formed by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.
As shown in fig. 4 and 5, after the stacked structure is formed, the etch mask layer 300 may be etched using a patterned photoresist layer (not shown) as a mask to form a patterned etch mask layer 310 including a plurality of mandrel patterns; the mandrel layer 200 is then etched using the patterned etch mask layer 310 as a mask to form a plurality of mandrels 210 arranged at intervals.
As shown in fig. 6, in one embodiment of the present application, a plurality of mandrels 210 are arranged on one surface of the substrate 100 at a distance from each other. The arrangement direction of the plurality of mandrels 210 may be set to the X direction. After forming the plurality of mandrels 210, a preparation layer 220 covering the mandrels 210 may be formed by, for example, a deposition process, wherein the preparation layer 220 may include a preparation layer upper layer 220A formed on a top surface of the mandrels 210 (a surface of the mandrels 210 away from the substrate 100); a preparatory-layer-side layer 220B formed on both side wall surfaces of the mandrel 210 (the surface of the mandrel 210 perpendicular to the X direction); and a preparation layer bottom layer 220C covering the substrate 100 and located between sidewalls of the plurality of mandrels 210.
In one embodiment of the present application, the preparation layer 220 may be formed by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. Alternatively, the preparation layer 220 may be formed by an atomic layer deposition process, and the preparation layer 220 formed by the atomic layer deposition process may have better uniformity, so as to improve the performance of the finally formed semiconductor device.
In addition, as shown in fig. 6 and 7, the preparation layer upper layer 220A and the preparation layer lower layer 220C of the preparation layer 220 may be removed, and the preparation layer side layer 220B may be remained to form the side walls 230 on both sides of the mandrel 210. Portions of the preliminary layer 220 in the X direction may be removed to form the sidewalls 230, such as by a dry etch process or a combination of dry and wet etch processes. Specifically, as an option, a wet etching process or an atomic layer etching process may be used to remove a portion of the preparation layer 220 in the X direction to form the sidewall spacers 230.
Alternatively, in an embodiment of the present application, the sidewall spacers 230, the mandrel 210, and the subsequently formed dielectric layer may be respectively prepared from different dielectric materials (for example, dielectric materials with different etching rates), so that in the subsequent step, the trench for accommodating the metal layer may be formed by only removing the sidewall spacers without damaging the dielectric layers and the mandrel. So that the metal layer of the metal interconnect structure provided in at least one embodiment of the present application has a uniform thickness (which can be understood as a thickness in a direction parallel to the alignment direction of the mandrels). The wiring density of the semiconductor integrated circuit is improved, the miniaturization of the semiconductor integrated circuit is realized, and the stability and the electrical property of a finally formed semiconductor device are improved.
Alternatively, in one embodiment of the present application, the sidewall spacers 230 may include at least one of a silicon nitride layer, a titanium nitride layer, and a titanium oxide layer.
Alternatively, in an embodiment of the present application, the sidewall spacers 230 may have an etching selectivity greater than a set value with respect to the mandrel 210, so as to retain the mandrel 210 in a subsequent step of removing the sidewall spacers 230.
As shown in fig. 13A to 13F, taking the self-aligned dual patterning process in the conventional method for fabricating a metal interconnect structure as an example, the method may generally include the following steps: sequentially depositing and forming a first hard mask layer 2, a core material layer 3, a second hard mask layer 4 and a photoetching layer 5 on the surface of the layer 1 to be etched, and then photoetching to form a patterned photoetching layer 5; etching the second hard mask layer 4 using the patterned photoresist layer 5 as a mask to form a patterned second hard mask layer (not shown); etching the core material layer 3 by using the patterned second hard mask layer as a mask to form a plurality of mandrels 3' arranged at intervals; then removing the patterned second hard mask layer, and forming a side wall material layer 6 covering the mandrel 3' by a deposition process; removing parts, such as the horizontal direction (X direction), of the side wall material layer 6 by an etching process to form side walls 6'; removing the mandrel 3 ' by an etching process, and etching the first hard mask layer 2 by taking the side wall 6 ' as a mask to form a patterned first hard mask layer 2 '; etching the layer to be etched 1 with the patterned first hard mask layer 2' as a mask to form a trench 7; and filling the trench 7 with a metal layer.
After the conductor manufacturing technology enters the technology node of 24nm and below, the conventional preparation method of the metal interconnection structure can replace the photoetching process to define the pattern size. However, the above-described conventional method for manufacturing a metal interconnection structure has some problems. For example, if one wants to further shrink the minimum feature size (CD) of a device to meet the requirements of a higher density semiconductor integrated circuit, one needs to rely on developing more advanced photolithography techniques; in addition, the existing preparation method of the metal interconnection structure has more etching times, the process steps are complicated, and the product yield needs to be further improved.
Compared with the conventional method for etching the substrate waiting etching layer by using the residual side wall as the mask after the mandrel etching to form the groove for containing the metal layer, the preparation method of the metal interconnection structure provided by at least one embodiment of the application can form the groove for containing the metal layer by removing the side wall used as the sacrificial layer, so that the etching times can be reduced, the process steps can be simplified, the manufacturing cost can be reduced, and the yield of the final device product can be improved.
In addition, in an embodiment of the present application, the sidewall, the dielectric layer (formed in the subsequent step), and the mandrel may be prepared by different materials, for example, the sidewall, the dielectric layer, and the mandrel are prepared by using dielectric materials with different etching rates, so that the sidewall has an etching selection ratio greater than a set value with respect to the mandrel and the dielectric layer, respectively.
Therefore, under the condition that the dielectric layer and the mandrel are not damaged, the groove for accommodating the metal layer can be formed only by removing the side wall, so that the metal layer of the metal interconnection structure provided by at least one embodiment of the application has uniform thickness (which can be understood as the thickness in the direction parallel to the arrangement direction of the mandrel). Therefore, the wiring density of the semiconductor integrated circuit is increased, the miniaturization of the semiconductor integrated circuit is realized, and the stability and the electrical property of the finally formed semiconductor device are improved.
Further, as shown in fig. 7, in some embodiments, the thickness W1 of the sidewall 230 in the X direction may be greater than or equal to the thickness W2 of the mandrel 210 in the X direction. In addition, in some other embodiments, the thickness W1 of the sidewall 230 in the X direction may be less than or equal to the thickness W2 of the mandrel 210 in the X direction.
Specifically, in one embodiment of the present application, the thickness W1 of the sidewall 230 may satisfy 20nm ≦ W1 ≦ 30 nm. Further, in an embodiment of the present application, the thickness W2 of the mandrel 210 may satisfy 30nm ≦ W2 ≦ 50 nm.
Therefore, according to the method for manufacturing a metal interconnection structure in at least one embodiment of the present application, since the thickness of the sidewall may be less than or equal to the thickness of the mandrel in the direction parallel to the arrangement direction of the mandrel, in the process of forming the trench for accommodating the metal layer by removing the sidewall serving as the sacrificial layer, the requirement of reducing the minimum feature size (CD) of the semiconductor device product to realize a higher density semiconductor integrated circuit can be satisfied without increasing additional production cost and process steps.
The process of forming the metal-accommodating trench by removing the sidewall as the sacrificial layer and forming the metal interconnection structure will be described in detail in steps S2 to S5 with reference to fig. 8 to 12 in particular.
Step S2
Fig. 8 is a schematic cross-sectional view of a structure formed after forming a dielectric layer 400 covering the mandrel 210 and the sidewalls 230 according to a method for fabricating a metal interconnect structure in accordance with an embodiment of the present application.
As shown in fig. 8, the step S2 of forming a dielectric layer covering the mandrel and the sidewalls may include, for example: the dielectric layer 400 is formed overlying the mandrel 210 and the sidewalls 230 by one or more thin film deposition processes. The thin film deposition process may include, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, which is not limited in this application.
In one embodiment of the present application, the dielectric layer 400 may be formed using any one or a combination of a layer such as an NDC (Nitrogen doped Silicon carbide) layer, a TEOS (ethyl orthosilicate) layer, and a BD (Black Diamond) layer, wherein the BD layer may be made of a silica-based low dielectric constant material organosilicate glass (SiOC), for example, the BD layer may be formed by doping silica with low polarity molecules such as methyl and oxygen, and using Plasma Enhanced Chemical Vapor Deposition (PECVD).
In addition, the dielectric layer 400 may be selected to have a single layer structure or a composite layer structure. Specifically, as an alternative, a BD layer covering the mandrel 210 and the sidewall spacers 230 may be formed first, and then an NDC layer may be formed on the surface of the BD layer to form the dielectric layer 400 of the composite structure. However, it will be appreciated by those skilled in the art that the composition, structure, and process of formation of the dielectric layer can be varied to achieve the various results and advantages described herein without departing from the claimed subject matter.
Alternatively, in an embodiment of the present application, the sidewall spacers 230 may have an etching selectivity greater than a predetermined value with respect to the dielectric layer 400, so as to retain the dielectric layer 400 in the subsequent step of removing the sidewall spacers 230. Therefore, the groove for accommodating the metal layer can be formed only by removing the side wall 230 without damaging the dielectric layer 400 and the mandrel 210.
Step S3
Figure 9 is a schematic cross-sectional view of a structure formed after removing a portion of dielectric layer 400 to form a remaining dielectric layer 410, in accordance with a method of forming a metal interconnect structure in accordance with one embodiment of the present application.
As shown in fig. 9, the step S3 of removing a portion of the dielectric layer to expose the top surfaces of the sidewalls may include, for example: removing a portion of dielectric layer 400 to form a remaining dielectric layer 410 may be stopped at the top surface 211 of mandrel 210 remote from substrate 100 and exposing the top surfaces 231 of sidewalls 230, using a process such as a dry etching process or a combination of dry and wet etching processes, or performing other fabrication processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing.
In one embodiment of the present application, a portion of the dielectric layer 400 may be removed by a Chemical Mechanical Polishing (CMP) process to form the remaining dielectric layer 410, and the polishing to remove the portion of the dielectric layer 400 may stop at the top surface 211 of the mandrel 210 and expose the top surfaces 231 of the sidewalls 230. In other words, the top surface 211 of the mandrel 210 away from the substrate 100 may serve as a stop layer to limit the above polishing process, and ensure uniformity of the surface of the remaining dielectric layer 410 and the surface of the exposed sidewall spacers 230.
In addition, the chemical mechanical polishing process may at least include a main polishing step in which a chemical preparation with polishing particles is used as a polishing liquid to polish the dielectric layer 400, and a deionized water cleaning step; the downforce used in the deionized water cleaning process is in the same direction as the downforce used in the main grinding process, so that the roughness of the surfaces of the residual dielectric layer 410, the side wall 230 and the mandrel 210 meets the requirements. Further, the polishing parameters of the chemical mechanical polishing process may include a down force, a polishing time and a polishing rotation speed, and by adjusting the polishing parameters, the roughness of the surfaces of the remaining dielectric layer 410, the sidewall 230 and the mandrel 210 may be dynamically adjusted or trimmed to meet the requirements of the subsequent process steps.
Therefore, in at least one embodiment of the present application, a Chemical Mechanical Polishing (CMP) process is used to replace a conventional etching process in the step of removing a portion of the dielectric layer to expose the top surface of the sidewall, so that the roughness of the surfaces of the remaining dielectric layer, the sidewall and the mandrel can meet the requirements of the subsequent process steps, and the conductivity and yield of the finally formed semiconductor device product can be improved.
Step S4
Fig. 10 is a schematic cross-sectional view of a structure formed after removing the sidewall spacers 230 to form the trench 240 according to a method for fabricating a metal interconnect structure in an embodiment of the present application.
As shown in fig. 10, the step S4 of removing the sidewalls to form the trench may include, for example: the spacers 230 (as shown in fig. 9) are removed to form the trench 240, for example, by a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes.
In addition, in an embodiment of the present application, the sidewall spacers 230 may have an etching selectivity greater than a predetermined value with respect to the mandrel 210, so that the mandrel 210 may remain during the step of removing the sidewall spacers 230. Alternatively, other methods, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, may be used to retain the mandrel 210 during the step of removing the sidewall spacers 230. The present application is not limited to the specific embodiments.
In a conventional method for manufacturing a metal interconnection structure, forming a trench generally requires removing a mandrel through an etching process, and etching a hard mask layer by using a side wall as a mask to form a patterned hard mask layer; and etching the layer to be etched by using the patterned hard mask layer as a mask to form a groove for accommodating the metal layer. In the preparation method of the metal interconnection structure provided by the embodiment of the application, the groove for accommodating the metal layer is formed only by removing the side wall through an etching process. Therefore, the etching times in the preparation method of the metal interconnection structure can be reduced, the process steps are simplified, the manufacturing cost is reduced, and the product yield is improved.
Further, in some embodiments, the thickness W1 of the sidewall 230 in the X direction is less than or equal to the thickness W2 of the mandrel 210 in the X direction. Therefore, according to the method for manufacturing a metal interconnection structure in at least one embodiment of the present application, since the thickness of the sidewall may be less than or equal to the thickness of the mandrel in the direction parallel to the arrangement direction of the mandrel, in the process of forming the trench for accommodating the metal layer by removing the sidewall serving as the sacrificial layer, the requirement of reducing the minimum feature size of the product device to realize a higher density semiconductor integrated circuit may be satisfied without increasing additional production cost and process steps.
Alternatively, in some embodiments, the mandrel 210 may be further removed to enlarge the dimension of the trench 240 in the X direction according to the design requirements of the finally formed semiconductor device.
Step S5
Fig. 11 is a schematic cross-sectional view of a structure formed after forming a metal layer 500 in a trench 240 according to a method of fabricating a metal interconnect structure in an embodiment of the present application. Fig. 12 is a schematic cross-sectional view of a metal interconnect structure 2000 formed after removing a portion of a metal layer 500 according to a method for fabricating a metal interconnect structure in accordance with an embodiment of the present application;
as shown in fig. 11 and 12, the step S5 of filling the trench with the metal layer may include, for example: filling the trench 240 with an initial metal layer 500; and removing portions of the initial metal layer 500 such that a top surface 511 of the initial metal layer 500 is flush with the top surface 211 of the mandrel 210 to form the metal layer 510.
Specifically, the metal layer 500 covering the top surface 211 of the mandrel 210 and the top surface of the dielectric layer 400 and filling the trench 240 (as shown in fig. 10) may be formed by one or more thin film deposition processes. The thin film deposition process may include, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, which is not limited in this application. Alternatively, the metal layer 500 may be deposited using Electroplating (ECP).
After forming the initial metal layer 500, a portion of the initial metal layer 500 may be removed, such as by a Chemical Mechanical Polishing (CMP), to make the top surface 511 of the initial metal layer 500 flush with the top surface 211 of the mandrel 210 to form the metal layer 510.
In one embodiment of the present application, copper may be selected as a material for forming the metal layer 500 because copper has superior conductivity and filling property. However, it will be understood by those skilled in the art that the structure, composition and process of formation of the metal layer may be varied to achieve the various results and advantages described in this specification without departing from the claimed subject matter. In one embodiment of the present application, a metal interconnect structure 2000 in a semiconductor device, for example, may be formed by the above steps.
In addition, at least one embodiment of the present application also provides a metal interconnection structure 2000 prepared by the above method, and specifically, as shown in fig. 12, the metal interconnection structure 2000 may include: a substrate 100 and an interconnect layer disposed on the substrate 100, wherein the interconnect layer may include a residual dielectric layer 410 (an interlayer dielectric layer), a metal layer 510 and a mandrel 210, wherein a trench (not shown) is disposed between the mandrel 210 and the interlayer dielectric layer 410; the metal layer 510 is disposed in the groove and has a uniform thickness in a direction parallel to the arrangement direction (X direction) of the mandrels 210.
Compared with the metal interconnection structure formed by a conventional method of etching the layer to be etched to form the groove by using the residual side wall as the mask after etching the mandrel, the method and the device for forming the metal interconnection structure can reduce the etching times in the process of preparing the metal interconnection structure and simplify the process steps by removing the side wall used as the sacrificial layer to form the groove for accommodating the metal layer and finally forming the metal interconnection structure. Furthermore, the manufacturing cost of the metal interconnection structure can be reduced, and the yield of the finally formed semiconductor device product can be improved.
In addition, the trench for accommodating the metal layer is formed by removing the sidewall without damaging the dielectric layer and the mandrel, so that the metal layer of the metal interconnection structure provided by at least one embodiment of the present application has a uniform thickness (which can be understood as a thickness in a direction parallel to the alignment direction of the mandrel). Therefore, the wiring density of the semiconductor integrated circuit is increased, the miniaturization of the semiconductor integrated circuit is realized, and the stability and the electrical property of the finally formed semiconductor device are improved.
Further, the metal interconnection structure 2000 prepared according to at least one embodiment of the present application may have a thickness of the metal layer 510 in a direction parallel to the alignment direction of the mandrels 210 (in the X direction) that is equal to or less than the thickness of the mandrels 210. Alternatively, the range of the thickness W3 of the metal layer 510 in the direction parallel to the alignment of the mandrels 210 (in the X direction) may satisfy 20 nm. ltoreq. W3. ltoreq.30 nm. Therefore, the requirement of reducing the minimum feature size (CD) of the semiconductor device product to realize a higher density semiconductor integrated circuit can be satisfied without increasing additional production cost and process steps.
In addition, in at least one embodiment of the present application, in the process of forming the metal interconnect structure 2000, a Chemical Mechanical Polishing (CMP) process is used to replace a conventional etching process in the step of removing a portion of the dielectric layer to expose the top surface of the sidewall, so that the roughness of the surfaces of the remaining dielectric layer, the sidewall and the mandrel can meet the requirements of the subsequent process steps, and thus the conductivity and yield of the metal interconnect structure and the finally formed semiconductor device product can be improved.
FIG. 14 is a schematic cross-sectional diagram of a peripheral circuit configuration according to one embodiment of the present application.
As shown in fig. 14, at least one embodiment of the present application further provides a peripheral circuit 3000 including any of the metal interconnect structures 2000 described above. The peripheral circuit 3000 may include: capacitive, inductive or PN structures, etc. Specifically, the peripheral circuit 3000 for connection with the memory circuit may include a plurality of semiconductor devices arranged in an array; and a metal interconnect structure 2000 for connecting the semiconductor device with the memory circuit. The metal interconnect structure 2000 may be prepared by any of the methods described above.
In one embodiment of the present application, the semiconductor device may include a gate structure 3002 on the second substrate 3001, and source-drain doped regions 3003 respectively located in the second substrate 3001 and located at two sides of the gate structure 3002. In addition, the semiconductor device further includes a first contact plug 3004 contacting the gate structure 3002, and a second contact plug 3005 contacting the source-drain doped region 3003.
The metal interconnection structure 2000 may be connected with the first contact plug 3004 and the second contact plug 3005 to output an electrical signal of the semiconductor device. Further, a connection layer may be formed on the surface of the metal interconnection structure 2000 and connected to, for example, bit lines and conductive plugs of the memory.
Peripheral circuitry 3000 may include any suitable digital, analog, and/or mixed-signal circuitry for facilitating operation of the electronic device. For example, peripheral circuit 3000 may include one or more of the following: a data buffer (e.g., a bit line page buffer), a decoder (e.g., a row decoder or a column decoder), a sense amplifier, a charge pump, a current or voltage reference, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor). In some embodiments, the peripheral circuit 3000 is formed using Complementary Metal Oxide Semiconductor (CMOS) technology. FIG. 15 is a schematic cross-sectional view of a memory structure according to one embodiment of the present application. As shown in fig. 15, at least one embodiment of the present application further provides a memory 4000 including the metal interconnect structure 2000. The memory 4000 may include a memory array 4001 and a peripheral circuit 4002 connected to the memory array 4001. The peripheral circuit 4002 includes a metal interconnect structure 2000 provided in another aspect of the present application.
In one embodiment of the present application, the memory 4000 may be a two-dimensional memory or a three-dimensional memory. For example, it may be at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.
Specifically, taking a three-dimensional NAND memory as an example, the memory array 4001 may include a first substrate 4003 and a plurality of memory strings 4004 on the first substrate 4003. A first conductive plug 4005 is disposed over the memory string 4004. The peripheral circuit 4002 includes a plurality of semiconductor devices arranged in an array, a metal interconnection structure 2000, and a bit line 4006. Bit line 4006 has one end connected to first conductive plug 4005 and the other end connected to metal interconnect structure 2000 to implement electrical signal transmission in memory 4000.
Fig. 16 is a schematic structural diagram of a storage system 10000 according to an embodiment of the present application.
As shown in fig. 16, at least one embodiment of the present application also provides a memory system 10000. The memory system 10000 can include a memory 4000 and a controller 6000. The memory 4000 may be the same as the memory described in any of the above embodiments, and is not described in detail in this application. The memory system 10000 can be a two-dimensional memory system or a three-dimensional memory system, and the following description will take a three-dimensional memory system as an example.
The three-dimensional memory system 10000 can include a three-dimensional memory 4000, a host 5000, and a controller 6000. The three-dimensional memory 4000 may be the same as the three-dimensional memory described in any of the above embodiments, and details thereof are not repeated herein. The controller 6000 may control the three-dimensional memory 4000 through the channel CH, and the three-dimensional memory 4000 may perform operations based on the control of the controller 6000 in response to a request from the host 5000. The three-dimensional memory 4000 may receive a command CMD and an address ADDR from the controller 5000 through a channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 4000 may perform an internal operation corresponding to a command on an area selected by an address.
In some embodiments, the three-dimensional memory system may be implemented as a memory device such as a universal flash memory storage (UFS) device, a Solid State Disk (SSD), a multimedia card in the form of an MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Personal Computer Memory Card International Association (PCMCIA) card type memory device, a Peripheral Component Interconnect (PCI) type memory device, a PCI express (PCI-E) type memory device, a Compact Flash (CF) card, a smart media card, or a memory stick, and so forth.
Fig. 17 is a schematic structural diagram of an electronic apparatus 20000 according to an embodiment of the present application.
As shown in fig. 17, at least one embodiment of the present application further provides an electronic device 20000. The electronic device 20000 includes a memory 4000. The memory 4000 may be the same as the memory described in any of the above embodiments, and is not described in detail in this application. The electronic device 20000 may be a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, or other devices with a storage function. Thus, the other module 8000 of the electronic apparatus 20000 may be determined according to a specific device type of the electronic apparatus 20000, the other module 8000 may control the three-dimensional memory 4000 through a channel or the like, and the three-dimensional memory 4000 may receive a command CMD and an address ADDR from the other module 8000 through a channel or the like and access an area selected from the memory cell array in response to the address. This is not limited in this application.
The application provides a peripheral circuit, a memory, a storage system and an electronic device, and the metal interconnection structure provided by the application is arranged, so that the peripheral circuit, the memory, the storage system and the electronic device have the same beneficial effects as the metal interconnection structure, and the details are not repeated herein.
Furthermore, although an exemplary self-aligned patterning process and an exemplary metal interconnect structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added from the above-described methods or structures. Furthermore, the materials of the various layers illustrated are merely exemplary.
The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (22)

1. A method for preparing a metal interconnection structure, the method comprising:
forming a plurality of mandrels arranged at intervals on a substrate, and forming side walls on two sides of the mandrels;
forming a dielectric layer covering the mandrel and the side wall;
removing part of the dielectric layer to expose the top surface of the side wall;
removing the side wall to form a groove; and
and filling the groove with a metal layer.
2. The method of claim 1,
in the arrangement direction parallel to the mandrels, the thickness of the side wall is smaller than or equal to that of the mandrels.
3. The method of claim 1, wherein removing a portion of the dielectric layer comprises:
removing part of the dielectric layer by adopting a chemical mechanical polishing process,
and the grinding operation for removing part of the dielectric layer is stopped at the surface of the mandrel far away from the substrate.
4. The method of claim 1, wherein forming sidewalls on both sides of the mandrel comprises:
forming a preparation layer by adopting an atomic layer deposition process, wherein the preparation layer covers the mandrel; and
and removing the parts, located on the top surface of the mandrel and between the side walls of the mandrels, of the preparation layer to form the side walls.
5. The method of claim 1,
the side wall has an etching selection ratio relative to the mandrel which is greater than a set value so as to retain the mandrel when the side wall is removed.
6. The method of claim 1, wherein the sidewall spacers comprise at least one of a silicon nitride layer, a titanium nitride layer, and a titanium oxide layer.
7. The method of claim 1 or 3, wherein removing the sidewalls to form trenches comprises:
and removing the side wall by adopting a wet etching process or an atomic layer etching process.
8. The method of claim 1, wherein forming a plurality of mandrels with predetermined spacing from each other on a substrate comprises:
forming a mandrel layer on the substrate;
forming an etching mask layer covering the mandrel layer;
patterning the etching mask layer to form a plurality of patterns of the mandrel; and
and etching the mandrel layer by taking the patterned etching mask layer as a mask to form a plurality of mandrels arranged at intervals.
9. The method of claim 1, wherein filling the trench with a metal layer comprises:
filling the groove; and
removing a portion of the metal layer such that a top surface of the metal layer is flush with a top surface of the mandrel.
10. The method of claim 9, wherein filling the trench comprises:
and filling the groove by adopting at least one or any combination process of electroplating, chemical vapor deposition and physical vapor deposition.
11. The method of claim 9, wherein removing portions of the metal layer comprises:
and removing part of the metal layer by adopting a chemical mechanical polishing process.
12. The method according to any one of claims 1 to 11, wherein the sidewall has a thickness W1 in an alignment direction parallel to the mandrel, wherein:
20nm≤W1≤30nm。
13. the method according to any one of claims 1 to 11, wherein the mandrel has a thickness W2 in a direction parallel to the mandrel's alignment, wherein:
30nm≤W2≤50nm。
14. a metal interconnect structure, comprising:
a substrate; and
an interconnect layer disposed on the substrate and comprising: a metal layer, a mandrel and an interlayer dielectric layer,
a groove is formed between the mandrel and the interlayer dielectric layer;
the metal layer is arranged in the groove; and
the metal layer has a uniform thickness in a direction parallel to the arrangement direction of the mandrels.
15. The metal interconnect structure of claim 14,
and in the arrangement direction parallel to the mandrel, the thickness of the metal layer is less than or equal to that of the mandrel.
16. The metal interconnect structure of claim 14 or 15,
the metal layer has a thickness W3 in a direction parallel to the alignment of the mandrels, wherein: w3 is more than or equal to 20nm and less than or equal to 30 nm.
17. A peripheral circuit for connection to a memory circuit, the peripheral circuit comprising:
a plurality of semiconductor devices arranged in an array; and
the metal interconnect structure of any of claims 14 to 16, used to connect the semiconductor device with the memory circuit.
18. A memory, the memory comprising:
a storage array; and
peripheral circuitry coupled to the memory array,
wherein the peripheral circuitry comprises a metal interconnect structure as claimed in any one of claims 14 to 16.
19. The memory of claim 18, wherein the memory comprises at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.
20. A memory system comprising a controller and the memory of claim 18 or 19, the controller coupled to the memory and configured to control the memory to store data.
21. An electronic device, comprising: the memory of claim 18 or 19.
22. The electronic device of claim 21, wherein the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.
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CN103579084A (en) * 2012-07-20 2014-02-12 中芯国际集成电路制造(上海)有限公司 Method for forming parallel metal interconnection structures
CN107993979A (en) * 2017-11-24 2018-05-04 长江存储科技有限责任公司 A kind of preparation process of metal interconnection structure
CN113793852A (en) * 2021-09-15 2021-12-14 长江存储科技有限责任公司 Self-aligned pattern process method and metal interconnection structure

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