CN115274673A

CN115274673A - Memory, manufacturing method thereof and memory system

Info

Publication number: CN115274673A
Application number: CN202211034132.7A
Authority: CN
Inventors: 刘子琛; 刘威; 王言虹; 黄诗琪; 刘雅琴
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-08-26
Filing date: 2022-08-26
Publication date: 2022-11-01

Abstract

The embodiment of the disclosure discloses a memory, a manufacturing method thereof and a memory system, wherein the memory is provided with a first area and a second area, and comprises a first semiconductor structure and a second semiconductor structure which are bonded; the first semiconductor structure includes: the memory cell array is positioned in the first area and is electrically connected with the second semiconductor structure; a first electrode structure located at the second region, comprising: a first body portion extending in a first direction and a plurality of first projections extending from the first body portion in a second direction; a second electrode structure located in the second region, comprising: a second body portion extending in a first direction and a plurality of second projections extending from the second body portion in a second direction; wherein the first and second projecting portions are located between the first and second body portions, and the second projecting portion is located between two adjacent first projecting portions; a dielectric structure located between the first electrode structure and the second electrode structure.

Description

Memory, manufacturing method thereof and memory system

Technical Field

The embodiment of the disclosure relates to the field of integrated circuits, and in particular relates to a memory, a manufacturing method thereof and a memory system.

Background

The memory comprises a memory cell array and peripheral circuits, active devices and passive devices (such as capacitors) are usually arranged in the peripheral circuits, and as the integration level of the memory is improved, more capacitors or capacitors with larger capacitance values need to be arranged to meet the circuit requirements.

However, the capacitors with larger number or larger capacitance occupy larger area, so that the size of the formed memory is larger, which is not favorable for increasing the integration level of the memory.

Disclosure of Invention

According to a first aspect of embodiments of the present disclosure, there is provided a memory having a first region and a second region, the memory comprising a first semiconductor structure and a second semiconductor structure bonded; the first semiconductor structure includes:

the memory cell array is positioned in the first area and is electrically connected with the second semiconductor structure;

a first electrode structure located in the second region, comprising: a first body portion extending in a first direction and a plurality of first projections extending from the first body portion in a second direction; wherein the first direction and the second direction intersect;

a second electrode structure located in the second region, comprising: a second body portion extending in the first direction and a plurality of second projections extending from the second body portion in the second direction; wherein the first and second projecting portions are located between the first and second body portions, and the second projecting portion is located between two adjacent first projecting portions;

a dielectric structure located between the first electrode structure and the second electrode structure.

According to a second aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a memory, the memory having a first region and a second region and including a first semiconductor structure and a second semiconductor structure, the method comprising:

forming the first semiconductor structure, including:

forming a memory cell array;

forming a first electrode structure; wherein the first electrode structure comprises a first body portion extending in a first direction and a plurality of first projections extending from the first body portion in a second direction; wherein the first direction and the second direction intersect;

forming a second electrode structure; wherein the second electrode structure comprises a second body portion extending in the first direction and a plurality of second projections extending from the second body portion in the second direction; wherein the first and second projecting portions are located between the first and second body portions, and the second projecting portion is located between two adjacent first projecting portions;

forming a dielectric structure; wherein the dielectric structure is located between the first electrode structure and the second electrode structure;

bonding the first semiconductor structure and the second semiconductor structure; wherein the memory cell array is located in the first region; the first electrode structure and the second electrode structure are located in the second region.

According to a third aspect of embodiments of the present disclosure, there is provided a memory system including:

the memory of any of the above embodiments, configured to store data;

a memory controller coupled to the memory configured to control the memory.

In the embodiment of the disclosure, by providing that the first electrode structure includes the first body portion and a plurality of first protruding portions protruding from the first body portion, the second electrode structure includes the second body portion and a plurality of second protruding portions protruding from the second body portion, and the dielectric structure is located between the first electrode structure and the second electrode structure, the first electrode structure, the dielectric structure, and the second electrode structure can form a capacitor with a large capacitance value, which is beneficial to better meeting the circuit requirements. In addition, the first electrode structure, the dielectric structure and the second electrode structure in the first semiconductor structure are all located in the second area, the non-array area in the first semiconductor structure can be fully utilized, the space of the second semiconductor structure is not occupied, the circuit requirements are met, the size of the second semiconductor structure can be reduced, and the integration level of the memory is improved.

Generally, the capacitor is arranged in the second semiconductor structure (for example, a peripheral circuit wafer), and the embodiment of the disclosure reduces the area and the wiring difficulty of the second semiconductor structure by arranging the capacitor in the first semiconductor structure (for example, a memory array wafer) and bonding the first semiconductor structure and the second semiconductor structure, which is beneficial to further improving the integration level of the memory.

Drawings

FIG. 1 is a cross-sectional view of a memory shown in accordance with an embodiment of the present disclosure;

FIG. 2 is a top view of a memory shown in accordance with an embodiment of the present disclosure;

FIG. 3 is a schematic diagram illustrating a layout of a memory according to an embodiment of the present disclosure;

fig. 4 is a flow chart illustrating a method of fabricating a memory according to an embodiment of the present disclosure.

Detailed Description

The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It is understood that the meaning of "on 8230; \8230on," \8230, on, "\8230, 8230on," \8230, on top of the \8230shouldbe read in the broadest manner so that "on 8230;" \8230, on "not only means that it is" on "something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of" on "something with intervening features or layers therebetween.

In the embodiments of the present disclosure, the terms "first", "second", "third", and the like are used for distinguishing similar objects, and do not necessarily describe a particular order or sequence.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers.

The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.

A Dynamic Random Access Memory (DRAM) includes a Memory cell array and a peripheral circuit, and a large number of capacitors are required to be disposed in the peripheral circuit to implement functions such as Decoupling (Decoupling) of input/output signals and a charge pump (charge pump).

The capacitor in the peripheral circuit includes: a Metal-Oxide-Semiconductor (MOS) capacitor, a Metal-Oxide-Metal (MOM) capacitor, or a Metal-Insulator-Metal (MIM) capacitor is generally fabricated in a post-Metal interconnection process.

However, the capacitor and the related metal wiring occupy a large area, so that the size of the formed memory is large, which is not favorable for improving the integration level of the memory.

In addition, under the condition that the size of the memory is basically kept unchanged, along with the increase of the storage density of the memory, the occupied area of the memory cell array is increased, the space of a peripheral circuit and a metal wiring is continuously compressed, namely the space for arranging a capacitor in the memory is reduced, so that the number of the capacitors is reduced or the capacitance value is reduced, and the circuit requirements are difficult to meet.

In view of this, embodiments of the present disclosure provide a memory, a method for manufacturing the same, and a memory system.

Fig. 1 isbase:Sub>A cross-sectional view ofbase:Sub>A memory 300 according to an embodiment of the disclosure, and fig. 2 isbase:Sub>A top view of the memory 300 of fig. 1 alongbase:Sub>A linebase:Sub>A-base:Sub>A' according to an embodiment of the disclosure. As shown in conjunction with fig. 1 and 2, the memory 300 has a first region 300a and a second region 300b, the memory 300 including a first semiconductor structure 100 and a second semiconductor structure 200 bonded; the first semiconductor structure 100 includes:

a memory cell array located in the first region 300a and electrically connected to the second semiconductor structure 200;

the first electrode structure 106, located in the second region 300b, includes: a first body portion 106a extending in a first direction and a plurality of first protruding portions 106b extending from the first body portion 106a in a second direction; wherein the first direction and the second direction intersect;

the second electrode structure 107, located in the second region 300b, includes: a second body portion 107a extending in the first direction and a plurality of second protrusion portions 107b extending from the second body portion 107a in the second direction; wherein the first projecting portion 106b and the second projecting portion 107b are located between the first body portion 106a and the second body portion 107a, and the second projecting portion 107b is located between two adjacent first projecting portions 106b;

a dielectric structure 111 located between the first electrode structure 106 and the second electrode structure 107.

The first semiconductor structure 100 and the second semiconductor structure 200 may be wafers, or may be diced wafers, such as dies. The bonded first and

second semiconductor structures

100 and 200 include: bonded wafers and wafers, bonded wafers and dies, or bonded dies and dies, etc. The first region 300a may be an array region in the memory 300, i.e., a region where a memory cell array is disposed, and the second region 300b may be a non-array region (non-cell region) in the memory 300, i.e., a region where a memory cell array is not disposed.

The memory cell array may be a dynamic random access memory cell array comprising a plurality of memory cells, the memory cells comprising a transistor 101 and an energy storage element 105 coupled to the transistor, the energy storage element 105 may be a capacitor for storing charge.

The memory cell array may also be a phase change memory cell array comprising a plurality of memory cells including a transistor 101 and a storage element 105 coupled to the transistor, the storage element 105 enabling storage of information based on a difference in resistivity of a crystalline phase and an amorphous phase of a phase change material (e.g., chalcogenide).

The memory cell array may also be a ferroelectric random access memory cell array comprising a plurality of memory cells, the memory cells comprising a transistor 101 and a storage element 105 coupled to the transistor, the storage element 105 enabling storage of information based on a switching of a ferroelectric material between two polarization states under an external electric field.

Referring to fig. 1 and 2, the first electrode structure 106 includes a first body portion 106a and a plurality of first protrusion portions 106b, the first body portion 106a extending in the x-direction, the first protrusion portions 106b protruding from one side of the first body portion 106a and extending in the y-direction, and the plurality of first protrusion portions 106b being juxtaposed in the x-direction. The second electrode structure 107 includes a second body portion 107a and a plurality of second protrusion portions 107b, the second body portion 107a extending in the x-direction, the second protrusion portions 107b protruding from one side of the second body portion 107a and extending in the y-direction, the plurality of second protrusion portions 107b being juxtaposed in the x-direction.

It should be noted that the first direction and the second direction used in the present disclosure are respectively represented by an x direction and a y direction, and the z direction is perpendicular to a plane in which the x direction and the y direction are located. The x-direction intersects the y-direction, and the included angle between the x-direction and the y-direction includes an acute angle, a right angle, or an obtuse angle. In this example, the included angle between the x direction and the y direction is a right angle, i.e., the x direction and the y direction are perpendicular, and will not be described further herein.

Still referring to fig. 1 and 2, the first and second projecting

portions

106b and 107b are located between the first and

second body portions

106a and 107a, the second projecting portion 107b is located between adjacent ones of the first projecting portions 106b, one end of the first projecting portion 106b near the second body portion 107a is electrically insulated from the second body portion 107a, and one end of the second projecting portion 107b near the first body portion 106a is electrically insulated from the first body portion 106 a.

In some embodiments, the length of the first body portion 106a in the x-direction is the same as the length of the second body portion 107a in the x-direction. In other embodiments, the length of the first body portion 106a in the x-direction and the length of the second body portion 107a in the x-direction are different.

In some embodiments, the length of first projecting portion 106b in the y-direction is the same as the length of second projecting portion 107b in the y-direction. In other embodiments, the length of the first projecting portion 106b in the y direction and the length of the second projecting portion 107b in the y direction are different.

Dielectric structures 111 are located between the first body portion 106a and the second protruding portion 107b, between the first protruding portion 106b and the second protruding portion 107b, and between the first protruding portion 106b and the second body portion 107 a.

The material of the first electrode structure 106 and the second electrode structure 107 includes a conductive material, such as tungsten, tantalum, titanium, nickel, platinum, tungsten nitride, tantalum nitride, or titanium nitride. The materials of the first electrode structure 106 and the second electrode structure 107 may be the same or different.

The material of the dielectric structure 111 includes a dielectric material, such as silicon oxide, aluminum oxide, or hafnium oxide.

It should be noted that the first electrode structure 106, the dielectric structure 111 and the second electrode structure 107 may constitute a capacitor. In practical applications, one or more capacitors may be disposed in the second region according to design requirements, and the disclosure is not limited thereto.

In the embodiment of the disclosure, by providing that the first electrode structure includes the first body portion and a plurality of first protruding portions protruding from the first body portion, the second electrode structure includes the second body portion and a plurality of second protruding portions protruding from the second body portion, and the dielectric structure is located between the first electrode structure and the second electrode structure, the first electrode structure, the dielectric structure, and the second electrode structure can form a capacitor with a large capacitance value, which is beneficial to better meeting the circuit requirements. In addition, the first electrode structure, the dielectric structure and the second electrode structure in the first semiconductor structure are all located in the second area, the non-array area in the first semiconductor structure can be fully utilized, the space of the second semiconductor structure is not occupied, the circuit requirement is met, meanwhile, the size of the second semiconductor structure can be reduced, and the integration level of the memory is improved.

In some embodiments, as shown in conjunction with fig. 1 and 2, the first semiconductor structure 100 further includes:

a first contact plug 113 positioned between the first electrode structure 106 and the second semiconductor structure 200; wherein one end of the first contact plug 113 is electrically connected to the first electrode structure 106, and the other end of the first contact plug 113 is electrically connected to the second semiconductor structure 200;

a second contact plug between the second electrode structure 107 and the second semiconductor structure 200; one end of the second contact plug is electrically connected to the second electrode structure 107, and the other end of the second contact plug is grounded.

As shown in fig. 1 and 2, the memory 300 includes a first bonding structure 131 located in the bonding layer 130, and the first electrode structure 106 is electrically connected to the second semiconductor structure 200 through the first contact plug 113, for example, the first electrode structure 106 is electrically connected to the second semiconductor structure 200 through the first contact plug 113, the first conductive layer 114, and the first bonding structure 131. The second electrode structure 107 is grounded via a second contact plug (not shown), for example, the second electrode structure 107 is grounded via the second contact plug and the second conductive layer.

Here, the first contact plug 113 and the second contact plug are juxtaposed in the x direction, the first conductive layer 114 and the second conductive layer are juxtaposed in the x direction, and the bonding layer 130 is located between the first semiconductor structure 100 and the second semiconductor structure 200.

In other embodiments, the first contact plug 113 is located between the second electrode structure 107 and the second semiconductor structure 200, and the second electrode structure 107 is electrically connected to the second semiconductor structure 200 through the first contact plug 113; and a second contact plug between the first electrode structure 106 and the second semiconductor structure 200, wherein the first electrode structure 106 is grounded through the second contact plug.

The material of the first contact plug 113, the second contact plug, the first conductive layer 114, the second conductive layer, and the first bonding structure 131 includes a conductive material, for example, tungsten, tantalum, titanium, nickel, platinum, aluminum, copper, tungsten nitride, tantalum nitride, titanium nitride, or the like. The materials of any two of the first contact plug 113, the second contact plug, the first conductive layer 114, the second conductive layer, and the first bond structure 131 may be the same or different.

The material of the bonding layer 130 includes an insulating material, for example, silicon oxide or silicon nitride.

In the embodiment of the disclosure, by arranging the first contact plug between the first electrode structure and the second semiconductor structure and arranging the second contact plug between the second electrode structure and the second semiconductor structure, two electrode plates (i.e., the first electrode structure and the second electrode structure) of the capacitor can be respectively led out through the first contact plug and the second contact plug, so that the electrical connection between the capacitor and the second semiconductor structure can be realized to meet the circuit requirements. And the first electrode structure and the second electrode structure are respectively led out through the first contact plug and the second contact plug, so that the integration level of the memory is improved, and the difficulty of metal wiring in the memory is favorably reduced.

In some embodiments, referring to fig. 1, the memory cell array includes: a transistor 101; the first semiconductor structure 100 further includes: the dummy transistor 102 is juxtaposed to the transistor 101 in the second direction and is located in the second region 300b. In practical application, a plurality of transistors are arranged in the array area, namely, the array area has a large area of silicon material.

In some embodiments, referring to fig. 1, the first semiconductor structure 100 further includes:

a first contact plug 113 between the first electrode structure 106 and the second semiconductor structure 200; one end of the first contact plug 113 is electrically connected to the first electrode structure 106, and the other end of the first contact plug 113 is electrically connected to the second semiconductor structure 200;

the source or drain of the dummy transistor 102 is electrically connected to the second electrode structure 107, and the drain or source of the dummy transistor 102 is grounded.

Referring to fig. 1, the transistor 101 includes a source, a channel and a drain juxtaposed in the z-direction, and the energy storage element 105 includes a first electrode plate (not shown), an energy storage medium 103 and a second electrode plate 104 juxtaposed in the z-direction, where the first electrode plate is located between the transistor 101 and the energy storage medium 103. In one example, a source of the transistor 101 is electrically connected to the first electrode plate, and a drain of the transistor 101 is electrically connected to the bit line 108. In another example, a drain of the transistor 101 is electrically connected to the first electrode plate, and a source of the transistor 101 is electrically connected to the bit line 108.

In some embodiments, referring to fig. 1, the first semiconductor structure 100 further includes: a conductive connection layer (not shown) is located between transistor 101 and bit line 108. The material of the connection layer includes metal silicide, such as tungsten silicide or titanium silicide. By providing a conductive connection layer between the bit line 108 and the transistor 101, the contact resistance between the bit line and the drain or source of the transistor can be reduced.

The dummy transistor 102 is juxtaposed with the transistor 101 in the x direction, the dummy transistor 102 includes a source, a channel, and a drain juxtaposed in the z direction, the first electrode structure 106 is electrically connected to the second semiconductor structure 200 through the first contact plug 113, and the second electrode structure 107 is grounded through the dummy transistor 102.

In other embodiments, the first contact plug 113 is located between the second electrode structure 107 and the second semiconductor structure 200, and the second electrode structure 107 is electrically connected to the second semiconductor structure 200 through the first contact plug 113; the first electrode structure 106 is grounded through the dummy transistor 102.

It should be noted that, in practical applications, the dummy transistor may be heavily doped, for example, the source, the channel, and the drain of the dummy transistor are heavily doped, so as to ensure good electrical connection between the second electrode structure and the dummy transistor, where the first electrode structure is led out through the first contact plug, and the second electrode structure is led out through the heavily doped dummy transistor.

In the embodiment of the disclosure, by disposing the first contact plug between the first electrode structure and the second semiconductor structure and disposing the dummy transistor in the second region, two plates of the capacitor (i.e., the first electrode structure and the second electrode structure) can be respectively led out through the first contact plug and the dummy transistor, so that the electrical connection between the capacitor and the second semiconductor structure can be realized to meet the circuit requirement. In addition, the first contact plug and the dummy transistor are respectively positioned on two sides of the capacitor, so that the integration level of the memory is improved, and the difficulty of metal wiring in the memory is reduced.

In other embodiments, the first semiconductor structure further comprises: a second contact plug between the second electrode structure and the energy storage element; one end of the second contact plug is electrically connected to the second electrode structure 107, and the other end of the second contact plug is grounded. It can be understood that, in the embodiments of the present disclosure, the second electrode structure may also be led out through a second contact plug different from the dummy transistor, that is, the second electrode structure may be led out from the wafer side of the memory array, and the first contact plug and the second contact plug are respectively located on two sides of the capacitor, which is beneficial to reducing the difficulty of metal wiring in the memory while improving the integration level of the memory.

In some embodiments, as shown with reference to fig. 1 and 2, dielectric structure 111 includes:

a first sub-dielectric structure 109 located between the first electrode structure 106 and the second electrode structure 107;

at least two second sub-dielectric structures; wherein the first second sub-dielectric structure 110a is located between the first electrode structure 106 and the first sub-dielectric structure 109, and the second sub-dielectric structure 110b is located between the second electrode structure 107 and the first sub-dielectric structure 109; the dielectric constant of the second sub-dielectric structure is larger than the dielectric constant of the first sub-dielectric structure 109.

The first sub-dielectric structure 109 may be a low dielectric constant material, such as silicon oxide, and the first second sub-dielectric structure 110a and the second sub-dielectric structure 110b may be a high dielectric constant material, such as aluminum oxide or hafnium oxide. The number of the second sub-dielectric structures is not limited to two, but may be more.

In some embodiments, the dielectric constant of the second sub-dielectric structure is greater than 3.9.

It should be noted that the first second sub-dielectric structure 110a and the second sub-dielectric structure 110b are both second sub-dielectric structures, and the materials included in the second sub-dielectric structures may be the same or different, and different reference numerals are only used to distinguish the difference in position between the two second sub-dielectric structures, and are not necessarily used to describe a specific order or sequence.

In the embodiment of the disclosure, the dielectric structure comprises the first sub-dielectric structure and at least two second sub-dielectric structures, and the dielectric constant of the second sub-dielectric structure is greater than that of the first sub-dielectric structure, so that the overall dielectric constant of the dielectric structure can be increased, the capacitance value of the capacitor can be increased, and the circuit requirements can be better met.

In some embodiments, referring to fig. 1, the first semiconductor structure 100 further includes: and an isolation structure 112 located in the second region 300b and located between the first electrode structure 106 and the memory cell array and between the second electrode structure 107 and the memory cell array. For example, the isolation structures 112 are located between the first electrode structure 106 and the transistor 101, between the second electrode structure 107 and the transistor 101, and between the dummy transistor 102 and the transistor 101. The material of the isolation structure 112 includes an insulating material, such as silicon oxide or silicon nitride.

In the embodiment of the disclosure, the isolation structures are arranged between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array, so that the coupling between the capacitor and the memory cell array is favorably reduced.

In some embodiments, referring to fig. 2, an isolation structure 112 is disposed around the first electrode structure 106, the second electrode structure 107, and the dielectric structure 111. It is understood that in the present embodiment, the isolation structure 112 is an isolation ring, which can better isolate the capacitor from the memory cell array, and is beneficial to further reduce the coupling between the capacitor and the memory cell array. In other embodiments, the isolation structure 112 may also be an isolation wall.

In some embodiments, referring to fig. 1, the first semiconductor structure 100 further includes: a bit line 108 located in the first region 300a and between the memory cell array and the second semiconductor structure 200; wherein, the memory cell array and the second semiconductor structure 200 are electrically connected through the bit line 108; the material of the bit line 108, the material of the first electrode structure 106, and the material of the second electrode structure 107 are the same.

Referring to fig. 1, the memory 300 further includes a second bonding structure 132 in the bonding layer 130, the bit line 108 is located between the transistor 101 and the second bonding structure 132, and the bit line 108 may be electrically connected to the second semiconductor structure 200 through the third contact plug 115, the third conductive layer 116, and the second bonding structure 132.

Here, the first contact plug 113, the second contact plug, and the third contact plug 115 are juxtaposed in the x direction, and the first conductive layer 114, the second conductive layer, and the third conductive layer 116 are juxtaposed in the x direction.

The materials of the bit line 108, the third contact plug 115, the third conductive layer 116, and the second bonding structure 132 include conductive materials, such as tungsten, tantalum, titanium, nickel, platinum, aluminum, copper, tungsten nitride, tantalum nitride, titanium nitride, or the like. The materials of any two of the bit line 108, the third contact plug 115, the third conductive layer 116, and the second bond structure 132 may be the same or different.

In some embodiments, the material of the bit line 108, the material of the first electrode structure 106, and the material of the second electrode structure 107 are the same. Thus, the bit line 108, the first electrode structure 106 and the second electrode structure 107 can be formed in the same manufacturing process, which is beneficial to saving the manufacturing process and reducing the manufacturing cost.

In some embodiments, the material of the first contact plug 113, the material of the second contact plug, and the material of the third contact plug 115 are the same. Thus, the first contact plug 113, the second contact plug, and the third contact plug 115 can be formed in the same manufacturing process, which is beneficial to saving the manufacturing process and reducing the manufacturing cost.

In some embodiments, the material of the first conductive layer 114, the material of the second conductive layer, and the material of the third conductive layer 116 are the same. Thus, the first conductive layer 114, the second conductive layer, and the third conductive layer 116 can be formed in the same manufacturing process, which is beneficial to saving the manufacturing process and reducing the manufacturing cost.

In some embodiments, the second semiconductor structure 200 includes peripheral circuitry. Referring to fig. 1, the peripheral circuit includes a transistor 202, and a source, a channel, and a drain of the transistor 202 are located in a substrate 201. The second semiconductor structure 200 further includes a shallow trench isolation 203, an insulating layer 204 and an interconnect structure 205, the shallow trench isolation 203 is located between two adjacent transistors 202, the insulating layer 204 covers the substrate 201 and the peripheral circuit, the interconnect structure 205 is located in the insulating layer 204, and the peripheral circuit is electrically connected to the memory cell array through a portion of the interconnect structure 205 and electrically connected to the first electrode structure 106 or the second electrode structure 107 through another portion of the interconnect structure.

Fig. 3 is a schematic diagram illustrating a layout of a memory according to an embodiment of the disclosure. Referring to fig. 3, the second semiconductor structure 200 includes peripheral circuits including a sense amplifier 206, a word line driver 207, a logic control circuit 208, and the like. It should be understood that in some examples, additional peripheral circuitry not shown in fig. 3 may also be included.

Still referring to fig. 3, the first semiconductor structure 100 includes an array region 100a and a non-array region 100b, the array region 100a may be a region of the first semiconductor structure 100 where the memory cell array is disposed, the non-array region 100b may be a region of the first semiconductor structure 100 where the memory cell array is not disposed, and the first electrode structure 106, the dielectric structure 111, and the second electrode structure may be located in the non-array region 100 b.

In the embodiment of the disclosure, by arranging the peripheral circuit in the second semiconductor structure and arranging the memory cell array in the first semiconductor structure, the peripheral circuit and the memory cell array can be connected in a bonding manner, so that the plane size of the memory is reduced, and the first electrode structure, the dielectric structure and the second electrode structure are arranged in the non-array area of the first semiconductor structure without occupying the space of the second semiconductor structure, so that the size of the second semiconductor structure can be reduced while the circuit requirements are met, and the integration level of the memory is improved.

In some embodiments, memory 300 includes: a three-dimensional memory.

In some embodiments, the three-dimensional memory comprises: dynamic random access memory, phase change memory, ferroelectric memory, or the like.

Fig. 4 is a flowchart illustrating a method for manufacturing a memory according to an embodiment of the present disclosure, the memory having a first region and a second region and including a first semiconductor structure and a second semiconductor structure, and referring to fig. 4, the method at least includes the following steps:

s100: forming a first semiconductor structure comprising: forming a memory cell array; forming a first electrode structure; wherein the first electrode structure includes a first body portion extending in a first direction and a plurality of first projection portions extending from the first body portion in a second direction; wherein the first direction and the second direction intersect; forming a second electrode structure; wherein the second electrode structure includes a second body portion extending in the first direction and a plurality of second protrusion portions extending from the second body portion in the second direction; wherein the first and second projecting portions are located between the first and second body portions, and the second projecting portion is located between two adjacent first projecting portions; forming a dielectric structure; wherein the dielectric structure is located between the first electrode structure and the second electrode structure;

s200: bonding the first semiconductor structure and the second semiconductor structure; the memory cell array is positioned in the first area; the first electrode structure and the second electrode structure are located in the second region.

For example, in step S100, a memory cell array as shown in fig. 1 may be formed by using a thin film deposition, photolithography, etching, and the like, and the memory cell array is located in the array region 100a shown in fig. 3.

The thin film deposition process includes, but is not limited to, a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process, or a combination thereof. The photolithography process includes, but is not limited to, an I-line photolithography process, a KrF photolithography process, an ArF photolithography process, or an immersion ArF photolithography process. The etching process includes, but is not limited to, a dry etching process, a wet etching process, or a combination thereof.

For example, in step S100, the first electrode structure 106, the second electrode structure 107 and the dielectric structure 111 shown in fig. 1 or fig. 2 may be formed by using a thin film deposition, photolithography, etching and the like, and the first electrode structure 106, the second electrode structure 107 and the dielectric structure 111 are located in the non-array region 100b shown in fig. 3.

Illustratively, in step S200, the memory 300 shown in fig. 1 may be formed by using a flip-chip bonding process, and the first semiconductor structure 100 and the second semiconductor structure 200 are electrically connected through the second bonding structure 132 at the bonding interface.

In the step S100, the order of forming the memory cell array, forming the first electrode structure, and forming the second electrode structure is not particularly limited. For example, at least two of the memory cell array, the first electrode structure and the second electrode structure may be formed simultaneously or sequentially, and the disclosure is not limited thereto, depending on actual process requirements.

In the embodiment of the disclosure, by forming a first electrode structure including a first body portion and a plurality of first protruding portions protruding from the first body portion, forming a second electrode structure including a second body portion and a plurality of second protruding portions protruding from the second body portion, and forming a dielectric structure located between the first electrode structure and the second electrode structure, the first electrode structure, the dielectric structure, and the second electrode structure can form a capacitor with a large capacitance value, which is beneficial to better meet circuit requirements. And the first electrode structure and the second electrode structure are both positioned in the second area after bonding, so that the non-array area in the first semiconductor structure can be fully utilized without occupying the space of the second semiconductor structure, the circuit requirement is met, the size of the second semiconductor structure can be reduced, and the integration level of the memory is improved.

Generally, a capacitor is formed in a second semiconductor structure (e.g., a peripheral circuit wafer), and the embodiments of the present disclosure reduce the area and the wiring difficulty of the second semiconductor structure by forming the capacitor in a first semiconductor structure (e.g., a memory array wafer) and bonding the first semiconductor structure and the second semiconductor structure, which is beneficial to further improving the integration level of the memory.

In some embodiments, the forming the memory cell array includes: forming a transistor;

the step S100 further includes:

forming a dummy transistor; the dummy transistor and the transistor are arranged in parallel along a second direction; the source electrode or the drain electrode of the dummy transistor is electrically connected with the second electrode structure, and the drain electrode or the source electrode of the dummy transistor is grounded;

forming a first contact plug after forming the dummy transistor; one end of the first contact plug is electrically connected with the first electrode structure;

the step S200 includes: bonding the first contact plug and the second semiconductor structure; the first contact plug is positioned between the first electrode structure and the second semiconductor structure, and the other end of the first contact plug is electrically connected with the second semiconductor structure; the dummy transistor is located in the second region.

Illustratively, the transistors 101 and the dummy transistors 102 shown in fig. 1 may be formed by photolithography, etching, doping, and the like, the transistors 101 and the dummy transistors 102 are juxtaposed in the x-direction, the transistors 101 are located in the array region 100a shown in fig. 3, and the dummy transistors 102 are located in the non-array region 100b shown in fig. 3. The transistor 101 and the dummy transistor 102 may be formed simultaneously or separately. In one embodiment, the transistor 101 and the dummy transistor 102 are formed simultaneously. Therefore, the manufacturing process can be reduced, and the manufacturing cost is saved. After the transistor 101 is formed, the energy storage element 105 shown in fig. 1 is formed. It should be understood that the memory cell array includes a transistor 101 and an energy storage element 105.

After the energy storage element 105 is formed, the transistor 101 and the dummy transistor 102 are inverted so that the source or drain of the transistor 101 and the dummy transistor 102 are directed upward, a dielectric material layer covering the transistor 101 and the dummy transistor 102 is formed, and the first electrode structure 106 and the second electrode structure 107 shown in fig. 1 or 2 are formed in the dielectric material layer, and the remaining dielectric material layer is the dielectric structure 111. Before inversion, a dielectric layer covering an end of the dummy transistor 102 away from the first electrode structure 106 may be formed and planarized to meet the flatness requirement of the subsequent process.

A first insulating material layer covering the first electrode structure 106, the dielectric structure 111 and the second electrode structure 107 is formed, and a first contact plug 113 as shown in fig. 1 is formed in the first insulating material layer, and the first semiconductor structure and the second semiconductor structure are bonded such that the first electrode structure is electrically connected to the second semiconductor structure through the first contact plug. The material of the first insulating material layer includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

In the embodiment of the disclosure, by forming the dummy transistor and the first contact plug which are arranged in parallel with the transistor along the second direction, two electrode plates (i.e. the first electrode structure and the second electrode structure) of the capacitor can be respectively led out through the first contact plug and the dummy transistor, so that the electrical connection between the capacitor and the second semiconductor structure can be realized to meet the circuit requirement. In addition, the first contact plug and the dummy transistor are respectively positioned on two sides of the capacitor, so that the integration level of the memory is improved, and the difficulty of metal wiring in the memory is reduced.

In some embodiments, the step S100 further includes:

forming a first contact plug; one end of the first contact plug is electrically connected with the first electrode structure;

forming a second contact plug; one end of the second contact plug is electrically connected with the second electrode structure;

the step S200 includes: bonding the first contact plug, the second contact plug and the second semiconductor structure; the first contact plug is positioned between the first electrode structure and the second semiconductor structure, and the other end of the first contact plug is electrically connected with the second semiconductor structure; the second contact plug is positioned between the second electrode structure and the second semiconductor structure, and the other end of the second contact plug is grounded.

For example, a first contact hole and a second contact hole may be formed in the first insulating material layer through an etching process, a bottom of the first contact hole exposing the first electrode structure, e.g., a bottom of the first contact hole exposing the first body portion, and a bottom of the second contact hole exposing the second electrode structure, e.g., a bottom of the second contact hole exposing the second body portion, a conductive material is filled into the first contact hole to form a first contact plug, one end of the first contact plug is electrically connected to the first body portion, a conductive material is filled into the second contact hole to form a second contact plug, and one end of the second contact plug is electrically connected to the second body portion. And bonding the first semiconductor structure and the second semiconductor structure, so that the first electrode structure is electrically connected with the second semiconductor structure through the first contact plug, and the second electrode structure is grounded through the second contact plug.

In the embodiment of the disclosure, by forming the first contact plug and the second contact plug and bonding the first contact plug, the second contact plug and the second semiconductor structure, two electrode plates (i.e., the first electrode structure and the second electrode structure) of the capacitor can be respectively led out through the first contact plug and the second contact plug, so that the electrical connection between the capacitor and the second semiconductor structure can be realized to meet the circuit requirements. And the first electrode structure and the second electrode structure are respectively led out through the first contact plug and the second contact plug, so that the integration level of the memory is improved, and the difficulty of metal wiring in the memory is reduced.

In some embodiments, the dielectric structure comprises: a first sub-dielectric structure and at least two second sub-dielectric structures; wherein the dielectric constant of the second sub-dielectric structure is greater than the dielectric constant of the first sub-dielectric structure; the above-described forming a dielectric structure includes:

forming a first sub-dielectric material layer covering the dummy transistor;

forming first and second grooves penetrating the first sub-dielectric material layer and alternating in a first direction; wherein, the remaining first sub-dielectric material layer is a first sub-dielectric structure;

forming a first second sub-dielectric structure covering the side wall of the first groove, and forming the first sub-groove based on the appearance of the first groove;

forming a second sub-dielectric structure covering the side wall of the second groove, and forming a second sub-groove based on the appearance of the second groove;

the above-described forming of the first electrode structure includes: forming a first protrusion portion in the first sub-groove;

the above-mentioned second electrode structure of formation includes: a second projection is formed in the second sub-groove.

Illustratively, the first sub-dielectric material layer is etched downwards along the z direction to form a plurality of first grooves which are arranged in parallel along the x direction and a third groove which extends along the x direction, the plurality of first grooves are communicated with the third groove to form a first second sub-dielectric structure which covers the side wall of the first groove, and the first groove which is formed with the first second sub-dielectric structure is filled with a conductive material to form a first protruding part. It should be understood that, when the first second sub-dielectric structure is formed to cover the sidewall of the first groove, the first second sub-dielectric structure covers the sidewall of the third groove, and when the conductive material is filled into the first groove in which the first second sub-dielectric structure is formed, the conductive material fills the third groove in which the first second sub-dielectric structure is formed, that is, the first body portion is formed. The material of the first sub-dielectric material layer includes an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.

It should be noted that, in this example, the first groove and the third groove are formed at the same time, and the first protruding portion and the first body portion are formed at the same time, so that the manufacturing process can be reduced, and the manufacturing cost can be saved. In other embodiments, the first recess and the third recess may be formed separately and the first projection and the first body portion may be formed separately.

Illustratively, the first sub-dielectric material layer is etched downwards along the z direction to form a plurality of second grooves arranged side by side along the x direction and a fourth groove extending along the x direction, the plurality of second grooves are communicated with the fourth groove, the second groove is positioned between two adjacent first convex parts, the first convex parts and the second groove are positioned between the first body part and the fourth groove to form a second sub-dielectric structure covering the side wall of the second groove, and the second groove formed with the second sub-dielectric structure is filled with a conductive material to form second convex parts. It should be understood that, when forming the second sub-dielectric structure covering the sidewalls of the second groove, the second sub-dielectric structure covers the sidewalls of the fourth groove, and when filling the second groove formed with the second sub-dielectric structure with the conductive material, the conductive material fills the fourth groove formed with the second sub-dielectric structure, i.e., forms the second body portion.

It should be noted that, in this example, the second groove and the fourth groove are formed at the same time, and the second protruding portion and the second body portion are formed at the same time, so that the manufacturing process can be reduced, and the manufacturing cost can be saved. In other embodiments, the second recess and the fourth recess may be formed separately and the second projection and the second body portion may be formed separately.

In the embodiment of the disclosure, by forming the dielectric structure including the first sub-dielectric structure and the at least two second sub-dielectric structures, since the dielectric constant of the second sub-dielectric structure is greater than that of the first sub-dielectric structure, the dielectric constant of the whole dielectric structure can be increased, which is beneficial to increasing the capacitance value of the capacitor, thereby better satisfying the circuit requirements.

In some embodiments, the step S100 further includes:

forming a first sub-dielectric material layer covering the transistor while forming the first sub-dielectric material layer covering the dummy transistor;

forming a bit line groove penetrating through the first sub-dielectric material layer; the transistor is exposed at the bottom of the bit line groove;

forming a bit line in the bit line groove while forming the first protrusion portion in the first sub-groove; alternatively, the bit line is formed in the bit line groove while the second protrusion portion is formed in the second sub-groove.

Illustratively, in forming the first sub-dielectric material layer covering the dummy transistor, the first sub-dielectric material layer covering the transistor is formed; when the first recess is formed, a bit line recess penetrating the first sub-dielectric material layer is formed, and when the first protrusion portion is formed in the first sub-recess, a bit line is formed in the bit line recess, or, when the second recess is formed, a bit line recess penetrating the first sub-dielectric material layer is formed, and when the first protrusion portion is formed in the second sub-recess, a bit line is formed in the bit line recess.

In the embodiment of the disclosure, the bit line and the first protruding portion or the second protruding portion can be formed in the same manufacturing process, which is beneficial to saving the manufacturing process and reducing the manufacturing cost.

In some embodiments, the step S100 further includes:

forming an isolation structure; the isolation structures are located in the second region, and located between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array.

Illustratively, isolation trenches are formed through the first sub-dielectric material layer, the isolation trenches being located between the first electrode structure and the transistor, between the second electrode structure and the transistor, and between the dummy transistor and the transistor, and the isolation trenches are filled with an isolation material to form isolation structures 112 as shown in fig. 1.

In the embodiment of the disclosure, by forming the isolation structures between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array, the coupling between the capacitor and the memory cell array is reduced.

Embodiments of the present disclosure also provide a memory system, including:

the memory 300 in any of the above embodiments, configured to store data;

a memory controller, coupled to the memory 300, is configured to control the memory 300.

The memory system may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having storage therein.

In some embodiments, the memory controller is designed for operation in a low duty cycle environment, such as a secure digital card, compact flash card, universal serial bus flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In some embodiments, the memory controller is designed for operation in a high duty cycle environment solid state disk or embedded multimedia card that is used as a data storage and enterprise storage array for mobile devices such as smart phones, tablets, laptops, and the like.

The memory controller may be configured to control operations of the memory 300, such as read, erase, and program operations. The memory controller may also be configured to manage various functions with respect to data stored or to be stored in the memory 300, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the memory controller is further configured to process error correction codes for data read from the memory 300 or written to the memory 300.

The memory controller may also perform any other suitable function, such as formatting the memory. The memory controller may communicate with an external device (e.g., a host) according to a particular communication protocol. For example, the memory controller may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The memory controller and the one or more memories may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package).

In some embodiments, the memory system further comprises:

a host coupled to the memory controller configured to send or receive data.

The host may be a processor (e.g., a central processing unit or a system on a chip (e.g., an application processor)) of the electronic device.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A memory, wherein the memory has a first region and a second region, the memory comprising a first semiconductor structure and a second semiconductor structure bonded; the first semiconductor structure includes:

2. The memory of claim 1, wherein the first semiconductor structure further comprises:

a first contact plug between the first electrode structure and the second semiconductor structure; one end of the first contact plug is electrically connected with the first electrode structure, and the other end of the first contact plug is electrically connected with the second semiconductor structure;

a second contact plug between the second electrode structure and the second semiconductor structure; one end of the second contact plug is electrically connected with the second electrode structure, and the other end of the second contact plug is grounded.

3. The memory of claim 1, wherein the memory cell array comprises: a transistor;

the first semiconductor structure further includes: and the dummy transistor and the transistor are arranged in parallel along the second direction and are positioned in the second area.

4. The memory of claim 3, wherein the first semiconductor structure further comprises:

the source or the drain of the dummy transistor is electrically connected with the second electrode structure, and the drain or the source of the dummy transistor is grounded.

5. The memory of claim 1, wherein the dielectric structure comprises:

a first sub-dielectric structure located between the first electrode structure and the second electrode structure;

at least two second sub-dielectric structures; wherein a first one of the second sub-dielectric structures is located between the first electrode structure and the first sub-dielectric structure, and a second one of the second sub-dielectric structures is located between the second electrode structure and the first sub-dielectric structure; the dielectric constant of the second sub-dielectric structure is greater than the dielectric constant of the first sub-dielectric structure.

6. The memory of claim 5, wherein the second sub-dielectric structure has a dielectric constant greater than 3.9.

7. The memory of claim 1, wherein the first semiconductor structure further comprises: and the isolation structures are positioned in the second area, and positioned between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array.

8. The memory of claim 7, wherein the isolation structure is disposed around the first electrode structure, the second electrode structure, and the dielectric structure.

9. The memory of claim 1, wherein the first semiconductor structure further comprises:

a bit line located in the first region and between the memory cell array and the second semiconductor structure; wherein the memory cell array and the second semiconductor structure are electrically connected through the bit lines; the material of the bit line, the material of the first electrode structure and the material of the second electrode structure are the same.

10. The memory of claim 1, wherein the second semiconductor structure comprises peripheral circuitry.

11. The memory of claim 1, wherein the memory comprises a dynamic random access memory.

12. A manufacturing method of a memory, wherein the memory has a first region and a second region and comprises a first semiconductor structure and a second semiconductor structure, the manufacturing method comprises the following steps:

forming the first semiconductor structure, including:

forming a memory cell array;

13. The method of claim 12, wherein the forming the first semiconductor structure further comprises:

forming a first contact plug; wherein one end of the first contact plug is electrically connected with the first electrode structure;

forming a second contact plug; wherein one end of the second contact plug is electrically connected with the second electrode structure;

the bonding the first semiconductor structure and the second semiconductor structure comprises:

bonding the first contact plug, the second contact plug and the second semiconductor structure; the first contact plug is positioned between the first electrode structure and the second semiconductor structure, and the other end of the first contact plug is electrically connected with the second semiconductor structure; the second contact plug is positioned between the second electrode structure and the second semiconductor structure, and the other end of the second contact plug is grounded.

14. The method of claim 12, wherein the forming the memory cell array comprises: forming a transistor;

the forming the first semiconductor structure further comprises:

forming a dummy transistor; wherein the dummy transistor and the transistor are juxtaposed along the second direction; the source electrode or the drain electrode of the dummy transistor is electrically connected with the second electrode structure, and the drain electrode or the source electrode of the dummy transistor is grounded;

forming a first contact plug after forming the dummy transistor; wherein one end of the first contact plug is electrically connected to the first electrode structure;

the bonding the first semiconductor structure and the second semiconductor structure comprises: bonding the first contact plug and the second semiconductor structure; the first contact plug is positioned between the first electrode structure and the second semiconductor structure, and the other end of the first contact plug is electrically connected with the second semiconductor structure; the dummy transistor is located in the second region.

15. The method of claim 14, wherein the dielectric structure comprises: a first sub-dielectric structure and at least two second sub-dielectric structures; wherein the dielectric constant of the second sub-dielectric structure is greater than the dielectric constant of the first sub-dielectric structure;

the forming a dielectric structure includes:

forming a first sub-dielectric material layer covering the dummy transistor;

forming first and second grooves through the first sub-dielectric material layer and alternating in the first direction; wherein the remaining first sub-dielectric material layer is the first sub-dielectric structure;

forming a first one of the second sub-dielectric structures covering the sidewall of the first groove and forming a first sub-groove based on the topography of the first groove;

the forming a first electrode structure includes:

forming the first protrusion portion in the first sub-groove;

the forming a second electrode structure includes:

the second protrusion portion is formed in the second sub-groove.

16. The method of claim 15, wherein the forming the first semiconductor structure further comprises:

forming the first sub-dielectric material layer covering the transistor while forming the first sub-dielectric material layer covering the dummy transistor;

forming a bit line in the bit line groove while forming the first protrusion in the first sub-groove; alternatively, a bit line is formed in the bit line recess while the second protrusion portion is formed in the second sub-recess.

17. The method of claim 12, wherein the forming the first semiconductor structure further comprises:

forming an isolation structure; wherein the isolation structure is located in the second region and located between the first electrode structure and the memory cell array and between the second electrode structure and the memory cell array.

18. A memory system, comprising:

the memory of any one of claims 1 to 11, configured to store data;

a memory controller, coupled to the memory, configured to control the memory.

19. The memory system according to claim 18, wherein the memory system further comprises:

a host coupled to the memory controller configured to send or receive the data.