CN113793852A - Self-aligned pattern process method and metal interconnection structure - Google Patents

Self-aligned pattern process method and metal interconnection structure Download PDF

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CN113793852A
CN113793852A CN202111080122.2A CN202111080122A CN113793852A CN 113793852 A CN113793852 A CN 113793852A CN 202111080122 A CN202111080122 A CN 202111080122A CN 113793852 A CN113793852 A CN 113793852A
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dielectric layer
layer
mandrel
forming
memory
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颜丙杰
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

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Abstract

The application provides a self-aligned graph process method, a metal interconnection structure, a peripheral circuit, an electronic device, a memory and a storage system, wherein the self-aligned graph process method comprises the following steps: forming a plurality of mandrels arranged at intervals on a substrate, and forming side walls on two sides of the mandrels; forming a dielectric layer covering the mandrel and the side wall, wherein the dielectric layer has a low dielectric constant; removing part of the dielectric layer to expose the top surface of the side wall; and removing the side wall to form a groove. According to the self-aligned graph process method, the groove for containing the metal layer is formed by removing the side wall serving as the sacrificial layer, and the interlayer dielectric layer of the metal interconnection structure is formed by adopting the low-dielectric-constant dielectric material, so that the etching times can be reduced, the process steps are simplified, the resistance-capacitance delay effect of the metal interconnection structure is reduced, the manufacturing cost is reduced, and the yield of the finally formed semiconductor device product is improved.

Description

Self-aligned pattern process method and metal interconnection structure
Technical Field
The present invention relates to the field of semiconductor design and manufacturing, and more particularly, to a self-aligned pattern process method, a metal interconnection structure, a peripheral circuit, a memory system, and an electronic device.
Background
With the development of semiconductor technology, the integration degree of very large scale integrated circuit chips has reached the scale of several hundreds of millions or even billions of devices, and thus multilayer metal interconnection technology for realizing electrical connection of semiconductor devices is widely used.
Conventional methods for fabricating metal interconnect structures may, for example, include: forming an Inter-layer dielectric (ILD) layer by a deposition process; forming a patterned groove (Trench) or a through hole (Via) in the interlayer dielectric layer through photoetching, etching process and the like; and depositing metal by Electrochemical Plating (ECP), embedding the metal as a metal layer in the interlayer dielectric layer to form a substrate of the metal interconnection structure, and then covering the electromigration barrier layer or the diffusion barrier layer on the surface of the substrate by a deposition process to form the metal interconnection structure.
However, as semiconductor devices in integrated circuits become more dense, metal interconnection structures for electrically connecting the semiconductor devices are increasing, feature Sizes (CDs) of the metal interconnection structures become smaller, and distances between adjacent metal layers in the metal interconnection structures become smaller, so that resistance and capacitance of the metal interconnection structures generate more and more significant delay effects, which affects operation speeds of the semiconductor devices and reduces reliability of the semiconductor devices.
Therefore, how to effectively reduce the parasitic capacitance of the metal interconnection structure to improve the operation speed and the use reliability of the semiconductor devices such as the three-dimensional memory is an urgent problem to be solved.
Disclosure of Invention
The present application provides a self-aligned pattern processing method, a metal interconnection structure, a peripheral circuit, a memory system, and an electronic device that can at least partially solve the above-mentioned problems in the related art.
One aspect of the present application provides a self-aligned pattern processing method, including: forming a plurality of mandrels arranged at intervals on a substrate, and forming side walls on two sides of the mandrels; forming a dielectric layer covering the mandrel and the side walls, wherein the dielectric layer has a low dielectric constant; removing part of the dielectric layer to expose the top surface of the side wall; and removing the side wall to form a groove.
In one embodiment of the present application, the dielectric constant K of the dielectric layer satisfies: k is more than or equal to 2 and less than or equal to 3.
In one embodiment of the present application, the dielectric layer includes: at least one of a black diamond layer and a nitrogen doped silicon carbide layer.
In one embodiment of the present application, forming a dielectric layer covering the mandrel and the sidewall comprises: and forming a dielectric layer covering the mandrel and the side wall by using a low dielectric material.
In one embodiment of the present application, forming a dielectric layer covering the mandrel and the sidewall comprises: and forming an air gap in the dielectric layer.
In one embodiment of the present application, forming a dielectric layer covering the mandrel and the sidewall comprises: and forming the dielectric layer by adopting a deposition process, wherein the deposition process adopts two deposition rates with different sizes so as to form the air gap in the dielectric layer.
In one embodiment of the present application, the deposition process simultaneously uses two deposition rates of different magnitudes to form the air gap in the dielectric layer.
In one embodiment of the present application, the depositing process using two different deposition rates to form the air gap in the dielectric layer includes: forming a first dielectric layer on the surface of the mandrel and the surface of the side wall at a first deposition rate; and forming a second dielectric layer on the surface of the first dielectric layer by adopting a second deposition rate, wherein the second deposition rate is greater than the first deposition rate.
In one embodiment of the present application, the ratio α between the second deposition rate and the first deposition rate is in the range of 1.5 ≦ α ≦ 2.
In one embodiment of the present application, removing a portion of the dielectric layer to expose the top surfaces of the sidewalls includes: and removing part of the dielectric layer by adopting a chemical mechanical polishing process, wherein the polishing operation for removing part of the dielectric layer is stopped at the surface of the mandrel far away from the substrate.
In one embodiment of the present application, forming the side walls on both sides of the mandrel includes: forming a cover layer covering the mandrel; and removing the parts, located on the top surface of the mandrel and between the side walls of the mandrels, of the covering layer to form the side walls.
In one embodiment of the present application, forming a cover layer covering the mandrel comprises: and forming a covering layer covering the mandrel by adopting an atomic layer deposition process.
In an embodiment of the present application, the sidewall has an etching selectivity greater than a set value with respect to the mandrel, so as to retain the mandrel when the sidewall is removed.
In an embodiment of the present application, in a direction parallel to the arrangement of the mandrels, the width of the side wall is less than or equal to the width of the mandrel.
In an embodiment of the application, after removing the sidewall spacers to form the trench, the method further includes: and filling the groove with a metal layer to form a metal interconnection structure.
Another aspect of the present application provides a metal interconnection structure, including: a substrate; and an interconnect layer disposed on the substrate and including: the metal core comprises a metal layer, a core shaft dielectric layer and an interlayer dielectric layer, wherein a groove is formed between the core shaft dielectric layer and the interlayer dielectric layer; the metal layer is arranged in the groove; and the interlayer dielectric layer is a low dielectric constant dielectric layer.
In one embodiment of the present application, the metal interconnect structure comprises a plurality of the metal layers; the interlayer dielectric layer comprises a first interlayer dielectric layer positioned between the adjacent metal layers; and at least one air gap formed in the first interlayer dielectric layer.
In one embodiment of the present application, the air gap is located in a middle or middle-lower portion of the first interlayer dielectric layer and extends in a direction perpendicular to the substrate.
In one embodiment of the present application, the first interlayer dielectric layer includes a first dielectric layer and a second dielectric layer sequentially arranged in a direction perpendicular to the substrate.
In one embodiment of the present application, the air gap includes a first portion in the first dielectric layer and a second portion in the second dielectric layer, and the first portion is larger than the second portion.
In one embodiment of the present application, the dielectric constant K of the interlayer dielectric layer satisfies: k is more than or equal to 2 and less than or equal to 3.
Yet another aspect of the present application provides a peripheral circuit for connection with a memory circuit, the peripheral circuit comprising: a plurality of semiconductor devices arranged in an array; and the metal interconnection structure provided by the other aspect of the application is used for connecting the semiconductor device and the memory circuit.
Yet another aspect of the present application provides a memory, comprising: a storage array; and peripheral circuitry coupled to the memory array, wherein the peripheral circuitry includes a metal interconnect structure provided in another aspect of the present application.
In one embodiment of the present application, the memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.
Yet another aspect of the present application provides a storage system, including: a controller and a memory provided by yet another aspect of the present application, the controller coupled to the memory and configured to control the memory to store data.
In yet another aspect, an electronic device is provided that includes a memory as provided in yet another aspect of the present application.
In one embodiment of the present application, the electronic device includes at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.
According to the self-aligned pattern process method and the metal interconnection structure provided by at least one embodiment of the application, the side wall serving as the sacrificial layer is removed to form the groove for accommodating the metal layer, and the low-dielectric-constant dielectric material is adopted to form the interlayer dielectric layer of the metal interconnection structure, so that the etching times can be reduced, the process steps can be simplified, the resistance-capacitance delay effect of the metal interconnection structure and the manufacturing cost thereof can be reduced, and the yield of the finally formed semiconductor device product can be improved.
According to the self-aligned pattern process method and the metal interconnection structure of at least one embodiment of the application, the RC delay effect of the metal interconnection structure can be further reduced by forming the air gap in the interlayer dielectric layer of the metal interconnection structure.
In addition, according to the self-aligned pattern process method and the metal interconnection structure, the peripheral circuit, the electronic device, the memory and the system in accordance with at least one embodiment of the present application, the width of the sidewall may be smaller than or equal to the width of the mandrel in the direction parallel to the mandrel arrangement, so that the requirement of reducing the minimum feature size (CD) of the semiconductor device product to realize a higher density semiconductor integrated circuit can be satisfied without increasing additional production cost and process steps.
In addition, in at least one embodiment of the present application, a Chemical Mechanical Polishing (CMP) process is used to replace a conventional etching process in the step of removing a portion of the dielectric layer to expose the top surface of the sidewall, so that the roughness of the surfaces of the remaining dielectric layer, the sidewall and the mandrel can meet the requirements of subsequent process steps, and the conductivity and yield of the finally formed semiconductor device product can be improved.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:
FIG. 1 is a flow chart of a self-aligned patterning process according to one embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of a structure formed after forming a mandrel layer on a substrate according to one embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a structure formed after forming an etch mask layer on a mandrel layer according to one embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of a structure formed after patterning an etch mask layer according to one embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a structure formed after forming a plurality of mandrels spaced apart on a substrate according to one embodiment of the present application;
FIG. 6 is a schematic cross-sectional view of a structure formed after forming a preliminary layer overlying a mandrel according to one embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a structure formed after forming sidewalls on both sides of a mandrel according to one embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a structure formed after forming a dielectric layer covering a mandrel and sidewalls according to one embodiment of the present application;
FIG. 9 is a schematic cross-sectional view of a structure formed after another dielectric layer is formed on a surface of the dielectric layer according to one embodiment of the present application;
FIG. 10 is a schematic cross-sectional view of a structure formed after removing a portion of a dielectric layer to form a remaining dielectric layer according to one embodiment of the present application;
FIG. 11 is a schematic cross-sectional view of a structure formed after removing sidewalls to form trenches, according to an embodiment of the present invention;
FIG. 12 is a cross-sectional view of a structure formed after a metal layer is formed in a trench according to a self-aligned patterning process in accordance with one embodiment of the present application;
FIG. 13 is a schematic cross-sectional view of a metal interconnect structure formed after removing a portion of a metal layer according to a self-aligned patterning process in accordance with one embodiment of the present application;
FIGS. 14A to 14F are schematic views illustrating a conventional self-aligned patterning process;
FIG. 15 is a schematic cross-sectional diagram of a peripheral circuit configuration according to one embodiment of the present application;
FIG. 16 is a schematic cross-sectional view of a memory structure according to an embodiment of the present application;
FIG. 17 is a schematic diagram of a storage system architecture according to an embodiment of the present application; and
FIG. 18 is a schematic diagram of an electronic device configuration according to one embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first side discussed in this application may also be referred to as a second side and a first trench may also be referred to as a second trench, and vice versa, without departing from the teachings of this application.
In the drawings, the width, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
Further, in this document, when it is described that one portion is "on" another portion, the meanings of "on … …", "above … …" and "above … …", for example, should be interpreted in the broadest way such that "on … …" not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "on … …" or "above … …" does not absolutely mean above with reference to the direction of gravity, nor only means "above something" or "above something", but may also include the meaning of "above something" or "above something" with no intermediate features or layers therebetween (i.e., directly on something).
It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.
As semiconductor devices in integrated circuits become more dense, metal interconnection structures for electrically connecting the semiconductor devices are increasing, and the distance between adjacent metal layers in the metal interconnection structures is required to be smaller. The inventors have found that making the distance between the metal layers small can cause significant delay effects in the resistance and capacitance of the metal interconnection structure, affect the operating speed of the semiconductor device, and reduce the reliability of the semiconductor device.
The embodiment of the application provides a self-aligned graph process method, a metal interconnection structure, a peripheral circuit, a memory, a storage system and electronic equipment. The method comprises the steps of forming a plurality of mandrels arranged at intervals on a substrate, forming side walls on two sides of the mandrels, forming dielectric layers covering the mandrels and the side walls, removing part of the dielectric layers to expose the top surfaces of the side walls, and removing the side walls to form grooves, wherein the dielectric layers have low dielectric constants. Therefore, the distance between adjacent metal layers in the metal interconnection structure can be reduced, and the delay effect generated by the resistance and the capacitance of the metal interconnection structure can be reduced. In some embodiments, the trenches are substantially equal in width from top to bottom, so that the metal layers filled subsequently are substantially equal in width from top to bottom, and thus occupy smaller dimensions and have relatively smaller distances between the metal layers. In some embodiments, the dielectric material of the dielectric layer is formed using a low dielectric material such that the formed dielectric layer has a low power saving constant. In some embodiments, the dielectric layer is formed with an air gap in between, thereby providing a low dielectric constant for the dielectric layer.
FIG. 1 is a flow chart of a self-aligned patterning process 1000 according to one embodiment of the present application. As shown in fig. 1, the self-aligned pattern process 1000 may include:
and S1, forming a plurality of mandrels arranged at intervals on the substrate, and forming side walls on two sides of the mandrels.
And S2, forming a dielectric layer covering the mandrel and the side walls, wherein the dielectric layer has a low dielectric constant.
And S3, removing part of the dielectric layer to expose the top surfaces of the side walls.
And S4, removing the side wall to form a groove.
The specific processes of the steps of the self-aligned patterning process 1000 will be described in detail with reference to fig. 2 to 13.
Step S1
Fig. 2 is a schematic cross-sectional view of a structure formed after forming a mandrel layer 200 on a substrate 100 according to one embodiment of the present application. Fig. 3 is a schematic cross-sectional view of a structure formed after forming an etch mask layer 300 on the mandrel layer 200 according to a self-aligned patterning process method of an embodiment of the present application. Fig. 4 is a schematic cross-sectional view of a structure formed after patterning an etch mask layer 300 according to a self-aligned patterning process method of an embodiment of the present application. Fig. 5 is a cross-sectional view of a structure formed after forming a plurality of mandrels 210 arranged at intervals on a substrate 100 according to a self-aligned patterning process method of an embodiment of the present application. Fig. 6 is a schematic cross-sectional view of a structure formed after forming a preparation layer 220 covering a mandrel 210 according to a self-aligned patterning process method of an embodiment of the present application. Fig. 7 is a schematic cross-sectional view of a structure formed after forming sidewalls 230 on both sides of the mandrel 210 according to an embodiment of the self-aligned patterning process.
As shown in fig. 2 to 7, the step S1 of forming a plurality of mandrels arranged at intervals on the substrate and forming sidewalls on two sides of the mandrels may include: forming a mandrel layer 200 on a substrate 100; forming an etching mask layer 300 on the mandrel layer 200; patterning the etching mask layer 300; forming a plurality of mandrels 210 arranged at intervals; and forming a preparation layer 220 covering the mandrel 210, and forming side walls 230 on both sides of the mandrel 210.
Specifically, in one embodiment of the present application, a stacked structure may be formed first, and as an option, the stacked structure may be, in order from bottom to top: the semiconductor device includes a substrate 100, a mandrel layer 200, an etching mask layer 300, and a photoresist layer (not shown), wherein the mandrel layer 200 may be a spin-on carbon-containing material (SoC) layer, a silicon oxide layer, or the like, the etching mask layer 300 may be a hard mask layer, and further, the etching mask layer 300 may be selected from at least one of a polysilicon layer, a silicon oxynitride layer, and a silicon nitride layer. The above-described stack structure may further include other layers, and in addition, the substrate, the mandrel layer, the etching mask layer, and the photoresist layer may also be composite layers, and fig. 2 to 7 provided herein simplify the above-described stack structure, and it will be understood by those skilled in the art that the composition and structure of the stack structure may be changed to obtain various results and advantages described in the present specification without departing from the technical solution claimed herein.
As shown in fig. 2 and 3, the above-described stacked structure including the substrate 100, the mandrel layer 200, the etch mask layer 300, and the photoresist layer in this order may be formed by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.
As shown in fig. 4 and 5, after the stacked structure is formed, the etch mask layer 300 may be etched using a patterned photoresist layer (not shown) as a mask to form a patterned etch mask layer 310 including a plurality of mandrel patterns; the mandrel layer 200 is then etched using the patterned etch mask layer 310 as a mask to form a plurality of mandrels 210 arranged at intervals.
As shown in fig. 6, in one embodiment of the present application, a plurality of mandrels 210 are arranged on one surface of the substrate 100 at a distance from each other. The arrangement direction of the plurality of mandrels 210 may be set to the X direction. After forming the plurality of mandrels 210, a preparation layer 220 covering the mandrels 210 may be formed by, for example, a deposition process, wherein the preparation layer 220 may include a preparation layer upper layer 220A formed on a top surface of the mandrels 210 (a surface of the mandrels 210 away from the substrate 100); a preparatory-layer-side layer 220B formed on both side wall surfaces of the mandrel 210 (the surface of the mandrel 210 perpendicular to the X direction); and a preparation layer bottom layer 220C covering the substrate 100 and located between sidewalls of the plurality of mandrels 210.
In one embodiment of the present application, the preparation layer 220 may be formed by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. Alternatively, the preparation layer 220 may be formed by an atomic layer deposition process, and the preparation layer 220 formed by the atomic layer deposition process may have better uniformity, so as to improve the performance of the finally formed semiconductor device.
In addition, as shown in fig. 6 and 7, the preparation layer upper layer 220A and the preparation layer lower layer 220C of the preparation layer 220 may be removed, and the preparation layer side layer 220B may be remained to form the side walls 230 on both sides of the mandrel 210. Portions of the preliminary layer 220 in the X direction may be removed to form the sidewalls 230, such as by a dry etch process or a combination of dry and wet etch processes. Specifically, as an option, a wet etching process, a reactive ion etching process, or an atomic layer etching process may be used to remove a portion of the preparation layer 220 in the X direction to form the sidewall spacers 230.
Alternatively, in one embodiment of the present application, the sidewall spacers 230 may include at least one of a silicon nitride layer, a titanium nitride layer, and a titanium oxide layer.
Alternatively, in an embodiment of the present application, the sidewall spacers 230 may have an etching selectivity greater than a set value with respect to the mandrel 210, so as to retain the mandrel 210 in a subsequent step of removing the sidewall spacers 230.
As shown in fig. 14A to 14F, taking the self-aligned dual patterning process in the conventional self-aligned patterning process as an example, the method may generally include the following steps: sequentially depositing and forming a first hard mask layer 2, a core material layer 3, a second hard mask layer 4 and a photoetching layer 5 on the surface of the layer 1 to be etched, and then photoetching to form a patterned photoetching layer 5; etching the second hard mask layer 4 using the patterned photoresist layer 5 as a mask to form a patterned second hard mask layer (not shown); etching the core material layer 3 by using the patterned second hard mask layer as a mask to form a plurality of mandrels 3' arranged at intervals; then removing the patterned second hard mask layer, and forming a side wall material layer 6 covering the mandrel 3' by a deposition process; removing parts, such as the horizontal direction (X direction), of the side wall material layer 6 by an etching process to form side walls 6'; removing the mandrel 3 ' by an etching process, and etching the first hard mask layer 2 by taking the side wall 6 ' as a mask to form a patterned first hard mask layer 2 '; etching the layer to be etched 1 with the patterned first hard mask layer 2' as a mask to form a trench 7; and filling the trench 7 with a metal layer.
After the conductor manufacturing technology enters a technology node of 24nm and below, the conventional self-aligned graph processing method can replace a photoetching process to define the graph dimension for preparing semiconductor devices such as metal interconnection structures and the like. However, as semiconductor devices in integrated circuits become more dense, metal interconnection structures for electrically connecting the semiconductor devices are increasing, feature Sizes (CDs) of the metal interconnection structures become smaller, and distances between adjacent metal layers in the metal interconnection structures become smaller, so that resistance and capacitance of the metal interconnection structures generate more and more significant delay effects, which affects operation speeds of the semiconductor devices and reduces reliability of the semiconductor devices.
Compared with the conventional method for etching a layer to be etched, such as a substrate, by using the remaining side wall as a mask to form a groove for accommodating the metal layer after the mandrel is etched, the self-aligned pattern process method for forming the metal interconnection structure, provided by at least one embodiment of the application, can form the groove for accommodating the metal layer by removing the side wall serving as the sacrificial layer, so that the formed metal layer is basically equal in width from top to bottom, the wiring density of the metal layer is improved, and the whole size of a device is reduced; and the interlayer dielectric layer of the metal interconnection structure is formed by adopting a low-dielectric-constant dielectric material, so that the etching times are reduced, the process steps are simplified, the resistance-capacitance delay effect and the manufacturing cost of the metal interconnection structure are reduced, and the yield of the finally formed semiconductor device product is improved.
In addition, according to the self-aligned pattern process method of at least one embodiment of the present application, the rc delay effect of the metal interconnect structure can be further reduced by forming an air gap in the interlayer dielectric layer of the metal interconnect structure.
As shown in fig. 7, in some embodiments, the width W1 of the sidewall 230 in the X direction may be greater than or equal to the width W2 of the mandrel 210 in the X direction. In addition, in some other embodiments, the width W1 of the sidewall 230 in the X direction may be less than or equal to the width W2 of the mandrel 210 in the X direction.
Specifically, in an embodiment of the present application, the width W1 of the sidewall 230 may satisfy 20nm ≦ W1 ≦ 30 nm. Further, in an embodiment of the present application, the width W2 of the mandrel 210 may satisfy 30nm ≦ W2 ≦ 50 nm.
Therefore, according to the self-aligned pattern processing method of at least one embodiment of the present application, since the width of the sidewall may be less than or equal to the width of the mandrel in the direction parallel to the mandrel arrangement, in the process of forming the trench for accommodating the metal layer by removing the sidewall serving as the sacrificial layer, the requirement of reducing the minimum feature size (CD) of the semiconductor device product to realize a higher density semiconductor integrated circuit can be satisfied without increasing additional production cost and process steps.
The process of forming the metal-accommodating trench by removing the sidewall as the sacrificial layer and forming the metal interconnection structure will be described in detail in steps S2 to S5 with reference to fig. 8 to 13 in particular.
Step S2
Fig. 8 is a cross-sectional view of a structure formed after forming a dielectric layer 401 of a first material covering the mandrel 210 and the sidewall spacers 230 according to an embodiment of the present disclosure. Fig. 9 is a cross-sectional view of a structure formed after another dielectric layer 402 of a second material is formed on the surface of the dielectric layer 401 of a first material according to a self-aligned patterning process of an embodiment of the present application.
As shown in fig. 8 and 9, in an embodiment of the present application, the step S2 is to form a dielectric layer covering the mandrel and the sidewall spacers, where the dielectric layer having a low dielectric constant may include: the dielectric layer 400 covering the mandrel 210 and the sidewall spacers 230 is formed by one or more thin film deposition processes, wherein the dielectric layer 400 may be made of at least one low-k dielectric material, and the thin film deposition processes may include, but are not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, which is not limited in this respect. The dielectric layer may be a low dielectric constant dielectric layer. It is understood that a low dielectric constant (low-k), i.e., a dielectric constant (k) that is relatively low (lower than silicon dioxide, k 3.9), may be a dielectric having a relatively low dielectric constant (k) that is lower than silicon dioxide, k 3.9.
In another embodiment of the present application, the step S2 is to form a dielectric layer covering the mandrel and the sidewall spacers, where the dielectric layer having a low dielectric constant may further include: doping a relatively more electronegative or less polarizable element (e.g., fluorine, etc.) or group (e.g., CH) into an initial dielectric layer having a first dielectric constantx、CHF3Etc.) to reduce the dipole polarization of the initial dielectric layer, such as by introducing Si-F bonds, thereby forming a dielectric layer having a second dielectric constant, wherein the second dielectric constant is a low dielectric constant and is less than the first dielectric constant.
In addition, in another embodiment of the present application, the step S2 forms a dielectric layer covering the mandrel and the sidewall spacers, where the dielectric layer having a low dielectric constant may further include: in the process of forming the dielectric layer by using the dielectric material with the third dielectric constant, the dielectric layer with the air gap is formed by controlling the process parameters such as the deposition process, and the dielectric constant of the dielectric layer can be reduced because the dielectric constant of the air gap is 1, so that the dielectric layer has a fourth dielectric constant which is low in dielectric constant and is smaller than the third dielectric constant.
Further, a dielectric layer having a low dielectric constant may be formed in combination with the above method. For example, a dielectric material with a low dielectric constant is selected to form a dielectric layer, and the dielectric layer with an air gap is formed by controlling the forming process parameters in the forming process. The dielectric layer with low dielectric constant can be obtained by preparing the dielectric layer by using the dielectric material with low dielectric constant and introducing air gaps in the structure of the dielectric layer. In addition, the structure, material and forming process of the dielectric layer with low dielectric constant are not limited in the application.
In the context of semiconductor processing, low dielectric constant (low-K) generally refers to a dielectric constant (K) that is lower than that of silicon oxide, wherein the dielectric constant of silicon oxide is between 3.9 and 4.1. A typical low dielectric constant may be less than 3.5.
In one embodiment of the present application, the dielectric constant K of the dielectric layer 400 covering the mandrel 210 and the sidewall spacers 230 may satisfy: k is more than or equal to 2 and less than or equal to 3.
As the feature size (CD) of a semiconductor device is smaller, the distance between adjacent metal layers is smaller, which results in larger capacitance generated between adjacent metal layers, and the capacitance also becomes a parasitic capacitance, which not only affects the operation speed of the semiconductor device, but also has a serious effect on the reliability of the semiconductor device. In order to alleviate such problems, for example, when an interlayer dielectric layer of a metal interconnection structure is formed, a low-k dielectric material may be used to replace a high-k dielectric material such as silicon oxide, so as to reduce the capacitance between adjacent metal layers in the interlayer dielectric layer, thereby solving parasitic capacitance, rc delay effects, and a series of problems caused thereby.
Further, according to the self-aligned pattern process method of at least one embodiment of the present application, an air gap may be further formed in the interlayer dielectric layer of the metal interconnection structure to reduce the rc delay effect of the metal interconnection structure.
Specifically, in one embodiment of the present application, the dielectric layer 400 may be formed using any one or a combination of a layer such as an NDC (Nitrogen doped Silicon carbide) layer, a TEOS (ethyl orthosilicate) layer, and a BD (Black Diamond) layer, wherein the BD layer may be made of a low dielectric constant material organosilicate glass (SiOC) based on Silicon dioxide, for example, the BD layer may be formed by doping Silicon dioxide with low polarity molecules such as methyl and oxygen, and using Plasma Enhanced Chemical Vapor Deposition (PECVD).
In addition, the dielectric layer 400 may be selected to have a single layer structure or a composite layer structure. Specifically, as shown in fig. 9, as an alternative, a first material dielectric layer 401 covering the mandrel 210 and the sidewall spacers 230 may be formed first, then a second material dielectric layer 402 is formed on the surface of the first material dielectric layer 401, and a third material dielectric layer 403 is formed on the surface of the second material dielectric layer 402 to form a dielectric layer 400 with a composite structure. However, it will be appreciated by those skilled in the art that the composition, structure, and process of formation of the dielectric layer can be varied to achieve the various results and advantages described herein without departing from the claimed subject matter.
Referring again to fig. 9, in one embodiment of the present application, an air gap may be formed in the dielectric layer 400 to reduce the rc delay effect of the metal interconnect structure. Specifically, as an option, the deposition process used to form the second material dielectric layer 402 may include two deposition rates with different magnitudes to form the air gap 01 in the second material dielectric layer 402, wherein the second material dielectric layer 402 may include a first dielectric layer 402A and a second dielectric layer 402B formed by the two deposition rates with different magnitudes.
Alternatively, a first dielectric layer 402A may be formed on the surface of the mandrel 210 and the surface of the sidewall spacer 230 at the same time by using a first deposition rate, or a first dielectric layer 402A may be formed on the surface of the first material dielectric layer 401 at the first deposition rate; and forming a second dielectric layer 402B on the surface of the first dielectric layer 402A using a second deposition rate. Further, when the first dielectric layer 402A and the second dielectric layer 402B are deposited simultaneously, the second deposition rate may be greater than the first deposition rate, so that the surface of the second dielectric layer 402B located above and formed first at the faster second deposition rate may seal a portion of the space, thereby affecting the first dielectric layer 402A located below and formed at the slower first deposition rate, and allowing the second dielectric layer 402 to have an air gap 01 therein.
In one embodiment of the present application, the ratio α between the second deposition rate and the first deposition rate may range from 1 ≦ α ≦ 3. Further, the ratio α can alternatively range from 1.5 ≦ α ≦ 2. When the first dielectric layer 402A and the second dielectric layer 402B are deposited simultaneously, and the ratio of the second deposition rate to the first deposition rate is in the above range, the surface of the upper second material dielectric layer 402B formed first at the faster second deposition rate may seal a portion of the space, thereby affecting the lower first second material dielectric layer 402A formed at the slower first deposition rate, and allowing the second material dielectric layer 402 to have an air gap 01. Since air has a lower dielectric constant, the dielectric constant of the dielectric layer (e.g., the dielectric layer 401 made of the first material) can be reduced by adding the air gap in the dielectric layer, and the RC delay phenomenon can be improved.
Further, the size and position of the air gap in the dielectric layer can be controlled by controlling the first deposition rate and the second deposition rate. For example, in one embodiment of the present application, the air gap 01 may include a first portion in the first dielectric layer 402A and a second portion in the second dielectric layer 402B, with the first portion being larger than the second portion. The larger the ratio alpha between the second deposition rate and the first deposition rate is, the larger the formed air gap is, and the more obvious the effect of improving the resistance capacitance delay phenomenon of the metal interconnection structure formed subsequently is. Furthermore, those skilled in the art will appreciate that the structure, composition, and formation process of the dielectric layer formed with air gaps can be varied without departing from the claimed subject matter to obtain the results and advantages described herein.
Step S3
Figure 10 is a cross-sectional schematic view of a structure formed after removing a portion of dielectric layer 400 to form a remaining dielectric layer 410, in accordance with one embodiment of the present application.
As shown in fig. 10, the step S3 of removing a portion of the dielectric layer to expose the top surfaces of the sidewalls may include, for example: removing a portion of dielectric layer 400 to form a remaining dielectric layer 410 may be stopped at the top surface 211 of mandrel 210 remote from substrate 100 and exposing the top surfaces 231 of sidewalls 230, using a process such as a dry etching process or a combination of dry and wet etching processes, or performing other fabrication processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing. The remaining dielectric layers 410 include a first dielectric layer 402A 'of a second material, a second dielectric layer 402B' of a second material, and at least one air gap 01.
In one embodiment of the present application, a portion of the dielectric layer 400 may be removed by a Chemical Mechanical Polishing (CMP) process to form the remaining dielectric layer 410, and the polishing to remove the portion of the dielectric layer 400 may stop at the top surface 211 of the mandrel 210 and expose the top surfaces 231 of the sidewalls 230. In other words, the top surface 211 of the mandrel 210 away from the substrate 100 may serve as a stop layer to limit the above polishing process, and ensure uniformity of the surface of the remaining dielectric layer 410 and the surface of the exposed sidewall spacers 230.
In addition, the chemical mechanical polishing process may at least include a main polishing step in which a chemical preparation with polishing particles is used as a polishing liquid to polish the dielectric layer 400, and a deionized water cleaning step; the downforce used in the deionized water cleaning process is in the same direction as the downforce used in the main grinding process, so that the roughness of the surfaces of the residual dielectric layer 410, the side wall 230 and the mandrel 210 meets the requirements. Further, the polishing parameters of the chemical mechanical polishing process may include a down force, a polishing time and a polishing rotation speed, and by adjusting the polishing parameters, the roughness of the surfaces of the remaining dielectric layer 410, the sidewall 230 and the mandrel 210 may be dynamically adjusted or trimmed to meet the requirements of the subsequent process steps.
Therefore, in at least one embodiment of the present application, a Chemical Mechanical Polishing (CMP) process is used to replace a conventional etching process in the step of removing a portion of the dielectric layer to expose the top surface of the sidewall, so that the roughness of the surfaces of the remaining dielectric layer, the sidewall and the mandrel can meet the requirements of the subsequent process steps, and the conductivity and yield of the finally formed semiconductor device product can be improved.
Step S4
Fig. 11 is a cross-sectional view of a structure formed after removing the sidewall spacers 230 to form the trench 240 according to an embodiment of the present invention.
As shown in fig. 11, the step S4 of removing the sidewalls to form the trench may include, for example: the spacers 230 (as shown in fig. 10) are removed to form the trench 240, for example, by a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes.
In addition, in an embodiment of the present application, the sidewall spacers 230 may have an etching selectivity greater than a predetermined value with respect to the mandrel 210, so that the mandrel 210 may remain during the step of removing the sidewall spacers 230. Alternatively, other methods, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, may be used to retain the mandrel 210 during the step of removing the sidewall spacers 230. The present application is not limited to the specific embodiments.
Forming a trench in a conventional self-aligned patterning process usually requires removing a mandrel by, for example, an etching process, and etching a hard mask layer using a sidewall as a mask to form a patterned hard mask layer; and etching the layer to be etched by using the patterned hard mask layer as a mask to form a groove for accommodating the metal layer. According to the self-aligned graph process method, the groove for containing the metal layer is formed by removing the side wall serving as the sacrificial layer, and the interlayer dielectric layer of the metal interconnection structure is formed by adopting the low-dielectric-constant dielectric material, so that the etching times can be reduced, the process steps are simplified, the resistance-capacitance delay effect and the manufacturing cost of the metal interconnection structure are reduced, and the yield of the finally formed semiconductor device product is improved.
Further, in some embodiments, the width W1 of the sidewall 230 in the X direction is less than or equal to the width W2 of the mandrel 210 in the X direction. Therefore, according to the self-aligned pattern processing method of at least one embodiment of the present application, since the width of the sidewall may be less than or equal to the width of the mandrel in the direction parallel to the arrangement of the mandrels, in the process of forming the trench for accommodating the metal layer by removing the sidewall serving as the sacrificial layer, the requirement of reducing the minimum feature size of the product device to realize a higher density semiconductor integrated circuit can be satisfied without increasing additional production cost and process steps.
Alternatively, in some embodiments, the mandrel 210 may be further removed to enlarge the dimension of the trench 240 in the X direction according to the design requirements of the finally formed semiconductor device.
Fig. 12 is a cross-sectional view of a structure formed after forming a metal fill layer 500 in a trench 240 according to a self-aligned patterning process in accordance with one embodiment of the present application. Fig. 13 is a schematic cross-sectional view of a metal interconnect structure 2000 formed after removing a portion of the metal fill layer 500 according to an embodiment of the present invention;
as shown in fig. 11 and 12, the self-aligned image processing method provided by the present application further includes: the trench is filled with a metal layer to form a metal interconnect structure, and the steps may include, for example: filling the trench 240 with a metal fill layer 500, such as by a deposition process; and removing a portion of the metal fill layer 500, such as by a chemical mechanical polishing process (CMP), to make the top surface 511 of the metal layer flush with the top surface 211 of the mandrel 210 to form a metal layer 510.
Specifically, a metal fill layer 500 may be formed by one or more thin film deposition processes that covers the top surface 211 of the mandrel 210 and the top surface of the dielectric layer 400 and fills the trench 240 (shown in fig. 10). The thin film deposition process may include, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, which is not limited in this application. Alternatively, the metal fill layer 500 may be deposited using Electrochemical Plating (ECP).
After forming the metal fill layer 500, a portion of the metal fill layer 500 may be removed, such as by a Chemical Mechanical Polishing (CMP), to make the top surface 511 of the metal layer flush with the top surface 211 of the mandrel 210 to form the metal layer 510.
In one embodiment of the present application, copper may be selected as the material for forming the metal filling layer 500 because copper has better conductivity and filling property. However, it will be understood by those skilled in the art that the structure, composition and process of formation of the metal fill layer can be varied to achieve the various results and advantages described in this specification without departing from the claimed subject matter.
In addition, in one embodiment of the present application, the self-aligned image processing method provided herein further includes the step of forming the metal interconnection structure 2000: the trench 240 formed by the residual dielectric layer 410 and the mandrel 210 is filled with a metal layer 510 to form a substrate, and then the metal interconnect structure 2000 is formed on the surface of the substrate by covering the electromigration barrier layer or the diffusion barrier layer by, for example, a deposition process.
Referring again to fig. 13, the present application also provides a metal interconnect structure 2000 prepared by the above method, and specifically, the metal interconnect structure 2000 may include: the semiconductor device includes a substrate 100 and an interconnection layer disposed on the substrate 100, wherein the interconnection layer may include a residual dielectric layer 410 (interlayer dielectric layer), a mandrel 210 and a metal layer 510, a trench (not shown) is disposed between the interlayer dielectric layer 410 and the mandrel 210, the metal layer 510 is disposed in the trench, and the interlayer dielectric layer 410 is a low-dielectric-constant dielectric layer.
Further, in one embodiment of the present application, the dielectric constant K of the interlayer dielectric layer satisfies: k is more than or equal to 2 and less than or equal to 3. Alternatively, the interlayer dielectric layer may include at least one of a black diamond layer and a nitrogen-doped silicon carbide layer.
The side wall serving as the sacrificial layer is removed to form a groove for containing the metal layer, and the low-dielectric-constant dielectric material is adopted to form the interlayer dielectric layer of the metal interconnection structure, so that the etching times can be reduced, the process steps are simplified, the resistance-capacitance delay effect of the metal interconnection structure and the manufacturing cost thereof are reduced, and the yield of the finally formed semiconductor device product is improved.
Further, in one embodiment of the present application, the interlayer dielectric layer 410 includes a first interlayer dielectric layer 411 between adjacent metal layers 510; and at least one air gap 01 formed in the first interlayer dielectric layer 411. The air gap 01 may reduce the rc delay effect of the metal interconnect structure 2000.
Alternatively, in one embodiment of the present application, the air gap 01 may be located in the middle or middle-lower portion of the first interlayer dielectric layer 411 and extend in a direction perpendicular to the substrate 100.
Further, in one embodiment of the present application, the interlayer dielectric layer 410 includes a first dielectric layer 402A '(the first dielectric layer 402A remaining in the previous step) and a second dielectric layer 402B' (the second dielectric layer 402B remaining in the previous step) sequentially disposed in a direction perpendicular to the substrate 100. Alternatively, the air gap 01 may include a first portion in the first dielectric layer 402A 'and a second portion in the second dielectric layer 402B', with the first portion being larger than the second portion.
According to the metal interconnection structure of at least one embodiment of the application, the resistance-capacitance delay effect of the metal interconnection structure can be reduced by forming the interlayer dielectric layer of the metal interconnection structure by using the low-dielectric-constant dielectric material and forming the air gap in the interlayer dielectric layer.
Further, the metal interconnection structure 2000 manufactured according to at least one embodiment of the present application may have a width W3 of the metal layer 510 in a direction parallel to the alignment direction of the mandrel 210 (in the X direction) in a range of 20nm ≦ W3 ≦ 30 nm. Therefore, the requirement of reducing the minimum feature size (CD) of the semiconductor device product to realize a higher density semiconductor integrated circuit can be satisfied without increasing additional production cost and process steps.
In addition, in at least one embodiment of the present application, in the process of forming the metal interconnect structure 2000, a Chemical Mechanical Polishing (CMP) process is used to replace a conventional etching process in the step of removing a portion of the dielectric layer to expose the top surface of the sidewall, so that the roughness of the surfaces of the remaining dielectric layer, the sidewall and the mandrel can meet the requirements of the subsequent process steps, and thus the conductivity and yield of the metal interconnect structure and the finally formed semiconductor device product can be improved.
FIG. 15 is a schematic cross-sectional diagram of a peripheral circuit configuration according to one embodiment of the present application.
As shown in fig. 15, another aspect of the present application also provides a peripheral circuit 3000 including the metal interconnection structure 2000 prepared by the above method. The peripheral circuit 3000 may include: capacitive, inductive or PN structures, etc. Specifically, the peripheral circuit 3000 for connection with the memory circuit may include a plurality of semiconductor devices arranged in an array; and a metal interconnect structure 2000 for connecting the semiconductor device with the memory circuit.
In one embodiment of the present application, the semiconductor device may include a gate structure 3002 on the second substrate 3001, and source-drain doped regions 3003 respectively located in the second substrate 3001 and located at two sides of the gate structure 3002. In addition, the semiconductor device further includes a first contact plug 3004 contacting the gate structure 3002, and a second contact plug 3005 contacting the source-drain doped region 3003.
The metal interconnection structure 2000 may be connected with the first contact plug 3004 and the second contact plug 3005 to output an electrical signal of the semiconductor device. Further, a connection layer may be formed on the surface of the metal interconnection structure 2000 and connected to, for example, bit lines and conductive plugs of the memory.
Peripheral circuitry 3000 may include any suitable digital, analog, and/or mixed-signal circuitry for facilitating operation of the electronic device. For example, peripheral circuit 3000 may include one or more of the following: a data buffer (e.g., a bit line page buffer), a decoder (e.g., a row decoder or a column decoder), a sense amplifier, a charge pump, a current or voltage reference, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor). In some embodiments, peripheral circuit 3000 is formed using Complementary Metal Oxide Semiconductor (CMOS) technology.
FIG. 16 is a schematic cross-sectional view of a memory structure according to one embodiment of the present application. As shown in fig. 15, another aspect of the present application also provides a memory 4000 including a metal interconnect structure 2000 fabricated by the above method. The memory 4000 may include a memory array 4001 and a peripheral circuit 4002 connected to the memory array 4001. The peripheral circuit 4002 includes a metal interconnect structure 2000 provided in another aspect of the present application.
In one embodiment of the present application, the memory 4000 may be a two-dimensional memory or a three-dimensional memory. For example, it may be at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.
Specifically, taking a three-dimensional NAND memory as an example, the memory array 4001 may include a first substrate 4003 and a plurality of memory strings 4004 on the first substrate 4003. A first conductive plug 4005 is disposed over the memory string 4004. The peripheral circuit 4002 includes a plurality of semiconductor devices arranged in an array, a metal interconnection structure 2000, and a bit line 4006. Bit line 4006 has one end connected to first conductive plug 4005 and the other end connected to metal interconnect structure 2000 to implement electrical signal transmission in memory 4000.
Fig. 17 is a schematic structural diagram of a storage system 10000 according to an embodiment of the present application.
As shown in fig. 17, yet another aspect of the present application also provides a memory system 10000. The memory system 10000 can include a memory 4000 and a controller 6000. The memory 4000 may be the same as the memory described in any of the above embodiments, and is not described in detail in this application. The memory system 10000 can be a two-dimensional memory system or a three-dimensional memory system, and the following description will take a three-dimensional memory system as an example.
The three-dimensional memory system 10000 can include a three-dimensional memory 4000, a host 5000, and a controller 6000. The three-dimensional memory 4000 may be the same as the three-dimensional memory described in any of the above embodiments, and details thereof are not repeated herein. The controller 6000 may control the three-dimensional memory 4000 through the channel CH, and the three-dimensional memory 4000 may perform operations based on the control of the controller 6000 in response to a request from the host 5000. The three-dimensional memory 4000 may receive a command CMD and an address ADDR from the controller 5000 through a channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 4000 may perform an internal operation corresponding to a command on an area selected by an address.
In some embodiments, the three-dimensional memory system may be implemented as a memory device such as a universal flash memory storage (UFS) device, a Solid State Disk (SSD), a multimedia card in the form of an MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Personal Computer Memory Card International Association (PCMCIA) card type memory device, a Peripheral Component Interconnect (PCI) type memory device, a PCI express (PCI-E) type memory device, a Compact Flash (CF) card, a smart media card, or a memory stick, and so forth. Fig. 18 is a schematic structural diagram of an electronic device 20000 according to an embodiment of the present application.
As shown in fig. 17, a further aspect of the embodiment of the present application further provides an electronic device 20000. The electronic device 20000 includes a memory 4000. The memory 4000 may be the same as the memory described in any of the above embodiments, and is not described in detail in this application. The electronic device 20000 may be a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, or other devices with a storage function. Thus, the other module 8000 of the electronic apparatus 20000 may be determined according to a specific device type of the electronic apparatus 20000, the other module 8000 may control the three-dimensional memory 4000 through a channel, etc., and the three-dimensional memory 4000 may receive a command CMD and an address ADDR from the other module 8000 through a channel, etc., and access an area selected from the memory cell array in response to the address, the other module 8000 may include a controller. This is not limited in this application.
The application provides a peripheral circuit, a memory, a storage system and an electronic device, and the metal interconnection structure provided by the application is arranged, so that the peripheral circuit, the memory, the storage system and the electronic device have the same beneficial effects as the metal interconnection structure, and the details are not repeated herein.
Furthermore, although an exemplary self-aligned patterning process and an exemplary metal interconnect structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added from the above-described methods or structures. Furthermore, the materials of the various layers illustrated are merely exemplary.
The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (27)

1. A method of self-aligned patterning, the method comprising:
forming a plurality of mandrels arranged at intervals on a substrate, and forming side walls on two sides of the mandrels;
forming a dielectric layer covering the mandrel and the side walls, wherein the dielectric layer has a low dielectric constant;
removing part of the dielectric layer to expose the top surface of the side wall; and
and removing the side wall to form a groove.
2. The method of claim 1, wherein the dielectric constant K of the dielectric layer satisfies:
2≤K≤3。
3. the method of claim 1, wherein the dielectric layer comprises: at least one of a black diamond layer and a nitrogen doped silicon carbide layer.
4. The method of claim 1, wherein forming a dielectric layer overlying the mandrel and the sidewalls comprises:
and forming a dielectric layer covering the mandrel and the side wall by using a low dielectric material.
5. The method of claim 1, wherein forming a dielectric layer overlying the mandrel and the sidewalls comprises:
and forming an air gap in the dielectric layer.
6. The method of claim 5, wherein forming a dielectric layer overlying the mandrel and the sidewalls comprises:
forming the dielectric layer by a deposition process,
the deposition process adopts two deposition rates with different sizes so as to form the air gap in the dielectric layer.
7. The method of claim 6, wherein the deposition process simultaneously uses two different deposition rates to form the air gap in the dielectric layer.
8. The method of claim 6, wherein the depositing process employs two different deposition rates to form the air gap in the dielectric layer comprises:
forming a first dielectric layer on the surface of the mandrel and the surface of the side wall at a first deposition rate; and
forming a second dielectric layer on the surface of the first dielectric layer at a second deposition rate,
wherein the second deposition rate is greater than the first deposition rate.
9. The method of claim 8, wherein a ratio α between the second deposition rate and the first deposition rate is in a range of 1.5 ≦ α ≦ 2.
10. The method of claim 1, wherein removing portions of the dielectric layer to expose top surfaces of the sidewalls comprises:
removing part of the dielectric layer by adopting a chemical mechanical polishing process,
and the grinding operation for removing part of the dielectric layer is stopped at the surface of the mandrel far away from the substrate.
11. The method of claim 1, wherein forming sidewalls on both sides of the mandrel comprises:
forming a cover layer covering the mandrel; and
and removing the parts, located on the top surface of the mandrel and between the side walls of the mandrels, of the covering layer to form the side walls.
12. The method of claim 11, wherein forming a cover layer covering the mandrel comprises:
and forming a covering layer covering the mandrel by adopting an atomic layer deposition process.
13. The method of claim 1,
the side wall has an etching selection ratio relative to the mandrel which is greater than a set value so as to retain the mandrel when the side wall is removed.
14. The method according to any one of claims 1 to 13,
in the direction parallel to the arrangement direction of the mandrels, the width of the side wall is smaller than or equal to that of the mandrels.
15. The method of any of claims 1 to 13, wherein after removing the sidewalls to form trenches, the method further comprises:
and filling the groove with a metal layer to form a metal interconnection structure.
16. A metal interconnect structure, comprising:
a substrate; and
an interconnect layer disposed on the substrate and comprising: a metal layer, a mandrel and an interlayer dielectric layer,
a groove is formed between the mandrel and the interlayer dielectric layer;
the metal layer is arranged in the groove; and
the interlayer dielectric layer is a low dielectric constant dielectric layer.
17. The metal interconnect structure of claim 16, wherein said metal interconnect structure comprises a plurality of said metal layers;
the interlayer dielectric layer comprises a first interlayer dielectric layer positioned between the adjacent metal layers; and
at least one of the air gaps formed in the first interlayer dielectric layer.
18. The metal interconnect structure of claim 17, wherein said air gap is located in a middle or lower portion of said first interlayer dielectric layer and extends in a direction perpendicular to said substrate.
19. The metal interconnect structure of claim 17, wherein said first interlevel dielectric layer comprises a first dielectric layer and a second dielectric layer sequentially disposed in a direction perpendicular to said substrate.
20. The metal interconnect structure of claim 19, wherein said air gap comprises a first portion in said first dielectric layer and a second portion in said second dielectric layer, and wherein said first portion is larger than said second portion.
21. The metal interconnection structure of claim 16, wherein the dielectric constant K of the interlevel dielectric layer satisfies:
2≤K≤3。
22. a peripheral circuit for connection to a memory circuit, the peripheral circuit comprising:
a plurality of semiconductor devices arranged in an array; and
the metal interconnect structure of any of claims 16 to 21, used to connect the semiconductor device with the memory circuit.
23. A memory, the memory comprising:
a storage array; and
peripheral circuitry coupled to the memory array,
wherein the peripheral circuitry comprises a metal interconnect structure as claimed in any one of claims 16 to 21.
24. The memory of claim 23, wherein the memory comprises at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.
25. A memory system comprising a controller and the memory of claim 23 or 24, the controller coupled to the memory and configured to control the memory to store data.
26. An electronic device, comprising: a memory as claimed in claim 23 or 24.
27. The electronic device of claim 26, wherein the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.
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