CN113838611A - QSFP-DD high-speed cable and QSFP-DD high-speed cable assembly - Google Patents

QSFP-DD high-speed cable and QSFP-DD high-speed cable assembly Download PDF

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Publication number
CN113838611A
CN113838611A CN202111428454.5A CN202111428454A CN113838611A CN 113838611 A CN113838611 A CN 113838611A CN 202111428454 A CN202111428454 A CN 202111428454A CN 113838611 A CN113838611 A CN 113838611A
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CN
China
Prior art keywords
wires
row
layer
pads
bonding pads
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Granted
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CN202111428454.5A
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Chinese (zh)
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CN113838611B (en
Inventor
郑美芳
张雪亮
卢玉华
沈诗明
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Pengyuansheng High Tech Co Ltd
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Pengyuansheng High Tech Co Ltd
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Priority to CN202111428454.5A priority Critical patent/CN113838611B/en
Publication of CN113838611A publication Critical patent/CN113838611A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B11/00—Communication cables or conductors
    • H01B11/02—Cables with twisted pairs or quads
    • H01B11/06—Cables with twisted pairs or quads with means for reducing effects of electromagnetic or electrostatic disturbances, e.g. screens
    • H01B11/10—Screens specially adapted for reducing interference from external sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B7/00—Insulated conductors or cables characterised by their form
    • H01B7/0045—Cable-harnesses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B7/00—Insulated conductors or cables characterised by their form
    • H01B7/08—Flat or ribbon cables
    • H01B7/0861—Flat or ribbon cables comprising one or more screens
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B7/00—Insulated conductors or cables characterised by their form
    • H01B7/08—Flat or ribbon cables
    • H01B7/0876—Flat or ribbon cables comprising twisted pairs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461—Means for preventing cross-talk
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461—Means for preventing cross-talk
    • H01R13/6463—Means for preventing cross-talk using twisted pairs of wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/665—Structural association with built-in electrical component with built-in electronic circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R9/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, e.g. terminal strips or terminal blocks; Terminals or binding posts mounted upon a base or in a case; Bases therefor
    • H01R9/11—End pieces for multiconductor cables supported by the cable and for facilitating connections to other conductive members, e.g. for liquid cooled welding cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

The invention discloses a QSFP-DD high-speed cable which comprises 16 leads, wherein the transverse section of each lead is hexagonal, the 16 leads comprise a first row of upper leads, a second row of upper leads, a third row of upper leads, a second row of lower leads and a first row of lower leads which are stacked from top to bottom, four leads of the third row of upper leads and four leads of the second row of lower leads are symmetrically distributed in parallel, the second row of upper leads comprise three leads and respectively span between two adjacent leads of the third row of upper leads, the first row of upper leads comprise two leads and respectively span between two adjacent leads of the second row of upper leads or two sides, and the first row of lower leads comprise three leads and respectively span between two adjacent leads of the second row of lower leads.

Description

QSFP-DD high-speed cable and QSFP-DD high-speed cable assembly
Technical Field
The invention relates to the technical field of printed cables, in particular to a QSFP-DD high-speed cable and a QSFP-DD high-speed cable assembly.
Background
The QSFP-DD (Quad Small Form-factor plug-Double Small plug) package is a package of a high-speed plug-pull module, and is the first choice of 400G optical module packages, so that the data center can effectively increase and expand the cloud capacity as required. QSFP-DD packages increase the number of lanes to eight, up to 25Gbps per lane operating rate by NRZ modulation or 50Gbps per lane operating rate by PAM4 modulation, thereby supporting 200Gbps or 400 Gbps.
In QSFP-DD, QSFP-DD high speed cables are typically soldered to a printed circuit board and then connected to a housing of a QSFP-DD connector. The QSFP-DD high speed cable includes 16 conductors (each conductor including a pair of signal lines) to form eight lanes.
The inventor finds that the prior art has at least the following problems in the process of implementing the invention:
the QSFP-DD connector has the characteristic of high density and small space, the internal space of the connector connected with the QSFP-DD high-speed cable is insufficient, and particularly the lower-layer space height (specifically, the space height formed between the lower-layer surface of the printed circuit board and the inner surface of the connector shell after the printed circuit board connected with the QSFP-DD high-speed cable is inserted into the connector) is low. 16 wires in the existing QSFP-DD high-speed cable are distributed in parallel and symmetrically in 4 rows, and in order to realize welding of a printed circuit board connected with the QSFP-DD high-speed cable, a double-layer wire stacking structure formed on the lower layer surface of the printed circuit board is higher in height (not lower than the sum of the heights of two wires), so that for the wires with larger diameters, the lower layer space inside the connector cannot be accommodated.
Disclosure of Invention
The invention aims to provide a QSFP-DD high-speed cable and a QSFP-DD high-speed cable assembly, which can effectively solve the technical problems in the prior art.
In order to achieve the above object, an embodiment of the present invention provides a QSFP-DD high-speed cable, which is characterized by including sixteen wires, a fixing layer covering the sixteen wires, a shielding layer covering the fixing layer, and a cable cover covering the shielding layer; each lead comprises two signal wires, two ground wires, two first insulating layers, a second insulating layer, an outer layer aluminum foil and a PET adhesive tape; the second insulating layer is used for wrapping the two signal wires of which the outer layers are respectively wrapped with the first insulating layer in a surrounding manner, the two ground wires are respectively arranged on two sides of the second insulating layer, the centers of the two ground wires and the centers of the two signal wires are positioned on the same horizontal plane, the PET adhesive tape is wrapped outside the outer-layer aluminum foil to form a double-layer shielding tape, the double-layer shielding tape is wrapped outside the two ground wires and the second insulating layer in a winding manner to form the lead, and the transverse section of the lead is hexagonal;
the sixteen wires comprise a first row of upper wires, a second row of upper wires, a third row of upper wires, a second row of lower wires and a first row of lower wires which are stacked from top to bottom, the third row of upper wires and the second row of lower wires respectively comprise four wires, the four wires of the third row of upper wires and the four wires of the second row of lower wires are symmetrically distributed in parallel, the second row of upper wires comprise three wires and respectively span between two adjacent wires in the third row of upper wires, and the left lower side surface and the right lower side surface of each wire in the second row of upper wires are respectively and correspondingly attached to the right upper side surface and the left upper side surface of two adjacent wires in the third row of upper wires; the first row of upper layer wires comprise two wires and respectively span between two adjacent wires or two sides of the second row of upper layer wires, and the left lower side surface and/or the right lower side surface of each wire in the first row of upper layer wires are correspondingly attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row of upper layer wires; the first row of lower layer wires comprise three wires and are respectively spanned between two adjacent wires in the second row of lower layer wires, and the upper left side surface and the upper right side surface of each wire in the first row of lower layer wires are correspondingly attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row of lower layer wires respectively.
Preferably, the width of the upper left surface, the upper right surface, the lower left surface and the lower right surface of each conducting wire is the same, and the width of the upper surface and the lower surface of each conducting wire is the same and is greater than or equal to the width of the upper left surface, the upper right surface, the lower left surface and the lower right surface;
the distance between two adjacent wires in the third row of upper wires is consistent with the width of the upper surface/lower surface of each wire, so that the left lower side surface and the right lower side surface of each wire in the second row of upper wires are completely attached to the right upper side surface and the left upper side surface of two adjacent wires in the third row of upper wires, and the left lower side surface and/or the right lower side surface of each wire in the first row of upper wires are completely attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row of upper wires;
the distance between two adjacent wires in the second row of lower layer wires is consistent with each width of the upper surface/lower surface of the wires, so that the upper left side surface and the upper right side surface of each wire in the first row of lower layer wires are completely attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row of lower layer wires.
Preferably, in a transverse cross section of each of the conductive wires, an inner angle formed by the upper left side, the upper right side and the upper side, and an inner angle formed by the lower left side, the lower right side and the lower side are R1, and satisfy: r1 is more than 120 degrees and less than or equal to 150 degrees; the interior angle that upper left side and lower left side constitute and the interior angle that upper right side and lower right side constitute are R2, and satisfy: 60 DEG-R2 < 120 DEG, so that the transverse section of each wire is in a flat hexagon shape.
Preferably, R1 further satisfies: 135 DEG-R1-150 DEG, said R2 further satisfying: r2 is more than or equal to 60 degrees and less than or equal to 90 degrees.
The embodiment of the invention also provides a QSFP-DD high-speed cable assembly which comprises the QSFP-DD high-speed cable and a printed circuit board correspondingly connected with the QSFP-DD high-speed cable.
Preferably, the printed circuit board comprises a circuit board body, an upper bonding pad arranged on the upper surface of the circuit board body and a lower bonding pad arranged on the lower surface of the circuit board body, wherein the upper bonding pad is used for connecting nine wires in the QSFP-DD high-speed cable, and the lower bonding pad is used for connecting the rest seven wires in the QSFP-DD high-speed cable;
the upper-layer bonding pads comprise a first row of upper-layer bonding pads, a second row of upper-layer bonding pads and a third row of upper-layer bonding pads, wherein the first row of upper-layer bonding pads, the second row of upper-layer bonding pads and the third row of upper-layer bonding pads are sequentially distributed from the front side to the back side of the upper surface of the circuit board body; the lower-layer bonding pads comprise a first row of lower-layer bonding pads and a second row of lower-layer bonding pads which are sequentially distributed from the front edge to the back edge of the lower-layer surface of the circuit board body, the first row of lower-layer bonding pads comprise three groups of butt-joint bonding pads, the second row of lower-layer bonding pads comprise four groups of butt-joint bonding pads, and the first row of lower-layer bonding pads and the second row of lower-layer bonding pads are distributed in a staggered mode and are respectively and correspondingly connected with the first row of lower-layer wires and the second row of lower-layer wires; and each group of the butt joint bonding pads is correspondingly connected with one wire.
Preferably, four sets of docking pads of the third row of upper layer pads are close to or adjacent to the rear edge of the upper layer surface; and the distance between four groups of butt joint bonding pads of the second row of lower bonding pads and the rear edge of the lower surface is greater than the length of signal wires and grounding wires exposed in the second row of lower leads correspondingly connected with the second row of lower bonding pads and used for realizing welding.
Preferably, four sets of landing pads of the second row of lower pads are adjacent to or abut a rear edge of the lower surface; the distance between four groups of butt-joint bonding pads of the third row of upper bonding pads and the rear edge of the upper layer surface is greater than the length of signal wires and grounding wires exposed in the third row of upper layer wires correspondingly connected with the third row of upper bonding pads and used for realizing welding.
Preferably, each group of the butt-joint bonding pads comprises four bonding pads, and two signal wires and two grounding wires which are respectively correspondingly connected with each conducting wire; the two signal lines of each wire are correspondingly connected with the middle two bonding pads in each group of the butt-joint bonding pads, and the two grounding lines of each wire are correspondingly connected with the two side bonding pads in each group of the butt-joint bonding pads, so that the butt-joint bonding pads in each group form grounding-signal-grounding arrangement from left to right or from right to left on a printed circuit board, and the adjacent two rows of bonding pads on the upper layer surface/the lower layer surface of the circuit board body form grounding-signal staggered arrangement.
Preferably, the thickness of each conducting wire is the same as that of the printed circuit board.
Compared with the prior art, the QSFP-DD high-speed cable and the QSFP-DD high-speed cable assembly provided by the embodiment of the invention have the following technical effects: in 16 wires contained in the QSFP-DD high-speed cable, the transverse section of each wire is in a hexagonal structure (preferably a flat hexagon) by improving the structure of each wire, so that the thickness (height) of each wire can be effectively reduced, and the wire is favorably accommodated in a shell of a QSFP-DD connector. In addition, 16 wires in the cable are stacked and arranged into 5 rows from top to bottom, the upper three rows (corresponding to 2, 3 and 4 wires) are stacked and arranged in a staggered mode, and the lower two rows are corresponding to 3 and 4 wires) are stacked and arranged in a staggered mode, so that the arrangement structure of all the wires in the QSFP-DD high-speed cable is firmer, the total thickness (height) of the QSFP-DD high-speed cable can be effectively reduced, and the flat QSFP-DD high-speed cable is formed. Moreover, the design of the upper three rows of leads which are arranged in a staggered and stacked manner and the lower two rows of leads which are arranged in a staggered and stacked manner is adopted, so that the design is beneficial to being respectively connected to the bonding pads (three rows of butt-joint bonding pads which are distributed in a staggered manner) on the upper layer surface and the bonding pads (two rows of butt-joint bonding pads which are distributed in a staggered and stacked manner) on the lower layer surface of the printed circuit board, the total height (lower than the sum of the heights of the two leads) after the leads which are connected to the lower layer surface of the printed circuit board are stacked is effectively reduced, and the technical problem caused by the low height of the lower layer space inside the connector in the prior art can be solved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a QSFP-DD high-speed cable assembly according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of another angle of a QSFP-DD high-speed cable assembly according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view of a QSFP-DD high-speed cable according to an embodiment of the present invention.
Fig. 4 is a cross-sectional view of each conductor of a QSFP-DD high-speed cable according to an embodiment of the present invention.
Fig. 5 shows a stacked arrangement of 16 wires of the QSFP-DD high speed cable of fig. 3.
Fig. 6 is a schematic structural diagram of a printed circuit board according to an embodiment of the present invention.
Fig. 7 is a schematic structural diagram of another angle of a printed circuit board according to an embodiment of the present invention.
Fig. 8 is a top view of a printed circuit board showing a pad structure on an upper surface of the printed circuit board according to an embodiment of the present invention.
Fig. 9 is a partial enlarged view shown by an arrow a in fig. 8, showing the structure of a set of landing pads.
Fig. 10 is a bottom view of a printed circuit board showing a pad structure on a lower surface of the printed circuit board in accordance with an embodiment of the present invention.
FIG. 11 is a partial top view of a printed circuit board after connection to a QSFP-DD high-speed cable according to an embodiment of the present invention, showing the connection of the land structures and the conductive lines on the top surface of the printed circuit board.
FIG. 12 is a partial bottom view of a printed circuit board after connection to a QSFP-DD high-speed cable according to an embodiment of the present invention, showing the connection of the land structures and the conductors on the lower surface of the printed circuit board.
FIG. 13 is a partial side view of a printed circuit board after connection to a QSFP-DD high-speed cable according to an embodiment of the present invention, showing the connection of the land structures and the conductors on the top and bottom surfaces of the printed circuit board.
Fig. 14 is a partially enlarged view shown by an arrow B in fig. 13.
Fig. 15 is a top view of a printed circuit board showing a pad structure on an upper surface of the printed circuit board according to a second embodiment of the present invention.
Fig. 16 is a bottom view of a printed circuit board showing a pad structure on a lower surface of the printed circuit board according to a second embodiment of the present invention.
Fig. 17 is an enlarged view of a portion of a printed circuit board according to a second embodiment of the present invention, showing the connection of the pad structures on the upper and lower surfaces of the printed circuit board to the conductive traces.
Fig. 18 is a schematic structural diagram of a QSFP-DD high-speed cable assembly according to an embodiment of the present invention after being connected to a QSFP-DD connector.
Fig. 19 is a sectional view of a QSFP-DD high-speed cable assembly according to an embodiment of the present invention after being connected to a QSFP-DD connector.
The attached drawings indicate the following:
100. a QSFP-DD high-speed cable assembly;
1. a printed circuit board; 11. a circuit board body; 111. the upper layer surface; 1111. the front side of the upper layer surface; 1112. behind the upper surface; 112. a lower layer surface; 1121. the front side of the lower layer surface; 1122. behind the surface of the lower layer;
12. an upper layer pad; 121. a first row of upper layer pads; 122. a second row of upper layer pads; 123. a third row of upper layer pads;
13. a lower layer pad; 131. a first row of lower layer pads; 132. a second row of lower layer pads;
14. an upper layer of golden fingers;
15. a lower layer of golden fingers;
120. butting the bonding pads;
2. QSFP-DD high-speed cable, 21 conducting wire, 22 fixing layer, 23 shielding layer; 24. a cable cover;
211. a signal line; 212. a ground wire; 213. a first insulating layer; 214. a second insulating layer; 215. a double-layer shielding tape;
2101. a left upper side surface; 2102. an upper right side surface; 2103. a left underside surface; 2104. a right underside surface; 2105. an upper surface; 2106. a lower surface;
201. a first row of upper conductors; 202. a second row of upper conductors; 203. a third row of upper conductors; 204. a second row of lower conductors; 205. a first row of lower conductors;
a QSFP-DD connector; 301. a housing;
1' printed circuit board; 111'. upper layer surface; 1111'. front side of upper layer surface; 1112' behind the upper layer surface; 112', lower layer surface; 1121' front of lower layer surface; 1122' behind the lower surface;
upper layer pads; 121' first row of upper layer pads; 122'. a second row of upper layer pads; 123'. third row of upper layer pads;
a lower layer pad; 131'. a first row of lower layer pads; 132' second row of lower level pads.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically connected, electrically connected or can communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1 to 2, an embodiment of the invention provides a QSFP-DD high-speed cable assembly 100, where the QSFP-DD high-speed cable assembly 100 includes a printed circuit board 1 and a QSFP-DD high-speed cable 2 correspondingly connected to the printed circuit board 1. Wherein the QSFP-DD high speed cable 2 comprises sixteen wires, sixteen sets of pads are provided on the surface of the printed circuit board 1 to enable connection (e.g., soldering) with the sixteen wires of the QSFP-DD high speed cable 2, nine sets of pads are provided on the upper surface of the printed circuit board 1 to connect the nine wires in the QSFP-DD high speed cable 2, and seven sets of pads are provided on the lower surface of the printed circuit board 1 to connect the remaining seven wires in the QSFP-DD high speed cable 2.
The specific structures of the printed circuit board 1 and the QSFP-DD high-speed cable 2 will be described below with reference to the accompanying drawings, so as to describe in detail how the printed circuit board 1 and the QSFP-DD high-speed cable 2 are correspondingly connected.
Referring to fig. 3, an embodiment of the present invention provides a QSFP-DD high-speed cable 2, where the QSFP-DD high-speed cable 2 includes sixteen wires 21, a fixed layer 22 wound around and covering the sixteen wires 21, a shielding layer 23 covering the fixed layer 22, and a cable jacket 24 covering the shielding layer 23. The sixteen wires 21 are covered and fixed inside the cable through the fixing layer 22, and it can be understood that in order to make the sixteen wires 21 more firm inside the cable, an adhesive layer may be provided inside the fixing layer 22 and between the sixteen wires 21.
As shown in fig. 4, each of the wires 21 includes two signal lines 211, two ground lines 212, two first insulating layers 213, a second insulating layer 214, an outer layer aluminum foil, and a PET tape (the PET tape is wrapped outside the outer layer aluminum foil to form a double-layer shielding tape 215). Each first insulating layer 213 cladding is respectively at the skin of a signal line 211, second insulating layer 214 cladding is respectively outward two signal lines 211 of first insulating layer 213 encircle the cladding, two ground wires 212 are located respectively the both sides of second insulating layer 214, just the center of two ground wires 212 with the center of two signal lines 211 is located same horizontal plane, double-deck shielding area 215 winding cladding is in two ground wires 212 and the outer 214 of second insulating layer are in order to form the conductor, and make the transverse section of wire 21 is the hexagon.
Preferably, the widths of the upper left surface 2101, the upper right surface 2102, the lower left surface 2103 and the lower right surface 2104 of each of the wires 21 are the same, and the widths of the upper surface 2105 and the lower surface 2106 of each of the wires 21 are the same and are greater than or equal to the widths of the upper left surface 2101, the upper right surface 2102, the lower left surface 2103 and the lower right surface 2104.
In addition, in the transverse cross section of each of the wires 21, an inner angle formed by the upper left side, the upper right side and the upper side and an inner angle formed by the lower left side, the lower right side and the lower side are R1, and satisfy: r1 is more than 120 degrees and less than or equal to 150 degrees. The interior angle that upper left side and lower left side constitute and the interior angle that upper right side and lower right side constitute are R2, and satisfy: 60 DEG-R2 < 120 DEG, so that the transverse section of each of the wires 21 is in the shape of a flat hexagon.
More preferably, R1 further satisfies: 135 DEG-R1-150 DEG, said R2 further satisfying: r2 is more than or equal to 60 degrees and less than or equal to 90 degrees.
With combined reference to fig. 4 and 5, in the QSFP-DD high-speed cable 2 provided by the embodiment, the sixteen wires wrapped and covered by the fixed layer include a first row of upper wires 201, a second row of upper wires 202, a third row of upper wires 203, a second row of lower wires 204 and a first row of lower wires 205, which are stacked from top to bottom. The third row of upper layer wires 203 and the second row of lower layer wires 204 respectively include four wires, and the four wires of the third row of upper layer wires 203 and the four wires of the second row of lower layer wires 204 are symmetrically distributed in parallel.
The second row of upper conductors 202 includes three conductors and spans between two adjacent conductors in the third row of upper conductors 203, and a left lower surface and a right lower surface of each conductor in the second row of upper conductors 202 are correspondingly attached to a right upper surface and a left upper surface of two adjacent conductors in the third row of upper conductors 203. The first row of upper layer conducting wires 201 comprise two conducting wires and respectively span between two adjacent conducting wires or two sides of the second row of upper layer conducting wires 202, and the left lower side surface and/or the right lower side surface of each conducting wire 201 in the first row of upper layer conducting wires are correspondingly attached to the right upper side surface and/or the left upper side surface of the adjacent conducting wire in the second row of upper layer conducting wires 202 respectively.
The first row of lower layer wires 205 comprises three wires and spans between two adjacent wires in the second row of lower layer wires 204, and the upper left side surface and the upper right side surface of each wire in the first row of lower layer wires 205 are correspondingly attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row of lower layer wires 204.
Preferably, the distance between two adjacent wires in the third row of upper wires 203 is the same as the width of the upper/lower surface of each wire 21, so that the lower left and lower right surfaces of each wire in the second row of upper wires 202 can be completely attached to the upper right and upper left surfaces of two adjacent wires in the third row of upper wires 203, and the lower left and/or lower right surfaces of each wire in the first row of upper wires 201 can be completely attached to the upper right and/or upper left surfaces of two adjacent wires in the second row of upper wires 202.
Accordingly, the distance between two adjacent wires in the second row of lower layer wires 204 is the same as the width of the upper/lower surface of each wire, so that the upper left surface and the upper right surface of each wire in the first row of lower layer wires 205 can be completely attached to the lower right surface and the lower left surface of two adjacent wires in the second row of lower layer wires 204.
It can be seen that, in the 16 wires included in the QSFP-DD high-speed cable 2 provided in this embodiment, the structure of each wire is improved to make the transverse cross section of each wire be in a hexagonal structure (preferably, a flat hexagon), so that the thickness (height) of each wire can be effectively reduced, and the QSFP-DD high-speed cable is favorably accommodated in a housing of a QSFP-DD connector. In addition, 16 wires in the cable are stacked and arranged into 5 rows from top to bottom, the upper three rows (corresponding to 2, 3 and 4 wires) are stacked and arranged in a staggered mode, and the lower two rows are corresponding to 3 and 4 wires) are stacked and arranged in a staggered mode, so that the arrangement structure of all the wires in the QSFP-DD high-speed cable is firmer, the total thickness (height) of the QSFP-DD high-speed cable can be effectively reduced, and the flat QSFP-DD high-speed cable is formed. Moreover, the design of the upper three rows of leads which are arranged in a staggered and stacked manner and the lower two rows of leads which are arranged in a staggered and stacked manner is adopted, so that the design is beneficial to being respectively connected to the pads (three rows of butt-joint pads which are distributed in a staggered manner) on the upper surface of the printed circuit board 1 and the pads (two rows of butt-joint pads which are distributed in a staggered and stacked manner) on the lower surface of the printed circuit board 1, the total height (lower than the sum of the heights of the two leads) after the leads which are connected to the lower surface of the printed circuit board 1 are stacked is effectively reduced, and the technical problem caused by the low height of the lower-layer space inside the connector in the prior art can be solved.
Referring to fig. 6 to 7, an embodiment of the present invention provides a printed circuit board 1, where the printed circuit board 1 is suitable for connecting a QSFP-DD high-speed cable, the printed circuit board 1 includes a circuit board body 11, an upper pad 12 disposed on an upper surface 111 of the circuit board body 11, and a lower pad 13 disposed on a lower surface 112 of the circuit board body 11, the upper pad 12 is used to connect nine wires in the QSFP-DD high-speed cable, and the lower pad 13 is used to connect the remaining seven wires in the QSFP-DD high-speed cable.
The upper layer bonding pad 12 is located in a rear area of the upper layer surface 111 close to the upper layer surface rear edge 1112, an upper layer golden finger 14 is arranged in a front area of the upper layer surface 111 close to the upper layer surface front edge 1111, and the upper layer golden finger 14 is correspondingly connected with the upper layer bonding pad 12. The lower layer pads 13 are located in the rear region of the lower layer surface 112 close to the lower layer surface rear edge 1122, and the front region of the lower layer surface 112 close to the lower layer surface front edge 1121 is provided with lower layer gold fingers 15, and the lower layer gold fingers 15 are correspondingly connected with the lower layer pads 13.
Referring to fig. 8 and 10, the upper layer lands 12 include a first row of upper layer lands 121, a second row of upper layer lands 122, and a third row of upper layer lands 123 that are sequentially distributed from an upper layer surface front side 1111 to an upper layer surface rear side 1112 of the upper layer surface 111 of the circuit board body 11. The first row of upper bonding pads 121 comprises two groups of butt-joint bonding pads, the second row of upper bonding pads 122 comprises three groups of butt-joint bonding pads, the third row of upper bonding pads 123 comprises four groups of butt-joint bonding pads, and the first row of upper bonding pads 121, the second row of upper bonding pads 122 and the third row of upper bonding pads 123 are distributed in a staggered mode. The lower layer pads 13 include a first row of lower layer pads 131 and a second row of lower layer pads 132 which are distributed in sequence from a lower layer surface front edge 1121 to a lower layer surface rear edge 1122 of the lower layer surface 112 of the circuit board body 11, the first row of lower layer pads 131 includes three sets of butt-joint pads, the second row of lower layer pads 132 includes four sets of butt-joint pads, and the first row of lower layer pads 131 and the second row of lower layer pads 132 are distributed in a staggered manner.
It is understood that, in the present embodiment, in conjunction with fig. 9, each set of the docking pads 120 is connected to one wire of the QSFP-DD high-speed cable. Each group of the docking pads 120 includes four pads arranged in parallel and at the same interval, and the four pads are respectively and correspondingly connected with two signal lines and two ground lines of one conductor in the QSFP-DD high-speed cable. Two middle bonding pads in each group of the bonding pads 120 are correspondingly connected with two signal wires in each wire, and two side bonding pads in each group of the bonding pads 120 are correspondingly connected with two grounding wires of each wire, so that each group of the bonding pads 120 form a grounding bonding pad 120 b-a signal bonding pad 120 a-a grounding bonding pad 120b arrangement from left to right or from right to left on a printed circuit board.
It can be understood that, in the present embodiment, in the upper surface 111 of the circuit board body 11, the staggered distribution among the first row of upper layer pads 121, the second row of upper layer pads 122, and the third row of upper layer pads 123 specifically means: the symmetry line (bilateral symmetry) of each group of the upper-layer pads 122 in the second row coincides with the symmetry line (bilateral symmetry) between two adjacent groups of the upper-layer pads 123 in the third row, and the symmetry line (bilateral symmetry) of each group of the upper-layer pads 121 in the first row coincides with the symmetry line (bilateral symmetry) between two adjacent groups of the upper-layer pads 122 in the second row (or the two groups of the upper-layer pads 121 in the first row may be symmetrically distributed with any two groups of the upper-layer pads 123 in the third row). Correspondingly, the staggered distribution between the first row of lower layer pads 131 and the second row of lower layer pads 132 specifically means: the symmetry line (bilateral symmetry) of each set of landing pads in the first row of lower pads 131 coincides with the symmetry line (bilateral symmetry) between two adjacent sets of landing pads in the second row of lower pads 132.
Preferably, in this embodiment, in three rows of upper pads on the upper surface 111 of the circuit board body 11, a distance L1 between two adjacent sets of the pads in the same row of upper pads is substantially equal to a distance L2 between two adjacent pads in the same set of the pads, so that, in combination with the design that the three rows of upper pads on the upper surface 111 of the circuit board body 11 are distributed in a staggered manner, two adjacent rows of upper pads on the upper surface 111 of the circuit board body 11 form a ground-signal staggered arrangement. That is, a ground connection pad of the second row upper layer pad 122 is distributed behind any one of the first row upper layer pads 121 connected to the signal line, and a ground connection pad of the third row upper layer pad 123 is distributed behind any one of the second row upper layer pads 122 connected to the signal line. Similarly, in the two rows of lower pads on the lower surface 112 of the circuit board body 11, the distance L1 between two adjacent sets of the landing pads in the same row of lower pads is substantially equal to the distance L2 between two adjacent pads in the same pair of landing pads, so that, in combination with the design of staggered distribution between two rows of lower pads on the lower surface 112 of the circuit board body 11, two rows of lower pads on the lower surface 112 of the circuit board body 11 form a ground-signal staggered arrangement. That is, the ground connection pad of the second row lower layer pad 132 is distributed behind any one of the first row lower layer pads 131 connected to the signal line. Due to the arrangement, when the printed circuit board is connected with the QSFP-DD high-speed cable, the signal lines connected with the front row of pads and the rear row of pads can be staggered, so that front-rear crosstalk between the signal lines connected with the front row of pads and the rear row of pads is effectively avoided, and the high-frequency performance of electrical transmission is improved. It will be appreciated that a certain distance is required between two adjacent rows of pads to facilitate bonding between the pads and the wires.
Referring to fig. 8, fig. 11 and fig. 14, in the present embodiment, four sets of docking pads of the third row of upper pads 123 are close to the upper layer rear edge 1112 of the upper layer surface 111, or four sets of docking pads of the third row of upper pads 123 are adjacent to the upper layer rear edge 1112 of the upper layer surface 111. Thus, when the wires (corresponding to the third row of upper wires) in the QSFP-DD high-speed cable are soldered to the third row of upper bonding pads 123, after the portions (i.e., the soldering terminals or the soldering pins) of the signal wires and the ground wires exposed from the third row of upper wires for soldering are soldered to the third row of upper bonding pads 123, the entire third row of upper wires can be bent downward and then accommodated in the space parallel to the circuit board body 11 at the rear side of the circuit board body 11, so that the thickness of the board body of the printed circuit board 1 is effectively utilized to accommodate the third row of upper wires, and the total height of the stacked wires connected to the upper surface 111 of the printed circuit board 1 is further reduced. Preferably, the thickness of the printed circuit board 1 is the same as the thickness of each wire in the connected QSFP-DD high-speed cable.
In addition, in the lower surface 112 of the circuit board body 11, the distance between the four sets of butt-joint pads of the second row of lower pads 132 and the lower surface back side 1122 of the lower surface 112 is greater than the length of the signal lines and the ground lines (i.e., the solder terminals or the solder pins) exposed from the wires (corresponding to the second row of lower wires) in the QSFP-DD high-speed cable connected to the second row of lower pads 132 for realizing soldering. That is, the second row of lower layer pads 132 in the lower layer surface 112 is not close to the lower layer surface back side 1122 of the lower layer surface 112, and is spaced from the lower layer surface back side 1122 of the lower layer surface 112 by a distance satisfying: the second row of lower conductors can be integrally arranged on the lower surface 112 after being welded with the second row of lower pads 132, so that the problem of vertical crosstalk between signal lines connected with the second row of lower pads 132 on the lower surface 112 and signal lines connected with the third row of upper pads 123 on the upper surface 111 can be effectively avoided.
Preferably, the position of the first row of upper layer pads 121 on the upper surface 111 of the circuit board body 11 is opposite to the position of the first row of lower layer pads 131 on the lower surface 112 of the circuit board body 11, and the position of the second row of upper layer pads 122 on the upper surface 111 of the circuit board body 11 is opposite to the position of the second row of lower layer pads 132 on the lower surface 112 of the circuit board body 11.
Referring to fig. 11 to 14 and 17, a transverse cross section of each of the wires in the QSFP-DD high-speed cable is hexagonal (preferably, flat hexagonal), when the QSFP-DD high-speed cable 2 is connected to the printed circuit board 1, in the QSFP-DD high-speed cable, the second row upper layer wires 202 connected to the second row upper layer pads 122 respectively straddle between two adjacent wires in the third row upper layer wires 203 connected to the third row upper layer pads 123, and a left lower side surface and a right lower side surface of each of the second row upper layer wires 202 respectively and correspondingly attach to a right upper side surface and a left upper side surface of two adjacent wires in the third row upper layer wires 203. The first row upper layer wires 201 correspondingly connected with the first row upper layer bonding pads 121 respectively span between two adjacent wires or two sides of the second row upper layer wires 202, and the left lower side surface and/or the right lower side surface of each wire in the first row upper layer wires 201 are correspondingly attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row upper layer wires 202. The first row lower layer wires 205 correspondingly connected with the first row lower layer pads 131 respectively span between two adjacent wires in the second row lower layer wires 204 correspondingly connected with the second row lower layer pads 132, and the upper left side surface and the upper right side surface of each wire in the first row lower layer wires 205 are correspondingly attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row lower layer wires 204 respectively.
It can be seen that, in the printed circuit board 1 suitable for connecting QSFP-DD high-speed cables provided in this embodiment, by improving the scheme of respectively providing eight pairs of docking pads on the upper and lower layer surfaces in the prior art, nine pairs of docking pads are provided on the upper layer surface of the printed circuit board 1 to connect nine wires in the QSFP-DD high-speed cables, seven pairs of docking pads are provided on the lower layer surface of the printed circuit board 1 to connect the remaining seven wires in the QSFP-DD high-speed cables, and the nine pairs of docking pads provided on the upper layer surface are sequentially distributed in three rows from the front to the rear of the upper layer surface of the circuit board body, corresponding to two, three and four sets of docking pads, and the three rows of docking pads are distributed in a staggered manner, and meanwhile, the seven pairs of docking pads provided on the lower layer surface are sequentially distributed in two rows from the front to the rear of the lower layer surface of the circuit board body, corresponding to three and four sets of docking pads, and the two rows of butt-joint welding pads are distributed in a staggered manner, so that when the QSFP-DD high-speed cable is connected with the printed circuit board 1, 9 wires correspondingly connected with the nine groups of butt-joint welding pads on the upper layer surface are arranged in a staggered manner in three rows (corresponding to 2, 3 and 4 wires) from top to bottom on the upper layer surface of the printed circuit board, and 7 wires correspondingly connected with the seven groups of butt-joint welding pads on the lower layer surface are arranged in a staggered manner in two rows (corresponding to 3 and 4 wires) from bottom to top on the upper layer surface of the printed circuit board. Therefore, the arrangement structure of all the wires in the QSFP-DD high-speed cable connected to the printed circuit board 1 can be firmer, the total height (lower than the sum of the heights of the two wires) of the stacked wires connected to the lower surface 112 of the printed circuit board 1 can be effectively reduced, and the technical problem caused by the low height of the lower space inside the connector in the prior art can be effectively solved. In addition, the last row of the docking pads on the upper surface 111 is close to the upper layer surface rear edge 1112 on the upper surface 111 or is adjacent to the upper layer surface rear edge 1112 on the upper surface 111, and the last row of the docking pads on the lower layer surface 112 is not close to the lower layer surface rear edge 1122 on the lower layer surface 112, so that the lead wires connected with the last row of the docking pads on the upper surface 111 can be placed by effectively utilizing the thickness of the board body of the printed circuit board, the total height of the stacked lead wires connected to the upper layer surface 111 of the printed circuit board 1 is further reduced, and the problem of vertical crosstalk between signal wires connected with the pads on the upper and lower layers of the printed circuit board 1 can be effectively avoided.
Referring to fig. 15 to 17, a printed circuit board 1 'according to a second embodiment of the present invention is similar to the printed circuit board 1 according to the first embodiment, the printed circuit board 1' according to the present embodiment includes an upper pad 12 'disposed on an upper surface 111' of a circuit board body and a lower pad 13 'disposed on a lower surface 112', the upper pad 12 'is used for connecting nine wires in the QSFP-DD high-speed cable, and the lower pad 13' is used for connecting the remaining seven wires in the QSFP-DD high-speed cable. The upper layer pads 12 ' include a first row of upper layer pads 121 ', a second row of upper layer pads 122 ', and a third row of upper layer pads 123 ' distributed in order from an upper layer surface front side 1111 ' to an upper layer surface rear side 1112 ' of the upper layer surface 111 '. The first row of upper bonding pads 121 'comprises two groups of butt-joint bonding pads, the second row of upper bonding pads 122' comprises three groups of butt-joint bonding pads, the third row of upper bonding pads 123 'comprises four groups of butt-joint bonding pads, and the first row of upper bonding pads 121', the second row of upper bonding pads 122 'and the third row of upper bonding pads 123' are distributed in a staggered manner. The lower layer pads 13 'include a first row of lower layer pads 131' and a second row of lower layer pads 132 'sequentially distributed from a lower layer surface front edge 1121' to a lower layer surface rear edge 1122 'of the lower layer surface 112', the first row of lower layer pads 131 'includes three sets of docking pads, the second row of lower layer pads 132' includes four sets of docking pads, and the first row of lower layer pads 131 'and the second row of lower layer pads 132' are alternately distributed.
Unlike the printed circuit board 1 provided in the first embodiment, in the printed circuit board 1 ' provided in the present embodiment, four sets of the landing pads of the second row of the lower layer pads 132 ' are close to the lower layer surface rear side 1122 ' of the lower layer surface 112 ', or four sets of the landing pads of the second row of the lower layer pads 132 ' are adjacent to the lower layer surface rear side 1122 ' of the lower layer surface 112 '. Thus, when the wires (corresponding to the second row of lower-layer wires) in the QSFP-DD high-speed cable are soldered to the second row of lower-layer pads 132 ', the portions (i.e., soldering terminals or soldering pins) of the signal wires and the ground wires exposed from the second row of lower-layer wires for soldering are soldered to the second row of lower-layer pads 132 ', and then the entire second row of lower-layer wires can be bent downward and then accommodated in the space parallel to the circuit board body at the rear side of the circuit board body, so that the thickness of the board body of the printed circuit board 1 ' is effectively used for accommodating the second row of lower-layer wires, and the total height of the stacked wires connected to the lower-layer surface 112 ' of the printed circuit board 1 ' is further reduced.
Meanwhile, in the upper surface 111 of the circuit board body 11 ', the distance between four sets of butt-joint bonding pads of the third row of upper bonding pads 123 ' and the rear edge 1112 ' of the upper surface 111 ' is greater than the length of the exposed signal lines and grounding lines (i.e. the welding terminals or the welding pins) for realizing welding in the wires (corresponding to the third row of upper wires) in the QSFP-DD high-speed cable correspondingly connected with the third row of upper bonding pads 123 '. That is, the third row of lower layer pads 123 'in the upper layer surface 111' is not close to the upper layer surface back edge 1112 'of the upper layer surface 111', and is spaced from the upper layer surface back edge 1112 'of the upper layer surface 111' by a distance that satisfies: the third row of upper layer wires and the third row of upper layer bonding pads 123 'can be integrally arranged on the upper layer surface 111', so that the problem of vertical crosstalk between the signal lines connected with the third row of lower layer bonding pads 123 'on the upper layer surface 111' and the signal lines connected with the second row of lower layer bonding pads 132 'on the lower layer surface 112' can be effectively avoided.
In addition, as a modification of the present embodiment, the third row of upper layer pads 123 'is located opposite to the first row of lower layer pads 131' at the upper layer surface 111 'of the circuit board body and at the lower layer surface 112' of the circuit board body.
It can be seen that, in the printed circuit board 1 'provided in the present embodiment, the last row of the docking pads on the lower surface 112' is close to or adjacent to the lower surface back side 1122 'of the lower surface 112', while the last row of the docking pads on the upper surface 111 'is not close to the upper surface back side 1112' of the upper surface 111 ', so that the thickness of the board body of the printed circuit board can be effectively utilized to place the wires connected to the last row of the docking pads on the lower surface 112', thereby further reducing the total height of the stacked wires connected to the lower surface 112 'of the printed circuit board 1', and further effectively solving the technical problem caused by the low height of the lower space inside the connector in the prior art. Moreover, the problem of vertical crosstalk between signal lines connected with the pads on the upper and lower surfaces of the printed circuit board 1' can be effectively avoided.
It can be understood that other structures of the printed circuit board 1' provided in this embodiment may refer to the description of the corresponding structure of the printed circuit board 1 provided in the first embodiment, and are not described herein again.
It can be seen that, according to the QSFP-DD high-speed cable assembly 100 provided by this embodiment, by using the printed circuit board 1 (or the printed circuit board 1') and the QSFP-DD high-speed cable 2 according to any of the above embodiments, a technical problem that a conductor cannot be accommodated due to a low height of a lower layer space inside a connector in the prior art can be solved, and a problem of vertical crosstalk between signal lines connected to pads on upper and lower layers of the printed circuit board can be effectively avoided. As shown in fig. 18 and 19, when the QSFP-DD high-speed cable assembly 100 provided by the present embodiment is inserted into the inside of the housing 301 of the QSFP-DD connector 300, the wires 21 connected to the pads on the lower-layer surface of the printed circuit board 1 can be completely accommodated in the internal lower-layer space of the connector 300.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A QSFP-DD high-speed cable is characterized by comprising sixteen conducting wires, a fixed layer for coating the sixteen conducting wires, a shielding layer for coating the fixed layer and a cable sleeve for coating the shielding layer; each lead comprises two signal wires, two ground wires, two first insulating layers, a second insulating layer, an outer layer aluminum foil and a PET adhesive tape; the second insulating layer is used for wrapping the two signal wires of which the outer layers are respectively wrapped with the first insulating layer in a surrounding manner, the two ground wires are respectively arranged on two sides of the second insulating layer, the centers of the two ground wires and the centers of the two signal wires are positioned on the same horizontal plane, the PET adhesive tape is wrapped outside the outer-layer aluminum foil to form a double-layer shielding tape, the double-layer shielding tape is wrapped outside the two ground wires and the second insulating layer in a winding manner to form the lead, and the transverse section of the lead is hexagonal;
the sixteen wires comprise a first row of upper wires, a second row of upper wires, a third row of upper wires, a second row of lower wires and a first row of lower wires which are stacked from top to bottom, the third row of upper wires and the second row of lower wires respectively comprise four wires, the four wires of the third row of upper wires and the four wires of the second row of lower wires are symmetrically distributed in parallel, the second row of upper wires comprise three wires and respectively span between two adjacent wires in the third row of upper wires, and the left lower side surface and the right lower side surface of each wire in the second row of upper wires are respectively and correspondingly attached to the right upper side surface and the left upper side surface of two adjacent wires in the third row of upper wires; the first row of upper layer wires comprise two wires and respectively span between two adjacent wires or two sides of the second row of upper layer wires, and the left lower side surface and/or the right lower side surface of each wire in the first row of upper layer wires are correspondingly attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row of upper layer wires; the first row of lower layer wires comprise three wires and are respectively spanned between two adjacent wires in the second row of lower layer wires, and the upper left side surface and the upper right side surface of each wire in the first row of lower layer wires are correspondingly attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row of lower layer wires respectively.
2. The QSFP-DD high-speed cable according to claim 1, wherein the upper left, upper right, lower left and lower right surfaces of each conductor have a uniform width, and the upper and lower surfaces of each conductor have a uniform width that is greater than or equal to the widths of the upper left, upper right, lower left and lower right surfaces;
the distance between two adjacent wires in the third row of upper wires is consistent with the width of the upper surface/lower surface of each wire, so that the left lower side surface and the right lower side surface of each wire in the second row of upper wires are completely attached to the right upper side surface and the left upper side surface of two adjacent wires in the third row of upper wires, and the left lower side surface and/or the right lower side surface of each wire in the first row of upper wires are completely attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row of upper wires;
the distance between two adjacent wires in the second row of lower layer wires is consistent with each width of the upper surface/lower surface of the wires, so that the upper left side surface and the upper right side surface of each wire in the first row of lower layer wires are completely attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row of lower layer wires.
3. The QSFP-DD high-speed cable according to claim 1 or 2, wherein in a transverse cross-section of each conductor, the inner angles formed by the upper left side, the upper right side and the upper side and the inner angles formed by the lower left side, the lower right side and the lower side are R1 and satisfy: r1 is more than 120 degrees and less than or equal to 150 degrees; the interior angle that upper left side and lower left side constitute and the interior angle that upper right side and lower right side constitute are R2, and satisfy: 60 DEG-R2 < 120 DEG, so that the transverse section of each wire is in a flat hexagon shape.
4. The QSFP-DD high-speed cable according to claim 3, wherein R1 is further adapted to: 135 DEG-R1-150 DEG, said R2 further satisfying: r2 is more than or equal to 60 degrees and less than or equal to 90 degrees.
5. A QSFP-DD high-speed cable assembly, comprising the QSFP-DD high-speed cable according to any one of claims 1 to 4 and a printed circuit board correspondingly connected with the QSFP-DD high-speed cable.
6. The QSFP-DD high-speed cable assembly according to claim 5, wherein the printed circuit board comprises a circuit board body, an upper bonding pad arranged on the upper surface of the circuit board body and a lower bonding pad arranged on the lower surface of the circuit board body, the upper bonding pad is used for connecting nine wires in the QSFP-DD high-speed cable, and the lower bonding pad is used for connecting the rest seven wires in the QSFP-DD high-speed cable;
the upper-layer bonding pads comprise a first row of upper-layer bonding pads, a second row of upper-layer bonding pads and a third row of upper-layer bonding pads, wherein the first row of upper-layer bonding pads, the second row of upper-layer bonding pads and the third row of upper-layer bonding pads are sequentially distributed from the front side to the back side of the upper surface of the circuit board body; the lower-layer bonding pads comprise a first row of lower-layer bonding pads and a second row of lower-layer bonding pads which are sequentially distributed from the front edge to the back edge of the lower-layer surface of the circuit board body, the first row of lower-layer bonding pads comprise three groups of butt-joint bonding pads, the second row of lower-layer bonding pads comprise four groups of butt-joint bonding pads, and the first row of lower-layer bonding pads and the second row of lower-layer bonding pads are distributed in a staggered mode and are respectively and correspondingly connected with the first row of lower-layer wires and the second row of lower-layer wires; and each group of the butt joint bonding pads is correspondingly connected with one wire.
7. The QSFP-DD high-speed cable assembly according to claim 6, wherein four sets of butt-pads of the third row of upper pads are near or adjacent to the rear edge of the upper surface; and the distance between four groups of butt joint bonding pads of the second row of lower bonding pads and the rear edge of the lower surface is greater than the length of signal wires and grounding wires exposed in the second row of lower leads correspondingly connected with the second row of lower bonding pads and used for realizing welding.
8. The QSFP-DD high-speed cable assembly according to claim 6, wherein four sets of butt-pads of the second row of lower pads are near or adjacent to a rear edge of the lower surface; the distance between four groups of butt-joint bonding pads of the third row of upper bonding pads and the rear edge of the upper layer surface is greater than the length of signal wires and grounding wires exposed in the third row of upper layer wires correspondingly connected with the third row of upper bonding pads and used for realizing welding.
9. The QSFP-DD high-speed cable assembly according to claim 6, wherein each set of said mating pads comprises four pads, two signal lines and two ground lines respectively connected to each of said conductors; the two signal lines of each wire are correspondingly connected with the middle two bonding pads in each group of the butt-joint bonding pads, and the two grounding lines of each wire are correspondingly connected with the two side bonding pads in each group of the butt-joint bonding pads, so that the butt-joint bonding pads in each group form grounding-signal-grounding arrangement from left to right or from right to left on a printed circuit board, and the adjacent two rows of bonding pads on the upper layer surface/the lower layer surface of the circuit board body form grounding-signal staggered arrangement.
10. The QSFP-DD high-speed cable assembly according to claim 6, wherein the thickness of each of the conductors is the same as the thickness of the printed circuit board.
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CN114267478A (en) * 2021-12-28 2022-04-01 鹏元晟高科技股份有限公司 Ultrathin bending-resistant cable assembly and manufacturing method thereof
CN114615797A (en) * 2022-05-11 2022-06-10 成都英思嘉半导体技术有限公司 Multi-channel high-speed flexible board

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