CN113838504A - Single-bit memory computing circuit based on ReRAM - Google Patents
Single-bit memory computing circuit based on ReRAM Download PDFInfo
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- CN113838504A CN113838504A CN202111416378.6A CN202111416378A CN113838504A CN 113838504 A CN113838504 A CN 113838504A CN 202111416378 A CN202111416378 A CN 202111416378A CN 113838504 A CN113838504 A CN 113838504A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0038—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a single-bit memory computing circuit based on a ReRAM (random access memory), which comprises a memory array module, a row decoding and input driving module, a column decoding and bit line source line driving module, a column selection module and a current-voltage conversion and reading module, wherein the row decoding and input driving module is connected with the row decoding and input driving module; the memory array module comprises a plurality of rows and a plurality of columns of resistive random access memory units; the row decoding and input driving module is connected with word lines in each row of resistive random access memory units in the memory array module, and the column decoding and bit line source line driving module is connected with bit lines and source lines in each column of resistive random access memory units in the memory array module; the column selection module is connected with the bit lines in the resistance change memory units in each column in the memory array module; the current-voltage conversion and reading module is connected with the column selection module and is used for converting the bit line current corresponding to one column selected by the column selection module into voltage and comparing the converted voltage with ten voltage comparators to output ten-bit output data. The invention reduces the occupied area and power consumption of memory calculation.
Description
Technical Field
The invention relates to the field of memory computing, in particular to a single-bit memory computing circuit based on a ReRAM.
Background
Deep Convolutional Neural Networks (DCNNs) continue to demonstrate improved inference accuracy, and deep learning is moving towards edge computing. This development has driven the work of low-resource machine learning algorithms and their accelerated hardware. The most common operation in DCNNs is Multiplication and Accumulation (MAC), which controls power and delay. The MAC operation has high regularity and parallelism, and is therefore very suitable for hardware acceleration. However, the amount of memory access severely limits the energy efficiency of conventional digital accelerators. Therefore, memory Computing (CIM) is increasingly attractive for DCNN acceleration.
In the current memory computing design, the memory is divided into SRAM-based design and new nonvolatile memory-based design according to the storage medium. The design technology based on the SRAM is mature, but the area power consumption is overlarge.
Disclosure of Invention
The invention aims to provide a single-bit memory computing circuit based on a ReRAM (random access memory), which reduces the occupied area and power consumption of memory computing.
In order to achieve the purpose, the invention provides the following scheme:
a ReRAM-based single bit memory compute circuit comprising: the device comprises a storage array module, a row decoding and input driving module, a column decoding and bit line source line driving module, a column selection module and a current-voltage conversion and readout module;
the memory array module comprises a plurality of rows and a plurality of columns of resistive random access memory units; the row decoding and input driving module is connected with word lines in each row of resistive random access memory units in the memory array module, and the column decoding and bit line source line driving module is connected with bit lines and source lines in each column of resistive random access memory units in the memory array module; the column selection module is connected with the bit lines in the resistive random access memory units in each column in the memory array module and is used for selecting one column in the memory array module for calculation; the current-voltage conversion and reading module is connected with the column selection module, and is used for converting the bit line current corresponding to one column selected by the column selection module into voltage and comparing the converted voltage with ten voltage comparators to output ten-bit output data;
the resistive random access memory unit comprises a Re device and an NMOS tube N0, one end of the Re device is connected with a bit line, the other end of the Re device is connected with a source electrode of an NMOS tube N0, a drain electrode of the NMOS tube N0 is connected with a source line, a grid electrode of the NMOS tube N0 is connected with word lines, word lines of the resistive random access memory units in each row are collinear, bit lines of the resistive random access memory units in each row are collinear, and source lines of the resistive random access memory units in each row are collinear.
Optionally, a weight writing resistive random access memory unit mode and a binary multiply-accumulate calculation mode are included;
when the single-bit-memory computing circuit based on the ReRAM writes a weight into a resistive random access memory unit mode, the row decoding and input driving module decodes row address signals of preset storage data, an ith row word line in the memory array module is conducted according to the decoding result of the row address signals, the column decoding and bit line source line driving module decodes column address signals of the preset storage data, and a bit line and a source line of a jth column of resistive random access memory units in the memory array module are selected according to the decoding result of the column address signals; when a weight value is written into 1, the word line of the ith row is set at a high level, an NMOS tube N0 in the resistive random access memory unit of the ith row and the jth column is conducted, the row decoding and bit line source line driving module controls the voltage of a bit line of the jth row of resistive random access memory unit to be a preset voltage, the row decoding and bit line source line driving module controls the source line of the jth row of resistive random access memory unit to be grounded, and an Re device in the resistive random access memory unit of the ith row and the jth column is in a low-resistance state; when the weight value is written into 0, the word line of the ith row is set at a high level, an NMOS tube N0 in the resistive random access memory unit of the ith row and the jth column is conducted, the row decoding and bit line source line driving module controls the bit line of the resistive random access memory unit of the jth column to be grounded, the row decoding and bit line source line driving module controls the source line of the resistive random access memory unit of the jth column to be a set voltage, and the Re device in the resistive random access memory unit of the ith row and the jth column is in a high-resistance state;
when the single-bit memory computing circuit based on the ReRAM is in the binary multiply-accumulate computing mode, input data are input into the row decoding and input driving module, a column of resistive random access memory units are selected by the column selection module, current in bit lines corresponding to the selected column of resistive random access memory units flows through Re devices and NMOS tubes N0 corresponding to the resistive random access memory units to corresponding source lines, and the source lines corresponding to the selected column of resistive random access memory units are grounded.
Optionally, the current-voltage conversion and readout module includes a current-voltage conversion unit and a voltage comparison output unit, the current-voltage conversion unit is configured to convert a current input by the column selection module into a voltage, the voltage comparison output unit includes ten voltage comparators, each of the voltage comparators inputs the converted voltage and outputs a one-bit voltage comparison value, and reference voltages input by each of the voltage comparators are different.
Optionally, the current-voltage conversion unit comprises a tube P1, a tube P2, a tube P3, a tube N1, a tube N2 and a capacitor Cc; the source of the tube P1 is connected to a power supply voltage, the drain of the tube P1 is connected to the column selection module, the gate of the tube P1 is connected to the drain of the tube P1 and the drain of the tube N1, the source of the tube N1 is connected to the drain of the tube P3 and the gate of the tube P2, the gate of the tube N1 is connected to the enable signal S1, the source of the tube P3 is connected to the power supply voltage, the gate of the tube P3 is connected to the enable signal S0, the source of the tube P2 is connected to the power supply voltage, the drain of the tube P2 is connected to the drain of the tube N2 and one end of the capacitor Cc, the other end of the capacitor Cc is grounded, the source of the tube N2 is grounded, the gate of the tube N2 is connected to the enable signal S2, and the drain of the tube P2 is the output end of the current-voltage conversion unit.
Alternatively, the tubes P1, P2, and P3 are PMOS tubes, and the tubes N1 and N2 are NMOS tubes.
Optionally, the voltage comparator comprises a tube N3, a tube N4, a capacitor Ci, an inverter I1, an inverter I2, and an inverter I3; the output end of the current-voltage conversion unit is respectively connected with the drain electrode of a tube N3 and one end of a capacitor Ci, the source electrode of a tube N3 is connected with reference voltage, the grid electrode of a tube N3 is connected with an enabling signal S3, the other end of the capacitor Ci is respectively connected with the source electrode of a tube N4 and the input end of an inverter I1, the output end of an inverter I1 is respectively connected with the input end of an inverter I2 and the drain electrode of the tube N4, the grid electrode of a tube N4 is connected with the enabling signal S4, and the output end of an inverter I2 is connected with the output end of the inverter I3.
Optionally, the tubes N3 and N4 are NMOS tubes.
Optionally, the memory array module includes 256 rows × 64 columns of resistive random access memory cells.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the memory cell is a resistance change memory cell, so that the occupied area and power consumption of memory calculation are reduced, and the current-voltage conversion circuit converts current into a voltage mode and is easy to read; ten voltage comparators are connected in the rear to read the calculation result, thereby simplifying the structure of a reading circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a single-bit-memory computing circuit based on ReRAM according to the present invention;
FIG. 2 is a schematic diagram of a current-to-voltage conversion and readout module according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a single-bit memory computing circuit based on a ReRAM (random access memory), which reduces the occupied area and power consumption of memory computing.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic diagram of a single-bit memory computing circuit based on ReRAM according to the present invention, and as shown in fig. 1, a single-bit memory computing circuit based on ReRAM includes: the circuit comprises a memory array module 1, a row decoding and input driving module 2, a column decoding and bit line source line driving module 3, a column selection module 4 and a current-voltage conversion and readout module 5.
The storage array module 1 is used for storing the weights.
The memory array module 1 comprises a plurality of rows and a plurality of columns of resistive random access memory cells; the row decoding and input driving module 2 is connected with word lines in each row of resistive random access memory units in the memory array module 1, and the column decoding and bit line source line driving module 3 is connected with bit lines and source lines in each column of resistive random access memory units in the memory array module 1; the column selection module 4 is connected with the bit line in each row of the resistance change memory units in the memory array module 1, and the column selection module 4 is used for selecting one row in the memory array module 1 for calculation; the current-voltage conversion and readout module 5 is connected to the column selection module 4, and the current-voltage conversion and readout module 5 is configured to convert a bit line current corresponding to a column selected by the column selection module 4 into a voltage, and compare the converted voltage with ten voltage comparators to output ten-bit output data.
The memory array module 1 comprises 256 rows of resistive random access memory units and 64 columns of resistive random access memory units. In fig. 1, Cell represents a resistance change memory Cell.
The row decoding and input driving module 2 controls the word lines of the memory array in the memory array module 1 for storing the weight when performing row decoding, and the row decoding and input driving module 2 applies the input data of 256 external bits to WL (0) -WL (255) (WL [0] -WL [255] in FIG. 1) when performing driving input.
The column decoding and bit line source line driving module 3 acts on the bit line bl (i) and the source line sl (i) at the time of column decoding, and writes the weight to the bit line bl (i) and the source line sl (i), and grounds the source line sl (i) at the time of calculation.
The column selection module 4 is used for selecting one column of the 64 columns for calculation.
The current-voltage conversion and readout module 5 converts the current into a voltage mode, one voltage value is compared with a reference voltage through ten internal voltage comparators to read the calculation result, and the outputs of the ten voltage comparators constitute a 10-bit output result (output data) (OUT [9:0 ]).
The resistive random access memory unit comprises a Re device and an NMOS tube N0, wherein one end of the Re device is connected with a bit line, the other end of the Re device is connected with a source electrode of an NMOS tube N0, a drain electrode of the NMOS tube N0 is connected with a source line, a grid electrode of the NMOS tube N0 is connected with word lines, the word lines of each row of resistive random access memory units are collinear, the bit lines of each column of resistive random access memory units are collinear, and the source lines of each column of resistive random access memory units are collinear.
The current-voltage converting and reading module 5 includes a current-voltage converting unit 51 and a voltage comparison output unit 52, the current-voltage converting unit 51 is configured to convert the current input by the column selection module 4 into a voltage, the voltage comparison output unit 52 includes ten voltage comparators, each voltage comparator inputs the converted voltage and outputs a one-bit voltage comparison value, and the reference voltages input by each voltage comparator are different.
As shown in fig. 2, the current-voltage conversion unit 51 includes a tube P1, a tube P2, a tube P3, a tube N1, a tube N2, and a capacitor Cc; the source of the tube P1 is connected to a power supply voltage, the drain of the tube P1 is connected to the column selection module 4, the gate of the tube P1 is connected to the drain of the tube P1 and the drain of the tube N1, the source of the tube N1 is connected to the drain of the tube P3 and the gate of the tube P2, the gate of the tube N1 is connected to the enable signal S1, the source of the tube P3 is connected to the power supply voltage, the gate of the tube P3 is connected to the enable signal S0, the source of the tube P2 is connected to the power supply voltage, the drain of the tube P2 is connected to the drain of the tube N2 and one end of the capacitor Cc, the other end of the capacitor Cc is grounded, the source of the tube N2 is grounded, the gate of the tube N2 is connected to the enable signal S2, and the drain of the tube P2 is the output end of the current-voltage conversion unit 51.
The pipe P1, the pipe P2 and the pipe P3 are PMOS pipes, and the pipe N1 and the pipe N2 are NMOS pipes.
As shown in fig. 2, the voltage comparator includes a transistor N3, a transistor N4, a capacitor Ci, an inverter I1, an inverter I2, and an inverter I3; the output end of the current-voltage conversion unit 51 is respectively connected with the drain of the tube N3 and one end of the capacitor Ci, the source of the tube N3 is connected with the reference voltage, the gate of the tube N3 is connected with the enable signal S3, the other end of the capacitor Ci is respectively connected with the source of the tube N4 and the input end of the inverter I1, the output end of the inverter I1 is respectively connected with the input end of the inverter I2 and the drain of the tube N4, the gate of the tube N4 is connected with the enable signal S4, and the output end of the inverter I2 is connected with the output end of the inverter I3.
The tubes N3 and N4 are NMOS tubes.
A single-bit memory computing circuit based on a ReRAM comprises a weight writing resistive random access memory unit mode and a binary multiply-accumulate computing mode.
When a single-bit memory computing circuit based on a ReRAM writes a resistive random access memory cell mode for weight, a row decoding and input driving module 2 decodes row address signals of preset storage data, an ith row word line in a memory array module 1 is gated according to the decoding result of the row address signals, a column decoding and bit line source line driving module 3 decodes column address signals of the preset storage data, and a bit line and a source line of a jth column of resistive random access memory cells in the memory array module 1 are selected according to the decoding result of the column address signals; when a weight value is written into 1, setting the word line of the ith row at a high level, conducting an NMOS (N-channel metal oxide semiconductor) tube N0 in the resistive random access memory unit of the ith row and the jth column, controlling the voltage of a bit line of the resistive random access memory unit of the jth column to be a preset voltage by the column decoding and bit line source line driving module 3, controlling the source line of the resistive random access memory unit of the jth column to be grounded by the column decoding and bit line source line driving module 3, and finishing the writing of the weight value into 1 when a Re device in the resistive random access memory unit of the ith row and the jth column is in a low-resistance state; when the weight value is written into 0, the word line of the ith row is set at a high level, the NMOS tube N0 in the resistive random access memory unit of the ith row and the jth column is conducted, the column decoding and bit line source line driving module 3 controls the bit line of the resistive random access memory unit of the jth column to be grounded, the column decoding and bit line source line driving module 3 controls the source line of the resistive random access memory unit of the jth column to be a set voltage, and the Re device in the resistive random access memory unit of the ith row and the jth column is in a high-resistance state, so that the writing of the weight value into 0 is completed. The set voltage was 1.5V. When the Re device is in a low-resistance state, the circuit where the Re device is located is conducted, and when the Re device is in a high-resistance state, the circuit where the Re device is located is not conducted.
When the single-bit memory computing circuit based on the ReRAM is in a binary multiply-accumulate computing mode, input data are input into a row decoding and input driving module 2, 256 rows of input data are driven to WL (0) -WL (255), a row of resistance change memory cells are selected by a row selection module 4, and current in a bit line corresponding to the selected row of resistance change memory cells flows through Re devices and NMOS tubes N0 corresponding to the resistance change memory cells to a pairAnd the source line corresponding to the selected one column of the resistive random access memory units is grounded. Wl (i) is high when the input data is 1, wl (i) is low when the input data is 0, the storage node is in a low impedance state when the weight value is 1, and the storage node is in a high impedance state when the weight value is 0. When the calculation is started, the column selection module 4 selects the calculated column, WL (i) is enabled, the channel is opened, the current flows from BL (j) to the resistive device Re and the MOS tube to SL (j) and then is grounded, IDL is the current obtained by multiplying and accumulating the whole column, the S0 control tube P3 is closed while the column selection is carried out, the S1 control tube N1 is opened, the S2 control tube N2 is disconnected, the P2 tube is connected and copies and charges IDL to the capacitor Cc, and the current obtained by multiplying and accumulating is converted into VSUMThen S0 control tube P3 is opened, S1 control tube N1 is disconnected, S2 control tube N2 is disconnected, and V reading is started after calculation is finishedSUM。
FIG. 2 is a schematic diagram of the structure of the current-voltage conversion and readout module 5, V being at the reading stageSUMAnd ten reference voltages VREF[9:0]The comparison is performed by ten voltage comparators to obtain a ten-bit result OUT [9:0]]. The reading is divided into two steps: in the first step, at the beginning of calculation, the transistor N2 is controlled to be closed by S3, the transistor N4 is controlled to be opened by S4, the two ends of the inverter I1 are short-circuited and are in a high-gain state, and the potential at the left end of the capacitor Ci is the calculated result VSUM(ii) a Secondly, when the calculation is finished, the tube N2 is controlled to be opened by S3, the tube N4 is controlled to be closed by S4, the reference voltage is supplied, and if V isSUM>VREFIf Ci is left-side discharged and right-side sensed to be low, inverter I1 outputs a high level, and the result out (I) =1 is obtained if VSUM<VREFCi charges left and senses right to be high, inverter I1 outputs a low level, and the result out (I) = 0. The outputs OUT (i) -OUT (9) of the ten voltage comparators form the output result of the current-voltage conversion and readout module.
In the invention, a nonvolatile ReRAM storage unit is adopted as a storage module in the memory computing device, and the ReRAM unit has the advantages of small area and low power consumption; the current-voltage conversion circuit converts the current into a voltage mode, so that the current mode is easy to read; ten voltage comparators are connected in the rear of the array to read the calculation result, so that the structure of a reading circuit is simplified, 64 columns of the array share one reading circuit through a column selection module, and the area of a reading part in the whole circuit is reduced.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (8)
1. A single-bit memory computing circuit based on a ReRAM is characterized by comprising a memory array module, a row decoding and input driving module, a column decoding and bit line source line driving module, a column selection module and a current-voltage conversion and reading module;
the memory array module comprises a plurality of rows and a plurality of columns of resistive random access memory units; the row decoding and input driving module is connected with word lines in each row of resistive random access memory units in the memory array module, and the column decoding and bit line source line driving module is connected with bit lines and source lines in each column of resistive random access memory units in the memory array module; the column selection module is connected with the bit lines in the resistive random access memory units in each column in the memory array module and is used for selecting one column in the memory array module for calculation; the current-voltage conversion and reading module is connected with the column selection module, and is used for converting the bit line current corresponding to one column selected by the column selection module into voltage and comparing the converted voltage with ten voltage comparators to output ten-bit output data;
the resistive random access memory unit comprises a Re device and an NMOS tube N0, one end of the Re device is connected with a bit line, the other end of the Re device is connected with a source electrode of an NMOS tube N0, a drain electrode of the NMOS tube N0 is connected with a source line, a grid electrode of the NMOS tube N0 is connected with word lines, word lines of the resistive random access memory units in each row are collinear, bit lines of the resistive random access memory units in each row are collinear, and source lines of the resistive random access memory units in each row are collinear.
2. The ReRAM-based single-bit memory computing circuit according to claim 1, comprising a weight write resistive random access memory cell mode and a binary multiply-accumulate computing mode;
when the single-bit-memory computing circuit based on the ReRAM writes a weight into a resistive random access memory unit mode, the row decoding and input driving module decodes row address signals of preset storage data, an ith row word line in the memory array module is conducted according to the decoding result of the row address signals, the column decoding and bit line source line driving module decodes column address signals of the preset storage data, and a bit line and a source line of a jth column of resistive random access memory units in the memory array module are selected according to the decoding result of the column address signals; when a weight value is written into 1, the word line of the ith row is set at a high level, an NMOS tube N0 in the resistive random access memory unit of the ith row and the jth column is conducted, the row decoding and bit line source line driving module controls the voltage of a bit line of the jth row of resistive random access memory unit to be a preset voltage, the row decoding and bit line source line driving module controls the source line of the jth row of resistive random access memory unit to be grounded, and an Re device in the resistive random access memory unit of the ith row and the jth column is in a low-resistance state; when the weight value is written into 0, the word line of the ith row is set at a high level, an NMOS tube N0 in the resistive random access memory unit of the ith row and the jth column is conducted, the row decoding and bit line source line driving module controls the bit line of the resistive random access memory unit of the jth column to be grounded, the row decoding and bit line source line driving module controls the source line of the resistive random access memory unit of the jth column to be a set voltage, and the Re device in the resistive random access memory unit of the ith row and the jth column is in a high-resistance state;
when the single-bit memory computing circuit based on the ReRAM is in the binary multiply-accumulate computing mode, input data are input into the row decoding and input driving module, a column of resistive random access memory units are selected by the column selection module, current in bit lines corresponding to the selected column of resistive random access memory units flows through Re devices and NMOS tubes N0 corresponding to the resistive random access memory units to corresponding source lines, and the source lines corresponding to the selected column of resistive random access memory units are grounded.
3. The ReRAM-based single-bit memory computing circuit of claim 1, wherein the current-voltage conversion and readout module comprises a current-voltage conversion unit and a voltage comparison output unit, the current-voltage conversion unit is configured to convert a current input by the column selection module into a voltage, the voltage comparison output unit comprises ten voltage comparators, each voltage comparator inputs the converted voltage and outputs a one-bit voltage comparison value, and reference voltages input by the voltage comparators are different.
4. The ReRAM-based single bit memory computing circuit of claim 3, wherein the current-to-voltage conversion unit comprises a tube P1, a tube P2, a tube P3, a tube N1, a tube N2, and a capacitance Cc; the source of the tube P1 is connected to a power supply voltage, the drain of the tube P1 is connected to the column selection module, the gate of the tube P1 is connected to the drain of the tube P1 and the drain of the tube N1, the source of the tube N1 is connected to the drain of the tube P3 and the gate of the tube P2, the gate of the tube N1 is connected to the enable signal S1, the source of the tube P3 is connected to the power supply voltage, the gate of the tube P3 is connected to the enable signal S0, the source of the tube P2 is connected to the power supply voltage, the drain of the tube P2 is connected to the drain of the tube N2 and one end of the capacitor Cc, the other end of the capacitor Cc is grounded, the source of the tube N2 is grounded, the gate of the tube N2 is connected to the enable signal S2, and the drain of the tube P2 is the output end of the current-voltage conversion unit.
5. The ReRAM based single bit memory compute circuit of claim 4, wherein transistors P1, P2, and P3 are PMOS transistors and transistors N1 and N2 are NMOS transistors.
6. The ReRAM based single bit memory compute circuit of claim 3, wherein the voltage comparator comprises a transistor N3, a transistor N4, a capacitor Ci, an inverter I1, an inverter I2, and an inverter I3; the output end of the current-voltage conversion unit is respectively connected with the drain electrode of a tube N3 and one end of a capacitor Ci, the source electrode of a tube N3 is connected with reference voltage, the grid electrode of a tube N3 is connected with an enabling signal S3, the other end of the capacitor Ci is respectively connected with the source electrode of a tube N4 and the input end of an inverter I1, the output end of an inverter I1 is respectively connected with the input end of an inverter I2 and the drain electrode of the tube N4, the grid electrode of a tube N4 is connected with the enabling signal S4, and the output end of an inverter I2 is connected with the output end of the inverter I3.
7. The ReRAM based single bit memory compute circuit of claim 6, wherein pipe N3 and pipe N4 are NMOS pipes.
8. The ReRAM-based single bit memory computing circuit of claim 1, wherein the memory array module comprises 256 rows by 64 columns of resistive switching memory cells.
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