CN115458010A - Arithmetic unit suitable for nonvolatile memory storage and calculation integrated array - Google Patents
Arithmetic unit suitable for nonvolatile memory storage and calculation integrated array Download PDFInfo
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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Abstract
The invention discloses an arithmetic unit suitable for a nonvolatile memory storage and calculation integrated array, which comprises at least one resistive random access memory, an inverter electrically connected with the resistive random access memory and a capacitor electrically connected with the inverter. In the embodiment of the invention, the factors of resistance mismatch and low ratio of the resistive random access memory are isolated by inserting the phase inverter, and the mismatch limit of the resistive random access memory is transferred to the capacitor by adopting capacitor sampling, so that the mismatch ratio and the power consumption of the operation unit in the nonvolatile memory integrated memory array can be weakened to a greater extent.
Description
Technical Field
The invention relates to the technical field of mixed signal circuits, in particular to an arithmetic unit suitable for a nonvolatile memory storage and calculation integrated array.
Background
Under the promotion of artificial intelligence, the demand of edge computing on computing power is continuously increased, and the demands on complex network computing and data processing speed are more and more strict. Under the current computing framework, how to efficiently utilize the deep learning neural network to process data, and developing a new generation of high energy efficiency neural network accelerator is one of the core problems of research and development in the academic world and the industrial world.
The traditional von Neumann structure separates data processing and storage, and data exchange with a memory is required frequently in the deep learning operation process, so that a large amount of energy is consumed. According to research, the energy consumption for carrying data is 4 to 1000 times that of floating point calculation. As semiconductor processes advance, the power consumption of data handling becomes larger, although the overall power consumption decreases.
The storage and computation integrated architecture is a key technology for breaking the limitation of a storage wall and breaking through the bottleneck of AI computing energy efficiency. The core idea of the storage and computation integrated architecture is to transfer part or all of computation to a memory module, that is, a computation unit and a memory unit are integrated on the same chip. Among a plurality of nonvolatile memories, a resistive random access memory ReRAM can realize a larger resistance ratio (on/off) and a higher tolerance, which is beneficial to improving the precision, accuracy and overall robustness of memory calculation, but the problem of high mismatch of an operation unit of a memory calculation integrated array based on the ReRAM nonvolatile memory at present can occur.
Thus, there is still a need for improvement and development of the prior art.
Disclosure of Invention
The present invention is directed to provide an arithmetic unit suitable for a non-volatile memory integrated array, which solves the above-mentioned drawbacks of the prior art, and aims to solve the problem of high mismatch of the arithmetic unit based on the ReRAM non-volatile memory integrated array in the prior art.
The technical scheme adopted by the invention for solving the problems is as follows:
in a first aspect, an embodiment of the present invention provides an operation unit, where the operation unit includes at least one resistive random access memory, an inverter electrically connected to the resistive random access memory, and a capacitor electrically connected to the inverter.
In one implementation, the inverter is electrically connected to the capacitor through a first switch.
In one implementation, the capacitor is electrically connected to a predetermined bit line through a second switch.
In one implementation manner, the number of the resistive random access memories is two, and the two resistive random access memories are connected in series.
In one implementation, the second switch has a different on-time than the second switch.
In one implementation, the first switch-on time precedes the second switch-on time within a preset period.
In one implementation, the bit line is connected to ground through a third switch.
In a second aspect, an embodiment of the present invention further provides an arithmetic unit-based nonvolatile memory bank array system, where the system includes a bank array, an analog-to-digital converter electrically connected to the bank array, a comparator electrically connected to the analog-to-digital converter, and a shift accumulation module electrically connected to the comparator; the storage and computation integrated array comprises a plurality of operation units.
In one implementation, the operation units in each column of the bank array correspond to one bit line.
In one implementation, the operation units in each column of the bank array correspond to one analog-to-digital converter.
In a third aspect, an embodiment of the present invention further provides an operation method based on an operation unit, where the operation method includes: acquiring input current and weight;
multiplying the current and the weight to obtain a voltage value;
transmitting the voltage to the upper plate of the capacitor through the first switch;
the charge is shared by the second switch and the voltage is output.
In a fourth aspect, an embodiment of the present invention further provides an intelligent terminal, including a memory, and one or more programs, where the one or more programs are stored in the memory, and configured to be executed by one or more processors, where the one or more programs include an operation method for executing the operation unit as described above.
In a fifth aspect, the present invention also provides a non-transitory computer-readable storage medium, where instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the operation method of the operation unit as described above.
The invention has the beneficial effects that: the operation unit comprises at least one resistive random access memory, an inverter electrically connected with the resistive random access memory, and a capacitor electrically connected with the inverter. Therefore, the inverter is inserted to isolate the factors of resistance mismatch and low ratio of the resistive random access memory, the limitation of the resistive random access memory mismatch is transferred to the capacitor by adopting capacitor sampling, and the mismatch ratio and the power consumption of the operation unit in the nonvolatile memory integrated array can be weakened to a great extent.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is also possible for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic diagram of an arithmetic unit according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an operation unit and a timing sequence thereof according to an implementation manner of the embodiment of the invention.
Fig. 3 is a truth table diagram of an and-gate operation unit according to an embodiment of the present invention.
Fig. 4 is a circuit schematic diagram of a conventional integrated architecture based on an inverting amplifier of the prior art.
Fig. 5 is a schematic diagram of a non-volatile memory bank array system according to an implementation manner of the embodiment of the invention.
Fig. 6 is a schematic block diagram of an internal structure of an intelligent terminal according to an embodiment of the present invention.
Detailed Description
The invention discloses an arithmetic unit suitable for a nonvolatile memory storage and calculation integrated array, and in order to make the purpose, technical scheme and effect of the invention clearer and clearer, the invention is further described in detail below by referring to the attached drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the prior art, most of the operation units based on the ReRAM nonvolatile memory integrated array have the following problems:
limited by the non-ideality of ReRAM arrays, the row parallelism of ReRAM is weaker than that of SRAM, affecting the flux boost. The main non-idealities of the single ReRAM computing unit are as follows: 1. the mismatch of Low Resistance State (LRS) and High Resistance State (HRS) results in large standard deviation of the accumulated result value. 2. The resistance ratio is not high enough to result in a small signal discrimination of the accumulated result. 3. The equivalent impedance existing in the ReRAM at different positions causes poor consistency of the accumulated results.
In addition, the conventional storage and computation integrated operation array adopts a current-mode accumulation output mode, as shown in fig. 1. The current mode accumulation type output mode is subjected to linear superposition of resistance mismatch of the ReRAM, so that the array size selection is limited, and a plurality of rows in the same column cannot be simultaneously operated and started. This approach requires the use of a voltage clamping circuit to ensure stability of the current output. And because extra voltage clamp circuit leads to every branch road all to need to increase the power consumption that increases by increasing the fortune and putting, but does not adopt the scheme of fortune to put but the rate of accuracy is low.
In order to solve the problems in the prior art, the embodiment provides an operation unit suitable for a nonvolatile memory storage and calculation integrated array, wherein an inverter is inserted to isolate the factors of resistance mismatch and low ratio of a resistive random access memory, and the mismatch limit of the resistive random access memory is transferred to a capacitor by adopting capacitor sampling, so that the mismatch ratio and the power consumption of the operation unit in the nonvolatile memory storage and calculation integrated array can be greatly reduced. The operation unit in the embodiment of the invention comprises at least one resistive random access memory, an inverter electrically connected with the resistive random access memory, and a capacitor electrically connected with the inverter.
Exemplary Unit
As shown in fig. 1-2, an embodiment of the present invention provides an arithmetic unit suitable for a nonvolatile memory integrated memory array, the arithmetic unit including at least one resistance random access memory, an inverter electrically connected to the resistance random access memory, and a capacitor electrically connected to the inverter.
Specifically, the problem that non-ideality factors such as mismatch of an operation unit in the conventional integrated storage and computation array design affect computation accuracy is solved. In addition, the limitation problem of mismatch of the resistive random access memory (ReRAM) is transferred to the capacitor by using the capacitance sampling, and the mismatch rate of the capacitor is two orders of magnitude smaller than that of the resistive random access memory (ReRAM), so that the mismatch influence of the resistive random access memory (ReRAM) array can be weakened to a greater extent by connecting the resistive random access memory with the inverter and the operation unit consisting of the capacitor.
In this embodiment, as shown in fig. 2, the number of the resistive random access memories (rerams) is two, and the two resistive random access memories are connected in series; in each cell, two resistance change memory cells (ReRAM) for storing weight data W are connected in series in the first stage. Between two resistive random access memories by means of a switch S write Will generate a bias voltage V after being switched on mid The voltage Vmid on the intermediate node is sent to an inverter which is used to isolate the effect of the ReRAM non-linearity problem on the calculation result, while at the same time enabling the set/reset process of the resistive random access memory (ReRAM). In addition, S is write After switching on, V can be adjusted mid Can be adjusted up or down so as to achieve the purpose of adjusting the resistance of the ReRAM. As shown in fig. 2 (a), the operating state of the inverter is determined by the Input on the WL line, and if Input (I) =1, the inverter will reverse the Input and determine V on the top plate of the capacitor C . If Input =0, the inverter cannot operate normally, and is driven by V C And keeping the reset voltage, wherein the reset voltage resets the voltage on the capacitor every period so as to update the voltage to the initial voltage. In this way, the operation unit can realize the function of inputting (I) × weight (W), and fig. 2 (b) shows the timing waveform of the operation unit. The input and weight and gate operation calculation unit truth table is shown in fig. 3. The inverter and the capacitor are connected through a first switch V charge Electrically connected, the output of the inverter being determined by Vmid and being generated by a rail-to-rail voltage which will charge the capacitor behind it. Therefore, the invention isolates the side effect of the nonlinearity of the resistance value of the ReRAM device through voltage division and reverse phase, and only considers the nonlinear effect of a small capacitor. Typically a 1M/100k omega ReRAM of high/low resistance states has a standard deviation of at least 10%, whereas the standard deviation of metal capacitors in a 28nm process is only 0.8%. Furthermore, the proposed charge-based arithmetic unit can also effectively isolate the IR-drop problem common in conventional 1T1R arithmetic units due to the charge sharing-based principle. IR Drop (IR-Drop) refers to a phenomenon in which the voltage drops or rises on the power and ground networks that occur in an integrated circuit. That is, the current flows on the wire I, and the resistance of the wire is proportional to the length of the wire and inversely proportional to the cross section of the wire due to the resistance R. The voltage difference V = I × R across the metal lines. Since the distances from the output end of the conventional current-based operation units in the same column are different, the accumulation result is influenced by the equivalent resistance value of the metal wire I.
In one implementation, the first switch V charge And the second switch V share Are different. In practice, the capacitor and the predetermined Bit Line (BL) pass through the second switch V share Electrically connected by closing a third switch V communicating with the Bit Line (BL) rst Effecting a connection to earth for restarting a new cycle, i.e. reset signal by connecting third switch V rst The Bit Line (BL) is connected to reset the voltage 0. During the predetermined period, the first switch V charge The second switch V is preceded by a switch-on time share The turn-on moment of. That is, in each cycle, the first switch V is turned on first charge The data of the inverter is transferred to the upper plate of the capacitor, and then a second switch V is connected through the upper plate of the capacitor on each column of the nonvolatile memory storage integral array system based on the operation unit share Charge sharing is achieved to generate an output voltage.
Exemplary System
Conventional banked array design as shown in fig. 4, the conventional read scheme accumulates the current in the arithmetic unit, and therefore, an I/V operational amplifier (OPAMP) is required to amplify the analog signal from each column to convert the signal from current to voltage and clamp the bit line voltage. The amplified voltage will then be stored in a sample and hold (S & H) module for subsequent a/D conversion. The problem that the computing unit is mismatched and non-ideal factors influence the computing precision is solved, and meanwhile, the problem of overlarge power consumption is caused by increasing a power amplifier in a current type accumulation output mode. Therefore, the invention designs a nonvolatile memory storage and calculation integrated array system based on the operation unit aiming at the problem of overlarge power consumption of an operational amplifier in a conventional storage and calculation integrated operation array current type accumulation output mode, and adopts a charge redistribution scheme based on a capacitor to collect and distribute all capacitor charges in the same column on all capacitors (including parasitic capacitors) as shown in fig. 5, thereby overcoming the problem of consistency caused by wiring parasitic. The voltage output is finally obtained by redistributing the charges, so that the bit line (Bitline) only needs to reset the voltage in a fixed period, and a voltage clamping circuit is not needed. Compared with the traditional system design, the method can greatly search the mismatch rate and the power consumption of the operation unit. During system design, non-linearity issues limit the number of ReRAM rows that can be activated simultaneously per column of the ReRAM array. In order to reduce the influence of ReRAM mismatch on the calculation precision and increase the percentage of parallel activation of rows in calculation, the invention designs the charge-based operation unit. The invention discloses a nonvolatile memory storage and calculation integrated array system based on an arithmetic unit, which comprises a storage and calculation integrated array, an analog-to-digital converter electrically connected with the storage and calculation integrated array, a comparator electrically connected with the analog-to-digital converter and a shift accumulation module electrically connected with the comparator. The integrated storage and calculation array comprises a plurality of operation units (Macro cells), each operation unit (Macro cell) forms an integrated storage and calculation array in an M-row N-row mode, the input of each row in the integrated storage and calculation array is the same, the output of each row in the integrated storage and calculation array is input to an analog-to-digital converter corresponding to the output of each row through a Bit Line (BL) and then output to a comparator, and multi-bit digital results output from the comparator after multiple cycles are input to a shift accumulation module. The operation units in each column of the bank array correspond to one bit line, that is, the outputs of the operation units (Macro cells) in each column of the bank array all pass through the same bit line. The operation units (Macro cells) in each column of the calculation-integrated array correspond to one analog-to-digital converter, that is, the output of each operation unit (Macro cell) in each column of the calculation-integrated array is input into one analog-to-digital converter ADC. In this way, the capacitors included in the operation cells (Macro cells) of the same column in the bank array all share the charge, and the accumulated voltage is generated on the bit line of the same column. In this way, the Bit Line (BL) can be directly connected to the ADC without the need for a clamp circuit. In addition, the use and hold (S & H) circuitry in conventional ADC designs is eliminated. The voltage on the Bit Line (BL) may be stored during ADC conversion and input to the comparator. In the shift accumulation module, ADC output of each column is circularly shifted according to weight parameters and accumulated in parallel to realize high throughput performance.
Exemplary method
The embodiment provides an arithmetic method based on an arithmetic unit, which is used for an intelligent terminal of a mixed signal circuit, and the method comprises the following steps:
s100, acquiring input current and weight;
step S200, multiplying the current and the weight to obtain a voltage value;
step S300, transmitting voltage to an upper plate of a capacitor through a first switch;
step S400, sharing the charge through the second switch and outputting the voltage.
Specifically, the input current is determined by the input on the WL line, and the weight W is stored in the resistance change memory ReRAM, as shown in fig. 2 (b), reset P at each cycle r During this period, the bit line passes through the third switch V rst The Bit Line (BL) is connected to reset the voltage 0, at which time the capacitor discharges to zero. Also during this time, the first switch V can be switched charge Switching on; then in a charging phase P c During the period, the third switch V is switched rst Open and hold the first switch V charge Turning on and holding the second switch V share And turning off, if the input current is 1, multiplying the input I by the weight W to obtain a voltage value, and updating the voltage value by the capacitor voltage V c . In the sharing phase P s While the first switch V is turned on charge Disconnecting the first switches V corresponding to all the arithmetic units (Macro cells) in each column of the integrated storage array share And switching on to realize charge sharing and generate an output voltage. At this time, the capacitor is connected to the Bit Line (BL) to generate an output result V OUT Output result V OUT Is the voltage value generated by the charge sharing of the capacitor. V OUT After the Nbit is input into the analog-to-digital converter ADC, the digital result of Nbit is obtained by the quantization of the analog-to-digital converter ADC.
The invention has the advantages that:
the invention adopts a mode of inverter isolation and capacitance sampling to isolate non-ideality factors of the ReRAM, including resistance mismatch and too low ratio. The charge redistribution scheme based on the capacitors collects charges of all capacitors in the same column and uniformly distributes the charges to all capacitors (including parasitic capacitors), current is converted into voltage, the problem of consistency caused by parasitic routing is solved, and the power consumption of additional operational amplifiers can be effectively reduced.
Based on the above embodiment, the present invention further provides an intelligent terminal, and a schematic block diagram thereof may be as shown in fig. 6. The intelligent terminal comprises a processor, a memory, a network interface, a display screen and a temperature sensor which are connected through a system bus. Wherein, the processor of the intelligent terminal is used for providing calculation and control capability. The memory of the intelligent terminal comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the intelligent terminal is used for being connected and communicated with an external terminal through a network. The computer program is executed by a processor to implement an arithmetic unit-based operation method. The display screen of the intelligent terminal can be a liquid crystal display screen or an electronic ink display screen, and the temperature sensor of the intelligent terminal is arranged inside the intelligent terminal in advance and used for detecting the operating temperature of internal equipment.
Those skilled in the art will appreciate that the schematic diagram of fig. 6 is merely a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation of the intelligent terminal to which the solution of the present invention is applied, and a specific intelligent terminal may include more or less components than those shown in the figure, or combine some components, or have different arrangements of components.
In one embodiment, an intelligent terminal is provided that includes a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for:
acquiring input current and weight;
multiplying the current and the weight to obtain a voltage value;
transmitting the voltage to the upper plate of the capacitor through the first switch;
the charge is shared by the second switch and the voltage is output.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, databases, or other media used in embodiments provided herein may include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
In summary, the invention discloses an arithmetic unit suitable for a nonvolatile memory integrated array, wherein the arithmetic unit comprises at least one resistive random access memory, an inverter electrically connected with the resistive random access memory, and a capacitor electrically connected with the inverter. In the embodiment of the invention, the factors of resistance mismatch and low ratio of the resistive random access memory are isolated by inserting the phase inverter, and the limit of the resistive random access memory mismatch is transferred to the capacitor by adopting capacitor sampling, so that the mismatch ratio and the power consumption of the operation unit in the nonvolatile memory integrated array can be weakened to a greater extent.
Based on the above embodiments, the present invention discloses an arithmetic method based on an arithmetic unit, it should be understood that the application of the present invention is not limited to the above examples, and it is obvious to those skilled in the art that modifications and changes can be made based on the above description, and all such modifications and changes are intended to fall within the scope of the appended claims.
Claims (10)
1. An arithmetic unit is characterized by comprising at least one resistive random access memory, an inverter electrically connected with the resistive random access memory, and a capacitor electrically connected with the inverter.
2. The arithmetic unit according to claim 1, wherein the inverter and the capacitor are electrically connected through a first switch.
3. The arithmetic unit according to claim 2, wherein the number of the resistance change memories is two, and the two resistance change memories are connected in series.
4. The arithmetic unit of claim 3, wherein the first switch turn-on timing precedes the second switch turn-on timing in a preset period.
5. A non-volatile memory bank array system of arithmetic units according to any of claims 1-4, characterized in that the system comprises a bank array, an analog-to-digital converter electrically connected to the bank array, a comparator electrically connected to the analog-to-digital converter, and a shift accumulation module electrically connected to the comparator; the storage and computation integrated array comprises a plurality of operation units.
6. The nonvolatile memory bank array system of claim 5, wherein a plurality of the operation units in each column in the bank array correspond to one bit line.
7. The non-volatile memory bank array system of claim 6, wherein a number of the arithmetic units in each column of the bank array correspond to one analog-to-digital converter.
8. A method of operating an arithmetic unit as claimed in any one of claims 1 to 4, characterized in that the method comprises:
acquiring input current and weight;
multiplying the current and the weight to obtain a voltage value;
transmitting the voltage to the upper plate of the capacitor through the first switch;
the charge is shared by the second switch and the voltage is output.
9. An intelligent terminal comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory, and wherein the one or more programs being configured to be executed by the one or more processors comprises instructions for performing the method of claim 8.
10. A non-transitory computer readable storage medium, wherein instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of claim 8.
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| US20210158854A1 (en) * | 2019-11-27 | 2021-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Compute in memory system |
| CN113838504A (en) * | 2021-11-26 | 2021-12-24 | 中科南京智能技术研究院 | Single-bit memory computing circuit based on ReRAM |
| CN114694727A (en) * | 2022-02-25 | 2022-07-01 | 北京智芯微电子科技有限公司 | Nonvolatile memory cell data reading method and in-memory calculation data reading method |
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