CN113823637B - Electronic device - Google Patents
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- CN113823637B CN113823637B CN202010563199.4A CN202010563199A CN113823637B CN 113823637 B CN113823637 B CN 113823637B CN 202010563199 A CN202010563199 A CN 202010563199A CN 113823637 B CN113823637 B CN 113823637B
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- electronic device
- insulating layer
- layer
- gate insulating
- conductive particles
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- 239000002245 particle Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000002161 passivation Methods 0.000 claims description 64
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 42
- 238000009413 insulation Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 13
- 239000000853 adhesive Substances 0.000 abstract description 10
- 230000001070 adhesive effect Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 178
- 239000002184 metal Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 22
- 230000000694 effects Effects 0.000 description 6
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920000728 polyester Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- -1 IZO) Chemical compound 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/32148—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the layer connector connecting to a bonding area protruding from the surface
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses an electronic device which comprises a flexible substrate, anisotropic conductive adhesive and an electronic element. The flexible substrate comprises an active region, a bonding pad and a plurality of protrusions positioned on the bonding pad. The anisotropic conductive paste includes a plurality of conductive particles, wherein the conductive particles contact the protrusions. The anisotropic conductive adhesive is located between the bonding pad of the flexible substrate and the electronic element. By arranging the protrusions on the bonding pads of the flexible substrate, the contact area between the conductive particles of the anisotropic conductive adhesive and the flexible substrate can be increased. By making the conductive particles contact the protrusions, the deformation amount of the conductive particles can be increased, and the bonding stability between the electronic device and the flexible substrate can be improved. Furthermore, in embodiments in which the conductive particles have an insulating layer, the provision of protrusions is also advantageous for breaking through the insulating layer. In this way, in the bonding process, the external force required to achieve effective contact between the electronic component and the flexible substrate can be reduced, and thus the collapse of the bonding pad of the flexible substrate can be avoided.
Description
Technical Field
The present invention relates to an electronic device, and more particularly, to an electronic device having a protrusion on a bonding pad.
Background
In order to make the conductive particles in the anisotropic conductive paste effectively deform and contact the conductive layer of the bonding pad, the bonding pad and the conductive particles must have a sufficient contact area to achieve effective contact. In order to ensure effective contact between the conductive particles and the bonding pads, a large bonding pressure is required. In an electronic device using a flexible substrate, a larger bonding pressure may cause a sagging of a bonding pad area of the flexible substrate.
In view of this, it is still an urgent need in the industry to provide a flexible substrate that can avoid the flexible substrate from collapsing due to the bonding pressure.
Disclosure of Invention
The invention aims to provide an electronic device capable of avoiding the collapse of a bonding pad of a flexible substrate.
In one embodiment, the electronic device includes a flexible substrate, an anisotropic conductive adhesive, and an electronic component. The flexible substrate comprises an active region, a bonding pad and a plurality of protrusions positioned on the bonding pad. The anisotropic conductive paste includes a plurality of conductive particles, wherein the conductive particles contact the protrusions. The anisotropic conductive adhesive is located between the bonding pad of the flexible substrate and the electronic element.
In one embodiment, each protrusion has a width in the range of 1 micron to 2 microns.
In one embodiment, each protrusion has a height in the range of 0.1 microns to 1 micron.
In one embodiment, adjacent ones of the protrusions have a spacing therebetween in the range of 1.2 microns to 2 microns.
In one embodiment, each protrusion has a width, each conductive particle has a diameter, the width is greater than 20% of the diameter, and the width is less than 3 times the diameter.
In one embodiment, each protrusion has a height, each conductive particle has a diameter, the height is greater than 5% of the diameter, and the height is less than 30% of the diameter.
In one embodiment, adjacent two of the protrusions have a spacing therebetween, each conductive particle has a diameter, the spacing is greater than 50% of the diameter of the conductive particle, and the spacing is less than 3 times the diameter of the conductive particle.
In one embodiment, the conductive particles have a deformation of greater than 15%.
In one embodiment, the protrusion includes a passivation layer having a thickness in a range of 0.3 microns to 0.4 microns.
In one embodiment, the passivation layer has a plurality of segments.
In one embodiment, the protrusion includes a gate insulating layer having a thickness in a range of 0.3 microns to 0.4 microns.
In one embodiment, the gate insulating layer has a plurality of segments.
In an embodiment, the vertical projection of the sections of the gate insulating layer on the flexible substrate overlaps with the sections of the gate insulating layer, respectively.
In one embodiment, a portion of the passivation layer is located between adjacent two of the sections of the gate insulating layer and extends onto the bond pad.
In an embodiment, the protrusion further comprises an amorphous silicon layer between the passivation layer and the gate insulating layer, the amorphous silicon layer having a thickness in a range of 0.05 microns to 0.15 microns.
In one embodiment, the passivation layer has a plurality of segments and the amorphous silicon layer has a plurality of segments.
In an embodiment, the perpendicular projection of the section of the passivation layer on the flexible substrate at least partially overlaps with the perpendicular projection of the section of the amorphous silicon layer on the flexible substrate.
In an embodiment, the gate insulating layer has a plurality of segments, the segments of the gate insulating layer overlap the segments of the gate insulating layer in a vertical projection of the flexible substrate, and the segments of the gate insulating layer overlap the segments of the amorphous silicon layer in a vertical projection of the flexible substrate.
In an embodiment, the protrusion further comprises a gate insulating layer and an amorphous silicon layer, the amorphous silicon layer is located between the passivation layer and the gate insulating layer, wherein the gate insulating layer has a plurality of sections, and the amorphous silicon layer has a plurality of sections.
In one embodiment, a portion of the passivation layer is located between adjacent two of the sections of the gate insulating layer and extends onto the bond pad.
In the above embodiment, by providing the protrusion on the bonding pad of the flexible substrate, the contact area between the conductive particles of the anisotropic conductive paste and the flexible substrate can be increased. In other words, by making the conductive particles contact the protrusions, the deformation amount of the conductive particles can be increased, thereby improving the bonding stability between the electronic device and the flexible substrate. Furthermore, in embodiments in which the conductive particles have an insulating layer, the provision of protrusions is also advantageous for breaking through the insulating layer. In this way, in the bonding process, the external force required to achieve effective contact between the electronic component and the flexible substrate can be reduced, and thus the collapse of the bonding pad of the flexible substrate can be avoided.
Drawings
Fig. 1 is a cross-sectional view of an electronic device according to an embodiment of the invention.
Fig. 2A is an enlarged view of the area a in fig. 1.
Fig. 2B is an enlarged view of the area B in fig. 1.
Fig. 3 is a cross-sectional view of a flexible substrate according to an embodiment of the present invention.
Fig. 4A is a top view of a flexible substrate according to an embodiment of the invention, with a portion of the active region omitted.
Fig. 4B is a top view of a flexible substrate with a portion of the active region omitted, according to an embodiment of the invention.
Fig. 5 is an enlarged view of a portion of the protrusion and bond pad of fig. 3.
Fig. 6A-6F are cross-sectional views of a protrusion and a bonding pad, respectively, according to various embodiments of the present invention.
The main reference numerals illustrate:
10-an electronic device; 100,100 a-flexible substrate; 102-a first metal layer; 104,104s,104 d-a second metal layer; 106-a third metal layer; 108-a protective layer; 110,110a,110b,110c,110d,110e,110f,110 g-projections; 112, 122-gate insulation layer; 112S-upper surface; 112W-sidewalls; 1122A, 1122B, 1122C-segments; 114, 124-amorphous silicon layer; 114S-upper surface; 114W-sidewalls; 1142A, 1142B, 1142C-segments; 116, 126-passivation layer; 116S-upper surface; 116W-sidewall; 200-anisotropic conductive adhesive; 210-conductive particles; 212-an insulating layer; 214-a metal layer; 216-resin; 300-an electronic component; 310-an electrical connection; a, B-region; BP-bond pad; AA-active region; DA-diameter; h-height; w-width; d-spacing; i1-interval; i2-interval; d1—a first direction; d2—a second direction; t1-thickness; t2-thickness; t3-thickness.
Detailed Description
In the following description, numerous practical details of the embodiments of the invention are set forth in the following description, taken in conjunction with the accompanying drawings. However, it should be understood that these practical details are not to be taken as limiting the invention. That is, in some embodiments of the invention, these practical details are unnecessary. Furthermore, for the sake of simplicity of the drawing, some well-known and conventional structures and elements are shown in the drawings in a simplified schematic manner. And the thickness of layers and regions in the drawings may be exaggerated for clarity and like reference numerals refer to like elements throughout the description of the drawings.
Fig. 1 is a cross-sectional view of an electronic device 10 according to an embodiment of the invention. The electronic device 10 includes a flexible substrate 100, an anisotropic conductive adhesive 200, and an electronic component 300. Fig. 2A is an enlarged view of the area a in fig. 1. Referring to fig. 1 and 2A simultaneously. The flexible substrate 100 includes a bonding pad BP and a protrusion 110 on the bonding pad BP. The anisotropic conductive paste 200 includes a plurality of conductive particles 210, wherein the conductive particles 210 contact the protrusions 110. The anisotropic conductive adhesive 200 is located between the bonding pads BP of the flexible substrate 100 and the electronic device 300. The flexible substrate 100 and the electronic component 300 are electrically connected and bonded to each other by the anisotropic conductive adhesive 200. The electronic device 300 includes an electrical connector 310. As shown in fig. 2A, after the electronic component 300 and the flexible substrate 100 are bonded by the bonding process, the conductive particles 210 are pressed by the electrical connector 310 and the bonding pad BP, so that the electrical connector 310 and the conductive layer (as shown in the metal layer 106 in fig. 3) on the bonding pad BP are electrically connected to the circuit between the electronic component 300 and the flexible substrate 100 through the conductive particles 210.
The flexible substrate 100 is, for example, polyimide (PI), polyester (PET), a composite flexible machine material of PI and glass, a composite flexible machine material of PET and glass, or a composite flexible machine material of PI, optical adhesive (OCA) and PET. The electronic component 300 may be, for example, an integrated circuit (INTEGRATED CIRCUIT, IC) or a flexible circuit board (Flexible Printed Circuit, FPC).
The electrical connection 310 may be, for example, gold Bump (Gold Bump), solder Bump (Solder Bump), conductive Bump (Pillar) or other device for electrical connection.
The conductive particles 210 include an insulating layer 212, a metal layer 214, and a resin 216. The core of the conductive particle 210 includes a resin 216, and the metal layer 214 coats the resin 216. The metal layer 214 may be composed of at least one of gold (Au), silver (Ag), copper (Cu), nickel (Ni), and nickel Alloy (Ni Alloy), for example. The insulating layer 212 surrounds the metal layer 214 and the resin 216, but the invention is not limited thereto. In some embodiments, the conductive particles 210 may also not include the insulating layer 212.
As shown in fig. 2A, by providing the protrusion 110 on the bonding pad BP of the flexible substrate 100, the contact area between the conductive particles 210 and the flexible substrate 100 can be increased. In other words, by making the conductive particles 210 contact the protrusions 110, the deformation amount of the conductive particles 210 can be increased, thereby improving the bonding stability between the electronic component 300 and the flexible substrate 100. In an embodiment, the deformation of the conductive particles 210 is greater than 15%, thereby improving the bonding stability between the electronic device 300 and the flexible substrate 100. In addition, in embodiments where the conductive particles 210 have an insulating layer 212, providing the protrusions 110 also facilitates breaking through the insulating layer 212. In this way, in the bonding process, the external force required to achieve effective contact between the electronic component 300 and the flexible substrate 100 can be reduced, and thus the collapse of the bonding pads BP of the flexible substrate 100 can be avoided.
As shown in fig. 2A, the protrusion 110 has a width W in the range of about 1 micron to 2 microns. The protrusions 110 have a height H in the range of about 0.1 microns to 1 micron. After the electronic component 300 is bonded to the flexible substrate 100 through the bonding process, a space I1 is provided between the electrical connector 310 of the electronic component 300 and the bonding pad BP of the flexible substrate 100. The electrical connector 310 of the electronic device 300 has a space I2 between the top ends of the protrusions 110, and the space I2 is smaller than the space I1. Such a structure can overcome the problem of rebound of the conductive particles 210 during environmental testing or after the electronic device 10 is used for a long time. In other words, since the interval I2 between the electrical connector 310 and the top end of the protrusion 110 is smaller, even if the interval I1 between the electrical connector 310 and the bonding pad BP increases with time or environmental changes, the contact area between the conductive particles 210 and the flexible substrate 100 is still ensured to be sufficient to maintain the effective contact and the effective electrical connection between the electronic device 300 and the flexible substrate 100.
Fig. 2B is an enlarged view of the area B in fig. 1. It is also possible that a portion of the conductive particles 210 is in contact with the protrusion 110 and another portion is located on the bonding pad BP without the protrusion 110. However, the height difference generated by the protrusion 110 may also have an effect of pressing the protrusion 110. In other words, the protrusion 110 does not need to be completely covered by the conductive particles 210, and may have the technical effect of increasing the contact area between the conductive particles 210 and the flexible substrate 100. It is understood that the size of the protrusion 110 may not be smaller than the size of the conductive particle 210, as long as the protrusion 110 on the bonding pad BP can increase the deformation amount of the conductive particle 210. The relationship between the size of the protrusion 110 and the size of the conductive particle 210 will be described in the subsequent paragraphs.
Fig. 3 is a cross-sectional view of a flexible substrate 100 according to an embodiment of the invention. The flexible substrate 100 further includes an active region AA. In this embodiment, the flexible substrate 100 includes a plurality of protrusions 110 on the bonding pad BP. Adjacent ones of the protrusions 110 have a spacing D therebetween, the spacing D being in a range of about 1.2 microns to 2 microns.
Referring to fig. 1 and 3, the conductive particles 210 have a diameter DA. In some embodiments, the diameter DA of the conductive particles 210 is approximately in the range of about 3 microns to 10 microns, but the invention is not limited thereto, and a user can select a suitable size of the conductive particles 210 according to the needs. The width W of the conductive particles 210 is greater than 20% of the diameter DA, and the width W is less than 3 times the diameter DA. The height H of the conductive particles 210 is greater than 5% of the diameter DA, and the height H is less than 30% of the diameter DA. Such a structural design ensures that the contact area between the conductive particles 210 and the flexible substrate 100 is sufficient to maintain an effective contact and an effective electrical connection between the electronic component 300 and the flexible substrate 100. The pitch D of the conductive particles 210 is greater than 50% of the diameter DA of the conductive particles 210, and the pitch D is less than 3 times the diameter DA of the conductive particles 210. Such a structural design ensures that the conductive particles 210 can contact the protrusions 110 to generate larger deformation (see fig. 2A and 2B).
Referring to fig. 3, the protrusion 110 includes a gate insulating layer 112, an amorphous silicon layer 114, and a passivation layer 116. An amorphous silicon layer 114 is located between the gate insulating layer 112 and the passivation layer 116. The amorphous silicon layer 114 contacts the gate insulating layer 112 and the passivation layer 116. The active area AA has an active array 120. The active array 120 has a gate insulation layer 122, an amorphous silicon layer 124, and a passivation layer 126. The gate insulating layer 122 of the active region AA extends to the gate insulating layer 112 over the bonding pad BP. The gate insulating layer 122 of the active region AA and the gate insulating layer 112 above the bonding pad BP may be formed in the same process step. The amorphous silicon layer 124 of the active area AA and the amorphous silicon layer 114 above the bonding pad BP may also be formed in the same process step. The passivation layer 126 of the active region AA and the passivation layer 116 over the bond pad BP may also be formed in the same process step. A second metal layer 104S, 104D is further disposed between the amorphous silicon layer 124 and the passivation layer 126 of the active area AA, which are a Source (Source) and a Drain (Drain) of a Thin Film Transistor (TFT) of the active area AA, respectively.
Between the flexible substrate 100 and the gate insulating layer 112, there is a first metal layer 102, which is located on the active area AA and the bonding pad BP. A third metal layer 106, such as a transparent conductive film, is disposed over the passivation layer 116 of the protrusion 110 and the passivation layer 126 of the active region AA. For example, the third metal layer 106 may be indium zinc oxide (Indium zinc oxide, IZO), indium tin oxide (Iindium tin oxide, ITO), or other transparent metal oxide film. A passivation layer 108 is further disposed between the passivation layer 126 of the active region AA and the third metal layer 106. The active area AA further includes a contact via 130, and the first metal layer 102, the second metal layer 104, and the third metal layer 106 in the contact via 130 are in contact with each other.
In the process of forming the active array 120, the gate insulating layer 112, the amorphous silicon layer 114 and the passivation layer 116 may be formed on the bonding pad BP by a patterning process according to the above description. In other words, the fabrication of the protrusion 110 can be achieved by merely adjusting the original mask design without adding process steps.
Fig. 4A is a top view of the flexible substrate 100 according to an embodiment of the invention, omitting a portion of the active area AA (see fig. 3). In the present embodiment, the protrusion 110 is elongated and extends along the first direction D1. The adjacent two protrusions 110 have a distance D therebetween in the second direction D2. The second direction D2 is different from the first direction D1. In the present embodiment, the second direction D2 is substantially perpendicular to the first direction D1.
Fig. 4B is a top view of the flexible substrate 100a according to an embodiment of the invention, omitting a portion of the active area AA (see fig. 3). In this embodiment, the protrusion 110a is island-shaped. The width W of the protrusion 110a is substantially the diameter of the protrusion 110 a. The adjacent two protrusions 110a have a distance D therebetween.
Fig. 5 is a partial enlarged view of the protrusion 110 and the bonding pad BP in fig. 3. In the present embodiment, the gate insulation layer 112 of the protrusion 110 includes sections 1122A, 1122B, 1122C. The amorphous silicon layer 114 of the protrusion 110 includes segments 1142A, 1142B, 1142C. The segments 1122A, 1122B, 1122C correspond in location to segments 1142A, 1142B, 1142C, respectively. In addition, the vertical projection of the amorphous silicon layer 114 on the bonding pad BP overlaps with the gate insulating layer 112. A portion of the passivation layer 116 is located between adjacent two of the segments 1122A, 1122B, 1122C of the gate insulating layer 112, and this portion of the passivation layer 116 extends onto the bond pad BP. As shown in fig. 5, the passivation layer 116 extending onto the bond pad BP contacts the first metal layer 102. In the present embodiment, the passivation layer 116 covers and contacts the amorphous silicon layer 114, the gate insulating layer 112, and the first metal layer 102. The gate insulating layer 112 has a thickness T1 in the range of about 0.3 microns to 0.4 microns. Amorphous silicon layer 114 has a thickness T2 in the range of about 0.05 microns to 0.15 microns. Passivation layer 116 has a thickness T3 in the range of about 0.3 microns to 0.4 microns. The thickness of the structure may be determined by the requirements in the active area AA, so that the step of depositing the material of the structure may not be changed.
Fig. 6A to 6F are cross-sectional views of a protrusion and a bonding pad BP according to various embodiments of the present invention, respectively. As shown in fig. 6A, the passivation layer 116 of the protrusion 110b has a plurality of sections, without the amorphous silicon layer 114 as shown in fig. 5. The gate insulating layer 112 is continuous and covers the first metal layer 102 and the bonding pad BP.
Referring to fig. 6B, the passivation layer 116 and the gate insulating layer 112 of the protrusion 110c respectively have a plurality of sections, without the amorphous silicon layer 114 as shown in fig. 5. The vertical projection of the section of the passivation layer 116 on the bonding pad BP overlaps the section of the gate insulating layer 112. In addition, the passivation layer 116 has a width smaller than that of the gate insulating layer 112, and thus may form a stepped protrusion 110c. In the present embodiment, the upper surface 116S of the passivation layer 116, the sidewall 116W of the passivation layer 116, a portion of the upper surface 112S of the gate insulating layer 112, and the sidewall 112W of the gate insulating layer 112 constitute a stepped profile of the protrusion 110c. The stepped protrusion 110c facilitates breaking through the insulating layer 212 of the conductive particle 210 and increasing the bond stability between the conductive particle 210 (see fig. 2A, which may or may not include the insulating layer 212) and the bond pad BP.
Referring to fig. 6C, the gate insulating layer 112 and the passivation layer 116 of the protrusion 110d each have a plurality of sections. A section of a portion of passivation layer 116 is located between adjacent two of the sections of gate insulating layer 112 and extends onto bond pad BP. In this embodiment, the section of the passivation layer 116 extending onto the bond pad BP contacts the first metal layer 102. In other words, in the present embodiment, the sections of the two gate insulating layers 112 and the section of one passivation layer 116 constitute the protrusion 110d of the symmetrical shape. In this embodiment, the upper surface 116S of the passivation layer 116, the sidewall 116W of the passivation layer 116, a portion of the upper surface 112S of the gate insulating layer 112, and the sidewall 112W on one side of the gate insulating layer 112 form a stepped profile of the protrusion 110d. The stepped protrusion 110d has the same technical effects as the protrusion 110c shown in fig. 6B, and will not be described again.
Referring to fig. 6D, the amorphous silicon layer 114 and the passivation layer 116 of the protrusion 110e each have a plurality of sections, and the gate insulating layer 112 is continuous and covers the first metal layer 102 and the bonding pad BP. In the present embodiment, the width of the section of the passivation layer 116 is larger than the width of the section of the amorphous silicon layer 114, and the passivation layer 116 and the gate insulating layer 112 surround the amorphous silicon layer 114. The passivation layer 116 is formed in a stepped section by the pattern of the amorphous silicon layer 114, and thus may form the stepped protrusion 110e. In this embodiment, the upper surface 116S of the passivation layer 116 and the sidewall 116W form a stepped profile of the protrusion 110e. The stepped protrusion 110e has the same technical effects as the protrusion 110c shown in fig. 6B, and will not be described again.
Referring to fig. 6E, the protrusion 110f is substantially the same as the protrusion 110E in fig. 6D, except that the gate insulating layer 112 of the protrusion 110f also has a plurality of sections. The vertical projection of the section of the passivation layer 116 at the bonding pad BP overlaps the section of the gate insulating layer 112, and the vertical projection of the section of the amorphous silicon layer 114 at the bonding pad BP overlaps the section of the gate insulating layer 112. In the present embodiment, the width of the gate insulating layer 112 is greater than the widths of the amorphous silicon layer 114 and the passivation layer 116, so that the stepped protrusion 110f may be formed. In the present embodiment, the upper surface 116S of the passivation layer 116, the sidewall 116W of the passivation layer 116, a portion of the upper surface 112S of the gate insulating layer 112, and the sidewall 112W on one side of the gate insulating layer 112 form a three-layer stepped profile of the protrusion 110f, but the invention is not limited thereto. In other embodiments, different processes may be used to form more layers of the stepped structure. For example, different etch depths may be created by a half-tone (half-tone) mask to form protrusions with more layers of stepped structures. The stepped protrusion 110f has the same technical effects as the protrusion 110e shown in fig. 6D, and will not be described again.
Referring to fig. 6F, the protrusion 110g is substantially the same as the protrusion 110e in fig. 6D, except that the vertical projection of the section of the passivation layer 116 of the protrusion 110g at the bonding pad BP at least partially overlaps with the vertical projection of the section of the amorphous silicon layer 114 at the bonding pad BP. For example, the section of passivation layer 116 on the left in fig. 6F completely covers the section of amorphous silicon layer 114 underneath it, but the sections of passivation layer 116 on the right and middle in fig. 6F cover only a portion of the section of amorphous silicon layer 114, so that the passivation layer 116 on the right and middle together with amorphous silicon layer 114 constitute an asymmetrically shaped stepped protrusion 110g. The upper surface 116S of the passivation layer 116, the sidewall 116W of the passivation layer 116, a portion of the upper surface 114S of the amorphous silicon layer 114, and the sidewall 114W on one side of the amorphous silicon layer 114 form three-layer stepped profiles of the right and middle protrusions 110g, but the invention is not limited thereto. The stepped protrusion 110g has the same technical effects as the protrusion 110e shown in fig. 6D, and will not be described again.
In summary, the present invention can increase the contact area between the conductive particles and the flexible substrate by disposing the protrusions on the bonding pads of the flexible substrate. In other words, by making the conductive particles contact the protrusions, the deformation amount of the conductive particles can be increased, thereby improving the bonding stability between the electronic device and the flexible substrate. Furthermore, in embodiments in which the conductive particles have an insulating layer, the provision of protrusions is also advantageous for breaking through the insulating layer. In this way, in the bonding process, the external force required to achieve effective contact between the electronic component and the flexible substrate can be reduced, and thus the collapse of the bonding pad of the flexible substrate can be avoided. In addition, since the interval between the electrical connection member and the top end of the protrusion is smaller, even if the interval between the electrical connection member and the bonding pad is increased with time or environmental change, the contact area between the conductive particles and the flexible substrate can be ensured to be enough to maintain effective contact and effective electrical connection between the electronic component and the flexible substrate.
While the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is accordingly defined by the appended claims.
Claims (19)
1. An electronic device, comprising:
A flexible substrate comprising an active region, a bond pad, and a plurality of protrusions on the bond pad, wherein a space is provided between two adjacent protrusions, and the protrusions comprise a passivation layer;
An anisotropic conductive paste comprising a plurality of conductive particles, wherein the plurality of conductive particles contact the plurality of protrusions, each of the conductive particles having a diameter, the spacing being greater than 50% of the diameter of the conductive particles, and the spacing being less than 3 times the diameter of the conductive particles; and
And the passivation layer protrudes towards the electronic component relative to the bonding pad.
2. The electronic device of claim 1, wherein each of the plurality of protrusions has a width in a range of 1 micron to 2 microns.
3. The electronic device of claim 1, wherein each of the protrusions has a height in a range of 0.1 microns to 1 micron.
4. The electronic device of claim 1, wherein the pitch is in a range of 1.2 microns to 2 microns.
5. The electronic device of claim 1, wherein each of the protrusions has a width, each of the conductive particles has a diameter, the width is greater than 20% of the diameter, and the width is less than 3 times the diameter.
6. The electronic device of claim 1, wherein each of the protrusions has a height, each of the conductive particles has a diameter, the height is greater than 5% of the diameter, and the height is less than 30% of the diameter.
7. The electronic device of claim 1, wherein the plurality of conductive particles have an amount of deformation greater than 15%.
8. The electronic device of claim 1, wherein the passivation layer has a thickness in a range of 0.3 microns to 0.4 microns.
9. The electronic device of claim 1, wherein the passivation layer has a plurality of segments.
10. The electronic device of claim 9, wherein the protrusion comprises a gate insulating layer having a thickness in a range of 0.3 microns to 0.4 microns.
11. The electronic device of claim 10, wherein the gate insulation layer has a plurality of segments.
12. The electronic device of claim 11, wherein vertical projections of the plurality of sections of the gate insulating layer onto the bond pad overlap the plurality of sections of the gate insulating layer, respectively.
13. The electronic device of claim 11, wherein a portion of the passivation layer is located between adjacent two of the plurality of sections of the gate insulating layer and extends onto the bond pad.
14. The electronic device of claim 10, wherein the protrusion further comprises an amorphous silicon layer between the passivation layer and the gate insulating layer, the amorphous silicon layer having a thickness in a range of 0.05 microns to 0.15 microns.
15. The electronic device of claim 14, wherein the passivation layer has a plurality of segments and the amorphous silicon layer has a plurality of segments.
16. The electronic device of claim 15, wherein a perpendicular projection of the plurality of sections of the passivation layer onto the bond pad at least partially overlaps a perpendicular projection of the plurality of sections of the amorphous silicon layer onto the bond pad.
17. The electronic device of claim 15, wherein the gate insulating layer has a plurality of sections, a vertical projection of the plurality of sections of the passivation layer onto the bond pad overlaps the plurality of sections of the gate insulating layer, and a vertical projection of the plurality of sections of the amorphous silicon layer onto the bond pad overlaps the plurality of sections of the gate insulating layer.
18. The electronic device of claim 9, wherein the protrusion further comprises a gate insulating layer and an amorphous silicon layer between the passivation layer and the gate insulating layer, wherein the gate insulating layer has a plurality of segments, the amorphous silicon layer has a plurality of segments.
19. The electronic device of claim 18, wherein a portion of the passivation layer is located between adjacent two of the plurality of sections of the gate insulating layer and extends onto the bond pad.
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