CN113820011A - Shielding type photocurrent detection circuit for GM-APD - Google Patents
Shielding type photocurrent detection circuit for GM-APD Download PDFInfo
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Abstract
The invention belongs to the field of integrated circuits and discloses a maskable photocurrent detection circuit applied to an avalanche diode Geiger mode (GM-APD). The circuit realizes extraction, quenching and detection state output of GM-APD photocurrent through a switching MOS tube and a digital logic operation circuit. The APD self-adaptive bias reset circuit has the advantages that the APD can be actively quenched and quickly biased and reset according to the circuit state and the input signal; shielding of a single pixel can be realized according to an input pixel enabling signal; an overcurrent protection mechanism can be started when the photocurrent is large, and the voltage of an APD port is limited from being too high; the pixel cascade can be realized, and the array type photoelectric current detection device is suitable for array type photoelectric current detection.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a maskable photocurrent detection circuit applied to a Geiger mode avalanche diode (GM-APD).
Background
The non-scanning three-dimensional laser imaging technology is used for carrying out three-dimensional imaging by measuring the time difference between a laser signal emitted by each pixel and an echo signal, so that three-dimensional information of each point in space is obtained. With the development of the ranging technology based on the Time of Flight (TOF), the processing capability of the non-scanning three-dimensional laser array detection circuit for three-dimensional optical signals is gradually improved, and compared with other laser detection modes, the non-scanning three-dimensional laser detection mode has the advantages of longer detection distance and higher imaging speed, and is more suitable for imaging of hidden targets and dynamic targets. In view of the superiority of the three-dimensional laser imaging technology in performance and practicability, the three-dimensional laser imaging technology has very wide application prospect in the fields of military affairs and commerce.
An Avalanche Photodiode (APD) is a photosensitive receiver diode that utilizes the Avalanche multiplication effect to produce an extremely large gain in current. The APD has the advantages of high sensitivity, small volume, low power consumption, small dark current, high quantum efficiency, insensitivity of magnetic field and the like, and is widely applied to optical signal detection in a weak light environment. APDs typically have two modes of operation, Linear Mode (LM) and Geiger Mode (GM). When the reverse bias voltage between two poles of the APD is smaller than the avalanche breakdown voltage, the magnitude of the photocurrent of the APD is in direct proportion to the intensity of the input optical signal, and the device works in a linear mode. APDs operating in the linear mode have relatively low sensitivity to optical signals, and need to receive a certain number of photons to achieve effective detection, which causes a great limitation to applications in low-light environments with only a few photon energies, even a single photon energy. To further increase the sensitivity of photon detection, APDs are typically operated in the geiger mode. When the voltage between two poles of the APD is larger than the avalanche breakdown voltage of the APD, the device works in a Geiger mode, and the current carrier excited by a single photon can trigger the self-sustaining avalanche breakdown with great gain, so that the limit of the sensitivity of the APD is reached. Based on the advantages of high sensitivity, high response speed and the like of the Geiger mode APD, the method has wide application in the aspects of light field detection, three-dimensional laser imaging, laser ranging, military reconnaissance, terrain detection and the like.
The APD working in the Geiger mode cannot be stopped spontaneously after triggering avalanche, and a GM-APD photocurrent detection circuit is needed to quench avalanche photocurrent. The photocurrent detection circuit, also commonly referred to as an interface circuit, performs sensing, detection and quenching of photocurrent and generates a detected status signal. The interface Circuit needs to be used with a Read Out Integrated Circuit (ROIC), the former of which performs signal extraction and the latter of which processes the extracted signal. With the gradual and deep research on the interface circuit and the read-out circuit, the interface circuit gradually tends to be miniaturized and arrayed, and the read-out circuit gradually develops towards higher precision and wider range.
Disclosure of Invention
The invention aims to provide a circuit for detecting a photoelectric current of a Geiger-mode avalanche diode (GM-APD) applied to a single pixel. The circuit can realize extraction and quenching of GM-APD photocurrent and overcurrent protection during large input photocurrent, and can realize selective shielding of a single pixel through enabling control of the logic circuit, and finally output a state detection signal.
The technical scheme of the invention is as follows:
a GM-APD (GM-avalanche photo diode) shielding type photocurrent detection circuit comprises switching tubes MP and MN, an overcurrent protection module, an analog test tube MTESTP (maximum voltage drop out), a Level Shift module, a delay module and a digital logic module.
The switching tubes MP and MN are used for controlling the reverse bias voltage of two poles of the APD, so that the APD is controlled to work in a Geiger mode or quench avalanche photocurrent.
The overcurrent protection module comprises a first NMOS transistor NMOS1, a second NMOS transistor NMOS2, a third NMOS transistor NMOS3, a fourth NMOS transistor NMOS4, a first PMOS transistor PMOS1 and a fuse R0. The method is used for limiting the voltage of an APD port within a safe voltage range when the APD generates large avalanche photocurrent.
The simulation test tube MTESTP is used for simulating the effect of arriving of optical signals when no laser echo signals exist.
The Level Shift module comprises a fifth NMOS transistor NMOS5 and a second PMOS transistor PMOS2, and is used for carrying out Level Shift on an input digital signal so as to be conveniently connected with the digital logic module.
The delay module includes a first inverter INV1 and a second inverter INV2, and is used for delaying an input reset control signal ARM _ IN, so as to facilitate the cascade and array of the photocurrent detection circuit.
The digital logic module comprises a three-input AND-NOR gate AND _ NOR1, a three-input NOR gate NOR1, a third inverter INV3, a fourth inverter INV4 AND a fifth inverter INV 5. The gate control circuit is used for generating gate control signals of the switching tubes MP and MN, so that the working mode of the APD and the quenching of photocurrent are controlled, and further a detection state signal is output.
Specifically, the source of the switch MP is connected to the power supply voltage VDD, the gate GP is connected to the output terminal of the three-input AND-NOR gate AND _ NOR1 AND the gate of the NMOS3, AND is also connected to the input terminal of INV5, AND the drain APD _ IN is connected to the input terminal a2 of the AND _ NOR 1. The source of the switch tube MN is grounded, the gate GNI is connected to the output terminal of the NOR1, and the drain is connected to the drain APD _ IN of the MP and the drain of the NMOS 3. MP and MN control the potential of APD _ IN point together, realize the control to APD reverse bias voltage.
Specifically, the source of the PMOS1 IN the overcurrent protection module is connected to APD _ IN, the gate is connected to the constant voltage bias VBP, and the drain is connected to the drain of the NMOS2 and the gate of the NMOS 1. The source of NMOS2 is grounded, the gate is connected to a constant voltage bias VBN, and the drain is connected to the drain of PMOS1 and the gate of NMOS 1. The source of NMOS1 is grounded and the drain is connected to APD _ IN. The source of NMOS3 is connected to the drain of NMOS4, the gate is connected to GP, and the drain is connected to APD _ IN. The source of the NMOS4 is connected to ground, and the gate is connected to a constant voltage bias VBN. When overcurrent occurs, the PMOS1 and the NMOS2 provide gate bias voltage for the NMOS1 to turn on the NMOS1, which conducts large current to ground.
Specifically, the source of the analog test tube MTESTP is connected to the power supply VDD, the gate is connected to the input signal TESTP, and the drain is connected to the APD _ IN.
Specifically, the source of PMOS2 in the Level Shift module is connected to VDD, the gate is connected to VBP, and the drain is connected to BLANK of NMOS5 and to the input of INV 3. The source of the NMOS5 is grounded, and the gate is connected to the input enable signal BLANK _ IN.
Specifically, the INV1 input terminal of the delay module is connected to the input reset control signal ARM _ IN, the output signal is connected to the input terminal of the INV2, the input terminal a1 of the AND _ NOR1 AND the input terminal a1 of the NOR1 are connected, AND the output signal GN of the INV2 is outputted to the next-stage pixel as the input reset control signal.
Specifically, an input end a1 of an AND _ NOR1 of the digital logic module is connected to an output end of INV1 AND an input end a1 of a NOR1, an input end a2 is connected to APD _ IN, an input end A3 is connected to an output end of the INV3 AND an input end a2 of the NOR1, AND an output end of the AND _ NOR1 is connected to GP, so that the operating state of the switching tube MP is controlled. An input end A1 of the NOR1 is connected with output ends of an input end A1 AND INV1 of the AND _ NOR1, an input end A2 is connected to an output end of the INV3, an input end A3 is connected to an output of the INV4, AND an output end of the NOR1 is connected to the GNI, so that the working state of the switching tube MN is controlled. The input terminal of INV3 is connected to BLANK, AND the output is sent to input terminal A3 of AND _ NOR 1. The input terminal of the INV5 is connected to the GP, and outputs the state detection signal STOP. The AND _ NOR1 of the digital logic module is a three-input logic gate for realizing operation
Fig. 1 shows the internal circuit thereof, and fig. 2 shows the Symbol (Symbol) thereof.
The invention has the beneficial effects that: the invention can carry out active quenching and bias reset on the APD according to the logic operation of the input signal, and has higher quenching speed and response speed; shielding of a single pixel can be realized according to an input pixel enabling signal; an overcurrent protection mechanism can be started when the photocurrent is large, and the voltage of an APD port is limited from being too high; the pixel cascade can be realized, and the array type photoelectric current detection device is suitable for array type photoelectric current detection.
Drawings
Fig. 1 shows the internal circuitry of the digital three-input logic gate AND _ NOR 1.
Fig. 2 is Symbol of a digital three-input logic gate AND _ NOR 1.
FIG. 3 is a circuit diagram of the present invention.
FIG. 4 is a timing diagram illustrating the operation of the present invention.
Detailed Description
The invention is further elucidated with reference to the drawing.
The digital logic module of the present invention is capable of performing: detecting optical current to generate gate control signals GP and GNI of the switching tubes MP and MN, further controlling the potential of an APD _ IN point and finally outputting a state detection signal; and carrying out logic operation on the input control signal, switching the working mode of the APD and controlling the pixel to enable. The truth table for this block is shown in the following table.
TABLE 1 truth table of digital logic blocks
The logic operation expression of the digital logic module is as follows:
fig. 2 is a circuit diagram of the present invention, and the operation state of the present invention will be explained with reference to fig. 2. When the input mask signal BLANK _ IN is inactive, i.e., BLANK _ IN is 0, the GM-APD photocurrent detection circuit has three operating states:
(1) resetting the state: when the reset control signal ARM _ IN is at a high level, the input control signal is operated by the digital logic module, and then the gate control signal GP of the switching tube MP and the gate control signal GNI of the switching tube MN are set to be high, so that the MP is turned off, the MN is turned on, and the APD anode potential APD _ IN is pulled down to a low potential, so that the reverse bias voltage is increased, the APD operates IN a geiger mode, and the detection circuit enters a state to be detected for waiting for a photocurrent signal.
(2) The state to be detected is as follows: after resetting, the reset control signal ARM _ IN is restored to low level, the gate control signal GP of the switching tube is set to high level, GNI is set to low level, and the switching tubes MP and MN are simultaneously cut off. At the moment, the reverse bias voltage of two poles of the APD is larger than the avalanche breakdown voltage of the APD, a single photon optical signal can be detected, and the circuit is in a state of waiting for detecting the current of the APD.
(3) Quenching state: when an optical signal arrives, the GM-APD generates avalanche breakdown, generates a large photocurrent, and enables the potential of an APD _ IN point to slowly rise. When the voltage of the digital logic circuit rises to the threshold value of the digital logic circuit, the logic gate circuit will change GP to low level, and GNI keeps the low level unchanged, so that the switch tube MP is turned on, and MN is still turned off, and the potential at the APD _ IN point is quickly pulled up to high level, the reverse bias voltage of APD is reduced, and the rising edge signal STOP is output. At the moment, the APD exits from the Geiger mode, the avalanche current is rapidly reduced, and the quenching of the photocurrent is realized. After the photocurrent is quenched, the detection circuit resets the next ARM _ IN at a high level and enters the detection waiting state again.
The invention can realize the overcurrent protection function when the APD current is overlarge. When the external optical signal intensity is high or the reverse bias voltage is high, the APD avalanche current is high, and in order to protect the port and make the port voltage not exceed 6V, the overcurrent protection module is required to work to realize the shunting of the large current. When no photocurrent comes, the NMOS2 of the overcurrent protection module is turned on, the potential at the APD _ IN point is low, the PMOS1 is turned off, no current flows through the two transistors, the gate voltage of the NMOS1 is kept at a low level, the NMOS1 is turned off, and the overcurrent protection module is turned off. When a large photocurrent comes, the APD _ IN point potential rises rapidly to turn on PMOS1, which generates a voltage drop on NMOS2 to raise the gate potential of NMOS1 and turn on NMOS 1. After the NMOS1 is conducted, the APD current is conducted to the ground through the tube, and the voltage of the APD port is stabilized within the range of 6V. In addition, the NMOS3 and the NMOS4 can be conducted when the switching tubes MP and MN are both closed, and the influence of APD dark current is effectively reduced.
IN addition, the present invention can implement a single pixel masking function by inputting the enable control signal BLANK _ IN. As shown IN the truth table of the digital logic circuit, when the masking function is not valid, i.e., BLANK _ IN is equal to 0, the detection circuit operates normally as described above, and when the masking function is valid, i.e., BLANK _ IN is equal to 1, the digital logic latches the gate control signal GP of the switching tube MP and the gate control signal GNI of the switching tube MN to 0. At this time, the potential of the APD _ IN point is high, the APD exits from the geiger mode, cannot receive the photocurrent, and outputs a STOP signal at a continuous high level.
The operation timing diagram of the photocurrent detection circuit is shown in fig. 4. Except that the photocurrent is a current signal, the other signals are voltage signals. Before time t6, the enable signal BLANK _ IN is asserted, the detection circuit operates normally according to the above-mentioned operating condition, and the operation sequence flow is as follows:
at the time of t0, the reset control signal ARM _ IN changes from low level to high level, the circuit enters a reset state, at this time, the gate control signals GP and GNI of the switching tubes MP and MN rise from low to high, the MP is turned off, the MN is turned on, and the potential of the APD _ IN point is reduced to low level under the pull-down action of the MN. At the time t1, the high level of the reset control signal ARM _ IN changes to the low level, the circuit reset is finished, and the state to be tested is kept from t1 to t 2.
The photocurrent comes at time t2, so that the potential of APD _ IN rises, the subsequent digital logic is triggered, GP changes from high level to low level, MP is started, and the circuit enters a quenching state. And the switch tube MP pulls up the APD _ IN point, so that the reverse bias voltage of the APD is reduced, and the Geiger mode is exited. At the same time, the detection circuit output signal STOP jumps from a low level to a high level, generating a state detection signal whose rising edge is active.
During t2 to t3, the APD is unable to detect the photocurrent. At time t3, the next high level of the reset signal ARM _ IN comes, and the above-described operation is repeated.
At time t6, the enable signal BLANK _ IN jumps from low level to high level, GP and GNI are locked to low level, the detection circuit has no response to the reset signal ARM _ IN and the photocurrent signal, and the STOP signal is continuously output to be high, so that the shielding function of a single pixel is realized.
Claims (1)
1. A maskable photocurrent detection circuit for GM-APD comprises a PMOS (P-channel metal oxide semiconductor) switching tube MP, an NMOS (N-channel metal oxide semiconductor) switching tube MN, an overcurrent protection module, an analog test tube MTESTP (maximum voltage drop out), a Level Shift module, a delay module and a digital logic module;
the PMOS switch tube MP and the NMOS switch tube MN are used for controlling the reverse bias voltage of two poles of the APD, so that the APD is controlled to work in a Geiger mode or quench avalanche photocurrent;
the overcurrent protection module comprises a first NMOS transistor NMOS1, a second NMOS transistor NMOS2, a third NMOS transistor NMOS3, a fourth NMOS transistor NMOS4, a first PMOS transistor PMOS1 and a fuse R0, and is used for limiting the voltage of an APD port within a safe voltage range;
the simulation test tube MTESTP is used for simulating the arrival effect of an optical signal when no laser echo signal exists;
the Level Shift module comprises a fifth NMOS transistor NMOS5 and a second PMOS transistor PMOS2, and is used for carrying out Level Shift on an input digital signal so as to be conveniently connected with the digital logic module;
the delay module comprises a first inverter INV1 and a second inverter INV2, and is used for delaying an input reset control signal ARM _ IN so as to facilitate the cascade connection and the array of the photocurrent detection circuit;
the digital logic module comprises a three-input AND-NOR gate AND _ NOR1, a three-input NOR gate NOR1, a third inverter INV3, a fourth inverter INV4 AND a fifth inverter INV5, AND is used for generating gate control signals of a PMOS (P-channel metal oxide semiconductor) switching tube MP AND an NMOS (N-channel metal oxide semiconductor) switching tube MN, so that the working mode of the APD AND the quenching of photocurrent are controlled, AND further a detection state signal is output;
the source of the PMOS switch MP is connected to the power supply voltage VDD, the gate is connected to the output end of the three-input AND-NOR gate AND _ NOR1 AND the gate of the NMOS3, the gate of the PMOS switch MP is simultaneously connected to the input end of the fifth inverter INV5, AND the drain of the PMOS switch MP is connected to the second input end a2 of the three-input AND-NOR gate AND _ NOR 1; the source electrode of the NMOS switch tube MN is grounded, the grid electrode of the NMOS switch tube MN is connected to the output end of the NOR1, the drain electrode of the NMOS switch tube MN is connected to the drain electrode of the PMOS switch tube MP, and the drain electrode of the NMOS switch tube MN is simultaneously connected with the drain electrode of the NMOS3 of the third NMOS tube; the PMOS switch tube MP and the NMOS switch tube MN jointly control the potential of the drain electrode of the PMOS switch tube MP so as to realize the control of the APD reverse bias voltage;
the source electrode of the first PMOS transistor PMOS1 is connected to the drain electrode of the PMOS switch transistor MP, the grid electrode is connected to the constant voltage bias VBP, and the drain electrode is connected with the drain electrode of the second NMOS transistor NMOS2 and the grid electrode of the first NMOS transistor NMOS 1; the source electrode of the second NMOS transistor NMOS2 is grounded, the grid electrode is connected to a constant voltage bias VBN, and the drain electrode is connected with the drain electrode of the first PMOS transistor PMOS1 and the grid electrode of the first NMOS transistor NMOS 1; the source electrode of the first NMOS tube NMOS1 is grounded, and the drain electrode is connected to the drain electrode of the PMOS switch tube MP; the source electrode of the third NMOS transistor NMOS3 is connected to the drain electrode of the fourth NMOS transistor NMOS4, the gate electrode of the third NMOS transistor NMOS3 is connected to the gate electrode of the PMOS switch transistor MP, and the drain electrode of the third NMOS transistor NMOS3 is connected to the drain electrode of the PMOS switch transistor MP; the source electrode of the NMOS4 of the fourth NMOS tube is grounded, and the grid electrode of the NMOS tube is connected with a constant voltage bias VBN; when overcurrent occurs, the first PMOS transistor PMOS1 and the second NMOS transistor NMOS2 provide gate bias voltage for the first NMOS transistor NMOS1 to enable the first NMOS transistor NMOS1 to be conducted, and large current is conducted to the ground;
the source electrode of the simulation test tube MTESTP is connected with a power supply VDD, the grid electrode is connected with an input signal TESTP, and the drain electrode is connected with the drain electrode of the PMOS switch tube MP;
the source electrode of the second PMOS tube PMOS2 is connected to a power supply VDD, the grid electrode is connected with a constant voltage bias VBP, the drain electrode is connected with the drain electrode of the fifth NMOS tube NMOS5, and the drain electrode of the second PMOS tube PMOS2 is simultaneously connected to the input of the third inverter INV 3; the source electrode of the fifth NMOS transistor NMOS5 is grounded, and the grid electrode is connected with an input enabling signal BLANK _ IN;
the input end of the first inverter INV1 is connected to the input reset control signal ARM _ IN, the output signal is connected to the input end of the second inverter INV2, the first input a1 of the three-input AND-NOR gate AND _ NOR1 AND the first input a1 of the three-input NOR gate NOR1 are simultaneously connected, AND the output signal of the second inverter INV2 is output to the next-stage pixel as the input reset control signal;
a first input end a1 of the three-input AND-NOR gate AND _ NOR1 is connected to the output end of the first inverter INV1 AND the first input end a1 of the three-input NOR gate NOR1, a second input end a2 of the three-input NOR gate NOR1 is connected to the drain of the PMOS switch tube MP, a third input end A3 of the three-input NOR gate NOR1 is connected to the output end of the third inverter INV3 AND the second input end a2 of the three-input NOR gate NOR1, AND an output end of the three-input AND-NOR gate AND _ NOR1 is connected to the gate of the PMOS switch tube MP, thereby controlling the working state of the PMOS switch tube MP; a first input end a1 of the three-input NOR gate NOR1 is connected with a first input end a1 of the three-input AND-NOR gate AND _ NOR1 AND an output end of the first inverter INV1, a second input end a2 of the three-input NOR gate NOR1 is connected to an output end of the third inverter INV3, a third input end A3 of the three-input NOR gate NOR1 is connected to an output of the fourth inverter INV4, AND an output end of the three-input NOR gate NOR1 is connected to a gate of the NMOS switching tube MN, so as to control an operating state of the NMOS switching tube MN; the input end of the third inverter INV3 is connected to the drain of the fifth NMOS transistor NMOS5, AND the output is sent to the third input end A3 of the three-input AND-NOR gate AND _ NOR 1; the input end of the fifth inverter INV5 is connected to the gate of the PMOS switch MP, and outputs the state detection signal STOP.
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| CN101789040A (en) * | 2010-01-27 | 2010-07-28 | 中国科学院上海技术物理研究所 | Design method of Geiger mode angular position digitizer (APD) passive quenching and recovering integrated circuit |
| US20160223397A1 (en) * | 2015-01-30 | 2016-08-04 | Industrial Technology Research Institute | System and method for controlling excess bias of single photon avalanche photo diode |
| CN105698826A (en) * | 2016-01-25 | 2016-06-22 | 天津大学 | Active quenching circuit used for APD detector in Geiger mode |
| CN107958944A (en) * | 2016-10-14 | 2018-04-24 | 意法半导体(R&D)有限公司 | Avalanche diode and its manufacture method |
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