CN113809990A - Radio frequency power amplifier and electronic equipment - Google Patents

Radio frequency power amplifier and electronic equipment Download PDF

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Publication number
CN113809990A
CN113809990A CN202111070536.7A CN202111070536A CN113809990A CN 113809990 A CN113809990 A CN 113809990A CN 202111070536 A CN202111070536 A CN 202111070536A CN 113809990 A CN113809990 A CN 113809990A
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CN
China
Prior art keywords
signal
radio frequency
sub
inverter
driving signal
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CN202111070536.7A
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Chinese (zh)
Inventor
刘瑞峰
罗素·莫恩
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Shanghai Orange Group Microelectronics Co ltd
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Shanghai Orange Group Microelectronics Co ltd
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Priority to CN202111070536.7A priority Critical patent/CN113809990A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Abstract

A radio frequency power amplifier and an electronic device, the radio frequency power amplifier includes: the drive amplification module is used for carrying out drive amplification on the radio frequency input signal and then outputting a drive signal; the radio frequency power amplification module comprises at least one signal generation unit and at least one output unit; the signal generating unit is connected to the output end of the driving amplifying module and used for outputting a first sub driving signal and a second sub driving signal according to the driving signal; the output unit is connected to the output end of the signal generation unit and used for outputting a radio frequency output signal according to the first sub-driving signal and the second sub-driving signal; the rising edge of the first sub-drive signal and the rising edge of the second sub-drive signal are at different moments; and/or the falling edge of the first sub-drive signal and the falling edge of the second sub-drive signal are at different time instants. The radio frequency power amplifier avoids the direct connection condition and reduces the power loss of the radio frequency power amplifier.

Description

Radio frequency power amplifier and electronic equipment
Technical Field
The present application relates to the field of electronic circuit technology, and in particular, to a radio frequency power amplifier and an electronic device.
Background
A power amplifier generally uses a plurality of transistors as output transistors, in which the sources of some of the transistors are connected to a power supply voltage, and the sources of the other transistors are grounded. If all transistors are turned on at the same time, a short circuit between the power supply and ground will be formed, which is called "shoot-through", which causes the power amplifier to generate a lot of heat and bring about high power loss.
As the frequency of the signal increases, such as when the input signal is a radio frequency signal, the power amplifier "shoot through" generates a large amount of heat and large power loss.
Disclosure of Invention
In view of this, the present application provides a radio frequency power amplifier and an electronic device, so as to solve the problems of the conventional power amplifier that a large amount of heat is generated and a large power loss is generated when the conventional power amplifier is in a "through" state.
The application provides a radio frequency power amplifier, includes: the drive amplification module is used for carrying out drive amplification on the radio frequency input signal and then outputting a drive signal; the radio frequency power amplification module comprises at least one signal generation unit and at least one output unit; the signal generating unit is connected to the output end of the driving amplifying module and used for outputting the first sub-driving signal and the second sub-driving signal according to the driving signal; the output unit is connected to the output end of the signal generating unit and used for outputting a radio frequency output signal according to the first sub-driving signal and the second sub-driving signal; the rising edge of the first sub-drive signal and the rising edge of the second sub-drive signal are at different times, and/or the falling edge of the first sub-drive signal and the falling edge of the second sub-drive signal are at different times.
Optionally, the signal generating unit includes a first signal buffering path and a second signal buffering path; the first signal buffer path is used for outputting a first sub-driving signal after a first preset time according to the driving signal, and the second signal buffer path is used for outputting a second sub-driving signal after a second preset time according to the driving signal; the first preset time is different from the second preset time so that the rising edge of the first sub-driving signal and the rising edge of the second sub-driving signal are at different moments;
and/or the falling edge of the first sub-drive signal and the falling edge of the second sub-drive signal are at different time instants.
Optionally, the first signal buffering path includes at least a first inverter and a second inverter, and the second signal buffering path includes at least a third inverter and a fourth inverter; the input end of the first inverter is used for inputting the driving signal, the output end of the first inverter is connected with the second inverter, and the output end of the second inverter is used for outputting the first sub-driving signal; the input end of the third phase inverter is used for inputting the driving signal, the output end of the third phase inverter is connected with the fourth phase inverter, and the output end of the fourth phase inverter is used for outputting the second sub-driving signal.
Optionally, the first inverter, the second inverter, the third inverter, and the fourth inverter each include at least one first PMOS transistor and at least one first NMOS transistor; the grid electrode of the first PMOS transistor is connected with the grid electrode of the first NMOS transistor, the drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor, the source electrode of the first PMOS transistor is connected with power supply voltage, and the source electrode of the first NMOS transistor is grounded; the drain electrode of the first PMOS transistor in the second inverter is used for outputting the first sub-driving signal, and the drain electrode of the first PMOS transistor in the fourth inverter is used for outputting the second sub-driving signal; the channel width-length ratios of the first PMOS transistor and the first NMOS transistor in the third inverter are both smaller than the channel width-length ratios of the first PMOS transistor and the first NMOS transistor in the first inverter, and the channel width-length ratios of the first PMOS transistor and the first NMOS transistor in the fourth inverter are both smaller than the channel width-length ratios of the first PMOS transistor and the first NMOS transistor in the second inverter.
Optionally, a ratio of a channel width-length ratio of a first PMOS transistor in the fourth inverter to a channel width-length ratio of a first NMOS transistor in the fourth inverter is a first ratio; the ratio of the channel width-length ratio of the first PMOS transistor in the second inverter to the channel width-length ratio of the first NMOS transistor in the second inverter is a second ratio; the first ratio is less than the second ratio.
Optionally, the radio frequency power amplifier includes a plurality of radio frequency power amplification modules, and the radio frequency power amplifier further includes at least one first gain control switch and a second gain control switch; one end of the first gain control switch is connected with the signal generating unit, the other end of the first gain control switch is connected with the ground, one end of the second gain control switch is connected with the signal generating unit, and the other end of the second gain control switch is connected with the power supply voltage; the radio frequency power amplifier is used for controlling the first gain control switch and the second gain control switch to be conducted according to a gain control signal so as to control the power of a radio frequency output signal output by the radio frequency power amplification module; the power of the radio frequency output signal of the radio frequency power amplifier is the sum of the powers of the radio frequency output signals output by all the radio frequency power amplification modules.
Optionally, the driving amplification module is further configured to adjust a voltage amplitude of the driving signal according to the duty ratio control signal; the radio frequency power amplification module is further used for controlling the duty ratio of the radio frequency output signal according to the voltage amplitude of the driving signal.
Optionally, the radio frequency power amplifier further includes a filtering module; the input end of the filtering module is connected with the output end of the output unit, and the output end of the filtering module is used for outputting the radio frequency output signal after filtering.
Optionally, the filtering module includes a 4 th-order LC ladder filter.
An electronic device comprising a radio frequency power amplifier as claimed in any preceding claim.
According to the radio frequency power amplifier, the signal generating unit outputs the first sub-driving signal and the second sub-driving signal to the output unit according to the driving signal output by the driving amplifying module, the rising edge of the first sub-driving signal and the rising edge of the second sub-driving signal are at different moments, and/or the falling edge of the first sub-driving signal and the falling edge of the second sub-driving signal are at different moments, so that the first sub-driving signal and the second sub-driving signal are prevented from being overlapped, when the output unit outputs the radio frequency output signal according to the first sub-driving signal and the second sub-driving signal, the output unit avoids the direct connection condition, a large amount of heat generated by the radio frequency power amplifier is avoided, and the power loss of the radio frequency power amplifier is reduced. And because the signal generating unit does not depend on a feedback technology, the signal generating unit can be suitable for high-frequency signals such as radio-frequency signals, and the accuracy of output data is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a radio frequency power amplifier according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a radio frequency power amplification module PAU according to an embodiment of the present invention;
fig. 3 is a circuit diagram of an rf power amplifying module PAU according to an embodiment of the present invention;
fig. 4 is a waveform diagram of the first sub-driving signal, the second sub-driving signal and the rf output signal according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Fig. 1 is a schematic structural diagram of a radio frequency power amplifier according to an embodiment of the invention.
The rf power amplifier PA of this embodiment includes a driving amplification module DA and an rf power amplification module PAU, and the number of the rf power amplification modules may be one or multiple. A radio frequency input signal PA _ in of the radio frequency power amplifier PA is input to a driving amplification module DA, and the driving amplification module DA is used for driving and amplifying the radio frequency input signal PA _ in and outputting a driving signal DA _ out; the driving signal da _ out is input to the rf power amplifying module PAU, and the rf power amplifying module PAU amplifies the driving signal da _ out to output an rf output signal pa _ out. The drive amplification module DA comprises a current control unit; the current control unit includes a plurality of switching devices, and the switching devices include: transistors and switching elements such as MOSFETs (metal-oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors) and BJTs (bipolar junction transistors), other switching devices may be selected in other embodiments.
Referring to fig. 2, a schematic structural diagram of a radio frequency power amplification module PAU according to an embodiment of the present invention is shown.
The radio frequency power amplification module PAU of this embodiment includes a signal generation unit 1 and an output unit 2, the number of the signal generation unit 1 and the output unit 2 may be multiple, and this embodiment takes one signal generation unit 1 and one output unit 2 for an exemplary description.
The signal generating unit 1 includes a signal generator, a transistor, and a switching element such as a MOSFET, an IGBT, and a BJT; the signal generating unit 1 is connected to an output end of the driving amplifying module DA, and outputs a first sub driving signal vp and a second sub driving signal vn according to the driving signal DA _ out. The signal generating unit 1 of the present embodiment includes a first signal buffer path 11 and a second signal buffer path 12; the first signal buffer path 11 is configured to output a first sub-driving signal vp after a first preset time according to a driving signal DA _ out output by the driving amplification module DA; the second signal buffer path 12 is configured to output a second sub-driving signal vn after a second preset time according to the driving signal DA _ out output by the driving amplification module DA; the first preset time is different from the second preset time. The first signal buffering path 11 and the second signal buffering path 12 include buffers, transistors, and switching elements such as MOSFETs. When the first signal buffering path 11 and the second signal buffering path 12 use different buffers, the first preset time and the second preset time may be different by setting different buffering times of the buffers, so that the rising edge or the falling edge of the first sub-driving signal vp and the second sub-driving signal vn are at different times. When the first signal buffer path 11 and the second signal buffer path 12 use transistors or switching elements, different signal conduction times or conduction speeds of the transistors or the switching elements can be set to realize that the rising edges or the falling edges of the output first sub-driving signal vp and the second sub-driving signal vn are at different moments. The rising edges or the falling edges of the first sub-driving signal vp and the second sub-driving signal vn are at different times, which means that the first sub-driving signal vp and the second sub-driving signal vn do not overlap at the same time, for example, when a first preset time corresponding to the first signal buffer path 11 and the second signal buffer path 12 is greater than a second preset time, the rising edge of the first sub-driving signal vp will be later than the rising edge of the second sub-driving signal vn, and when the first preset time is less than the second preset time, the rising edge of the first sub-driving signal vp will be earlier than the rising edge of the second sub-driving signal vn. The first and second sub driving signals vp and vn include rectangular waves, sine waves, sawtooth waves, and the like. In other embodiments, the first sub-drive signal vp and the second sub-drive signal vn may be provided by an external circuit to implement applications of various application scenarios.
The output unit 2 includes at least two transistors or switching elements such as MOSFETs, IGBTs or BJTs; the gate or the input terminal of the transistor or the switching element in the output unit 2 is connected to the output terminal of the signal generating unit 1, respectively, and outputs the rf output signal pa _ out according to the first sub-driving signal vp and the second sub-driving signal vn. Since the rising edge of the first sub-driving signal vp and the rising edge of the second sub-driving signal vn are at different times, and the falling edge of the first sub-driving signal vp and the falling edge of the second sub-driving signal vn are at different times, that is, the first sub-driving signal vp and the second sub-driving signal vn are not overlapped, and the first sub-driving signal vp and the second sub-driving signal vn are used for driving different transistors or switching units in the output unit 2, different transistors or switching elements in the output unit 2 are not turned on at the same time, thereby avoiding the occurrence of the shoot-through condition, avoiding a large amount of heat generated by the rf power amplifier PA, and reducing the power loss of the rf power amplifier PA. In some other embodiments, the rising edge of the first sub-driving signal vp and the rising edge of the second sub-driving signal vn may be maintained at different times, or the falling edge of the first sub-driving signal vp and the falling edge of the second sub-driving signal vn may be maintained at different times, so that the transistor or the switching element in the output unit 2 is turned on when the signal rising edge or the signal falling edge is different, and a shoot-through condition of the transistor or the switching element in the output unit 2 at the signal rising edge or the signal falling edge is avoided.
Referring to fig. 3, a circuit diagram of an rf power amplifying module PAU according to an embodiment of the invention is shown.
In the rf power amplifying module PAU of this embodiment, the first signal buffering path 11 includes a first inverter 21 and a second inverter 22, the second signal buffering path 12 includes a third inverter 23 and a fourth inverter 24, an input end of the first inverter 21 is configured to input the driving signal DA _ out of the driving amplifying module DA, an output end of the first inverter 21 is connected to the second inverter 22, and an output end of the second inverter 22 is configured to output the first sub-driving signal vp; the input end of the third inverter 23 is configured to input the driving signal DA _ out of the driving amplification module DA, the output end is connected to the fourth inverter 24, and the output end of the fourth inverter 24 is configured to output the second sub-driving signal vn. The output unit 2 comprises an output transistor 25, and an input terminal of the output transistor 25 is used for inputting the first sub-drive signal vp and the second sub-drive signal vn.
The radio frequency power amplifier PA further comprises a first gain control switch 26 and a second gain control switch 27. The rf power amplifier PA is configured to control the first gain control switch 26 and the second gain control switch 27 to be turned on according to a gain control signal GC < i >, so as to control the gain of the rf output signal PA _ out output by the rf power amplification module PAU. The radio frequency power amplifier PA includes at least one radio frequency power amplification module PAU, and when the number of the radio frequency power amplification modules PAU is multiple, the power of the radio frequency output signal PA _ out of the radio frequency power amplifier PA is the sum of the powers of the radio frequency output signals of all the radio frequency power amplification modules PAU. The radio frequency output signal PA _ out of the radio frequency power amplifier PA is equal to the sum of the superposition of the radio frequency output signals output by all the radio frequency power amplification modules PAU.
The first inverter 21 includes a first PMOS transistor PMP1 and a first NMOS transistor NMP1, the second inverter 22 includes a second PMOS transistor PMP2 and a second NMOS transistor NMP2, the third inverter 23 includes a third PMOS transistor PMN1 and a third NMOS transistor NMN1, the fourth inverter 24 includes a fourth PMOS transistor PMN2 and a fourth NMOS transistor NMN2, and the output transistor 25 includes a fifth PMOS transistor PM and a fifth NMOS transistor NM. The first gain control switch 26 includes a fourth gain switch sw4, a fifth gain switch sw5 and a sixth gain switch sw6, the second gain control switch 27 includes a first gain switch sw1, a second gain switch sw2 and a third gain switch sw3, and the first gain switch sw1, the second gain switch sw2, the third gain switch sw3, the fourth gain switch sw4, the fifth gain switch sw5 and the sixth gain switch sw6 are controlled by a gain control signal GC < i >. PMP1, PMP2, PMN1 and PMN2 are first PMOS transistors included in each inverter, and NMP1, NMP2, NMN1 and NMN2 are first NMOS transistors included in each inverter.
The gate of the first PMOS transistor PMP1 is connected to the driving signal da _ out, the source is connected to the power supply voltage, the drain is connected to one end of a fourth gain switch sw4, the other end of the fourth gain switch sw4 is connected to one end of a sixth gain switch sw6, the other end of the sixth gain switch sw6 is connected to ground, one end of a fifth gain switch sw5 is connected to the drain of the first NMOS transistor NMP1, the other end of the fifth gain switch sw5 is connected to one end of the sixth gain switch sw6, and the gate of the first NMOS transistor NMP1 is connected to the driving signal da _ out and the source is connected to ground. A gate of the second PMOS transistor PMP2 is connected to one end of the sixth gain switch sw6, a source thereof is connected to a power supply voltage, a drain thereof is connected to a drain of the second NMOS transistor NMP2, a gate of the second NMOS transistor NMP2 is connected to one end of the sixth gain switch sw6, and a source thereof is grounded; the gate of the third PMOS transistor PMN1 is connected to the driving signal da _ out, the source is connected to a power supply voltage, the drain is connected to one end of a first gain switch sw1, the other end of the first gain switch sw1 is connected to one end of a third gain switch sw3, the other end of the third gain switch sw3 is connected to the power supply voltage, one end of a second gain switch sw2 is connected to the drain of the third NMOS transistor NMN1, the other end of the second gain switch sw2 is connected to one end of the third gain switch sw3, and the gate of the third NMOS transistor NMN1 is connected to the driving signal da _ out and the source is grounded; a gate of the fourth PMOS transistor PMN2 is connected to one end of the third gain switch sw3, a source thereof is connected to a power supply voltage, a drain thereof is connected to a drain of the fourth NMOS transistor NMN2, a gate of the fourth NMOS transistor NMN2 is connected to one end of the third gain switch sw3, and a source thereof is grounded; the gate of the fifth PMOS transistor PM is connected to the drain of the second PMOS transistor PMP2, the source is connected to the power supply voltage, the drain is connected to the drain of the fifth NMOS transistor NM, the gate of the fifth NMOS transistor NM is connected to the drain of the fourth PMOS transistor PMN2, the source is grounded, and the drain of the fifth NMOS transistor NM is used for outputting the rf output signal PA _ out of the rf power amplifier PA. The drain of the second PMOS transistor PMP2 is for outputting a first sub-driving signal vp, and the drain of the fourth PMOS transistor PMN2 is for outputting a second sub-driving signal vn. The channel width to length ratios of the third PMOS transistor PMN1 and the third NMOS transistor NMN1 are each smaller than the channel width to length ratios of the first PMOS transistor PMP1 and the first NMOS transistor NMP1, and the channel width to length ratios of the fourth PMOS transistor PMN2 and the fourth NMOS transistor NMN2 are each smaller than the channel width to length ratios of the second PMOS transistor PMP2 and the second NMOS transistor NMP2, so that the drive capacities of the third PMOS transistor PMN1 and the third NMOS transistor NMN1 are smaller than the drive capacities of the first PMOS transistor PMP1 and the first NMOS transistor NMP1, and the drive capacities of the fourth PMOS transistor PMN2 and the fourth NMOS transistor NMN2 are smaller than the drive capacities of the second PMOS transistor PMP2 and the second NMOS transistor NMP 2; therefore, the delay of the driving signal da _ out to the second sub-driving signal vn is greater than the delay of the driving signal da _ out to the first sub-driving signal vp, that is, the rising edge of the second sub-driving signal vn of the fifth NMOS transistor NM is later than the rising edge of the first sub-driving signal vp of the fifth PMOS transistor PM, it is possible to prevent the gate driving signals of the fifth PMOS transistor PM and the fifth NMOS transistor NM from "through" at the time of the rising edge, and to reduce the heat and power loss of the power amplifier PA.
In the radio frequency power amplifier in the scheme, the signal generating unit outputs the first sub-driving signal and the second sub-driving signal, the first sub-driving signal and the second sub-driving signal do not depend on feedback, the frequency of the signal is not limited, and the radio frequency power amplifier can respond to the radio frequency signal.
Further, the dynamic gain adjustment of the radio frequency power amplification module PAU can be realized through the first gain control switch 26, the second gain control switch 27 and the gain control signal GC < i >, so as to further expand the application scenarios.
To further reduce the heat and power consumption of the rf power amplifier PA, the channel width to length ratio S of the fourth PMOS transistor PMN2PMN2Channel width to length ratio S of fourth NMOS transistor NMN2NMN2The ratio of (a) to (b) is a first width-to-length ratio; channel width and length S of second PMOS transistor PMP2PMP2The channel width to length ratio S of the second NMOS transistor NMP2NMP2The ratio of (a) to (b) is a second width-to-length ratio; the first width-to-length ratio is smaller than the second width-to-length ratio, so that the falling edge of the second sub-drive signal vn of the fifth NMOS transistor NM is earlier than the falling edge of the first sub-drive signal vp of the fifth PMOS transistor PM, so that the signal vn is narrower than the signal vp, and the gate drive voltages of the output transistors of the output sub-unit 25 do not overlap, thereby further reducing the heat and power loss of the power amplifier PA.
The working principle of the circuit in fig. 3 is as follows: when the gain control signal GC<i>When 0 (i is 0. ltoreq. n),the first gain switch sw1, the second gain switch sw2, the fourth gain switch sw4 and the fifth gain switch sw5 are turned off, the sixth gain switch sw6 and the third gain switch sw3 are turned on, the first gate signal vp1 is connected to the ground, the second gate signal vn1 is connected to the power supply voltage, the first sub-driving signal vp of the fifth PMOS transistor PM is pulled up to the power supply, the second sub-driving signal vn of the fifth NMOS transistor NM is pulled to the ground, the fifth PMOS transistor PM and the fifth NMOS transistor NM are both turned off, and at this time, the radio frequency power amplification module PAU does not operate. When the gain control signal GC<i>When the input signal is 1 (i is more than or equal to 0 and less than or equal to n), the circuit normally works, the first gain switch sw1, the second gain switch sw2, the fourth gain switch sw4 and the fifth gain switch sw5 are turned on, the sixth gain switch sw6 and the third gain switch sw3 are turned off, the first gate signal vp1 is connected with the output end of the first inverter 21, the second gate signal vn1 is connected with the output end of the third inverter 23, the fifth PMOS transistor PM and the fifth NMOS transistor NM are both normally turned on, the radio frequency power amplification module PAU normally works, and radio frequency power amplification of the input signal can be achieved. Since the driving capability of the third PMOS transistor PMN1, the third NMOS transistor NMN1, the fourth PMOS transistor PMN2, the fourth NMOS transistor NMN2 is designed to be weaker than the driving capability of the first PMOS transistor PMP1, the first NMOS transistor NMP1, the second PMOS transistor PMP2, the second NMOS transistor NMP2, the delay of the driving signal da _ out to the second sub-driving signal vn of the fifth NMOS transistor NM is greater than the delay of the driving signal da _ out to the first sub-driving signal vp of the fifth PMOS transistor PM, so that the driving signal vp reaches the gate of the fifth PMOS transistor PM earlier. And due to SPMN2And SNMN2The ratio of is less than SPMP2And SNMP2In this case, the second sub-driving signal vn of the fifth NMOS transistor NM is narrower than the first sub-driving signal vp of the fifth PMOS transistor PM. Therefore, the grid driving signals of the fifth PMOS transistor PM and the fifth NMOS transistor NM of the output transistor are not overlapped, the 'through' phenomenon is avoided, the heat and the power loss generated by the radio frequency power amplifier are reduced, the circuit does not depend on feedback, and a higher frequency range can be applied.
Referring to fig. 4, waveforms of the first sub-driving signal, the second sub-driving signal and the rf output signal of the present embodiment are shown.
The first and second sub-drive signals vp and vn are approximately sinusoidal, the channel width-to-length ratios of the third PMOS transistor PMN1 and the third NMOS transistor NMN1 are both smaller than the channel width-to-length ratios of the first PMOS transistor PMP1 and the first NMOS transistor NMP1, the channel width-to-length ratios of the fourth PMOS transistor PMN2 and the fourth NMOS transistor NMN2 are both smaller than the channel width-to-length ratios of the second PMOS transistor PMP2 and the second NMOS transistor NMP2, and the channel width-to-length ratio S of the fourth PMOS transistor PMN2 is smaller than the channel width-to-length ratio SPMN2Channel width to length ratio S of fourth NMOS transistor NMN2NMN2The ratio of (a) to (b) is a first width-to-length ratio; channel width and length S of second PMOS transistor PMP2PMP2The channel width to length ratio S of the second NMOS transistor NMP2NMP2The ratio of (a) to (b) is a second width-to-length ratio; the first width-to-length ratio is smaller than the second width-to-length ratio, the first sub-drive signal vp is earlier than the second sub-drive signal vn when rising, the first sub-drive signal vp is later than the second sub-drive signal vn when falling, namely, the sine waveform of the second sub-drive signal vn is entirely narrower than the sine waveform of the first sub-drive signal vp, namely, the first sub-drive signal vp and the second sub-drive signal vn are not overlapped, the fifth PMOS transistor PM and the fifth NMOS transistor NM are not in a through state, so that the radio-frequency power amplifier PA is prevented from generating a large amount of heat and power loss, and the radio-frequency output signal paout _ of the radio-frequency power amplifier PA is prevented from generating loss.
The radio frequency power amplifier of the embodiment can avoid the direct connection condition and avoid the radio frequency power amplifier from generating a large amount of heat and power loss. In order to further reduce the harmonic level of the radio frequency power amplifier, the following technical solutions are proposed.
In the radio frequency power amplifier PA of this embodiment, the driving amplification module DA is connected to the radio frequency power amplification module PAU, the driving amplification module DA can control the voltage amplitude of the driving signal DA _ out output by the driving amplification module DA according to the duty cycle control signal, and the radio frequency power amplification module PAU can control the duty cycle of the radio frequency output signal of the radio frequency power amplifier PA according to the voltage amplitude of the driving signal, that is, the duty cycle of the radio frequency output signal of the radio frequency power amplifier PA can be controlled by the duty cycle control signal, so as to achieve suppression of the harmonic level of the power amplifier by adjusting the duty cycle of the output signal of the radio frequency power amplifier PA, so that the radio frequency power amplifier PA meets the relevant regulations about harmonics, the harmonic suppression mode is simple and controllable, and compared with a method of suppressing harmonics by using a filter device, fewer components are used, and the cost is lower, the harmonic suppression effect is better.
The embodiment of the invention also provides a radio frequency power amplifier, which further comprises a filtering module; the input end of the filtering module is connected with the output end of the output unit, and the output end of the filtering module is used for outputting the radio frequency output signal after filtering. Specifically, the output end of the radio frequency power amplifier is connected with an LPF (low pass filter), the LPF is a 4-order LC (inductance-capacitance) ladder filter, the passband is in a range of 2.4-2.5GHz (gigahertz), and second harmonic attenuation of 30dB (decibel) and third harmonic attenuation of 46dB are provided. The LPF comprises a first inductor, a second inductor, a first capacitor and a second capacitor, wherein one end of the first inductor is connected with an output signal of the power amplifier PA, the other end of the first inductor is connected with one end of the second inductor and one end of the first capacitor respectively, the other end of the second inductor is connected with one end of the second capacitor and is used for being connected with an external load, and the other ends of the first capacitor and the second capacitor are grounded. Harmonics can be further suppressed by connecting an LPF in series between the rf power amplifier PA and the external load, and the LPF can also perform impedance matching to convert the load impedance into the impedance required by the power amplifier PA, for example, the impedance required by the power amplifier PA is 10 ohms, and the load impedance can be converted into 10 ohms by the LPF to improve the efficiency of the rf power amplifier PA.
The embodiment of the invention also provides electronic equipment comprising the radio frequency power amplifier, such as a mobile phone, a tablet computer, a power amplifier and the like. By the radio frequency power amplifier, harmonic waves and power consumption of the electronic equipment can be reduced, so that the radio frequency power amplifier meets relevant regulations of the regulations on harmonic waves.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. A radio frequency power amplifier, comprising:
the drive amplification module is used for carrying out drive amplification on the radio frequency input signal and then outputting a drive signal;
the radio frequency power amplification module comprises at least one signal generation unit and at least one output unit;
the signal generating unit is connected to the output end of the driving amplifying module and used for outputting a first sub driving signal and a second sub driving signal according to the driving signal;
the output unit is connected to the output end of the signal generating unit and used for outputting a radio frequency output signal according to the first sub-driving signal and the second sub-driving signal;
the rising edge of the first sub-drive signal and the rising edge of the second sub-drive signal are at different moments in time;
and/or the falling edge of the first sub-drive signal and the falling edge of the second sub-drive signal are at different time instants.
2. The radio frequency power amplifier of claim 1, wherein the signal generating unit includes a first signal buffering path and a second signal buffering path; the first signal buffer path is used for outputting a first sub-driving signal after a first preset time according to the driving signal, and the second signal buffer path is used for outputting a second sub-driving signal after a second preset time according to the driving signal; the first preset time is different from the second preset time so that the rising edge of the first sub-driving signal and the rising edge of the second sub-driving signal are at different moments;
and/or the falling edge of the first sub-drive signal and the falling edge of the second sub-drive signal are at different time instants.
3. The radio frequency power amplifier of claim 2, wherein the first signal buffering path includes at least a first inverter and a second inverter, and the second signal buffering path includes at least a third inverter and a fourth inverter; the input end of the first inverter is used for inputting the driving signal, the output end of the first inverter is connected with the second inverter, and the output end of the second inverter is used for outputting the first sub-driving signal; the input end of the third phase inverter is used for inputting the driving signal, the output end of the third phase inverter is connected with the fourth phase inverter, and the output end of the fourth phase inverter is used for outputting the second sub-driving signal.
4. The radio frequency power amplifier of claim 3, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise at least a first PMOS transistor and at least a first NMOS transistor; the grid electrode of the first PMOS transistor is connected with the grid electrode of the first NMOS transistor, the drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor, the source electrode of the first PMOS transistor is connected with power supply voltage, and the source electrode of the first NMOS transistor is grounded; the drain electrode of the first PMOS transistor in the second inverter is used for outputting the first sub-driving signal, and the drain electrode of the first PMOS transistor in the fourth inverter is used for outputting the second sub-driving signal; the channel width-length ratios of the first PMOS transistor and the first NMOS transistor in the third inverter are both smaller than the channel width-length ratios of the first PMOS transistor and the first NMOS transistor in the first inverter, and the channel width-length ratios of the first PMOS transistor and the first NMOS transistor in the fourth inverter are both smaller than the channel width-length ratios of the first PMOS transistor and the first NMOS transistor in the second inverter.
5. The radio frequency power amplifier of claim 4, wherein a ratio of a channel width to length ratio of the first PMOS transistor in the fourth inverter to a channel width to length ratio of the first NMOS transistor in the fourth inverter is a first ratio; the ratio of the channel width-length ratio of the first PMOS transistor in the second inverter to the channel width-length ratio of the first NMOS transistor in the second inverter is a second ratio; the first ratio is less than the second ratio.
6. The rf power amplifier of claim 1, wherein the rf power amplifier includes a plurality of the rf power amplification modules, the rf power amplifier further including at least a first gain control switch and a second gain control switch; one end of the first gain control switch is connected with the signal generating unit, the other end of the first gain control switch is connected with the ground, one end of the second gain control switch is connected with the signal generating unit, and the other end of the second gain control switch is connected with the power supply voltage; the radio frequency power amplifier is used for controlling the first gain control switch and the second gain control switch to be conducted according to a gain control signal so as to control the power of a radio frequency output signal output by the radio frequency power amplification module; the power of the radio frequency output signal of the radio frequency power amplifier is the sum of the powers of the radio frequency output signals output by all the radio frequency power amplification modules.
7. The radio frequency power amplifier of claim 1, wherein the drive amplification module is further configured to adjust a voltage amplitude of the drive signal according to a duty cycle control signal; the radio frequency power amplification module is further used for controlling the duty ratio of the radio frequency output signal according to the voltage amplitude of the driving signal.
8. The radio frequency power amplifier of any of claims 1-7, wherein the radio frequency power amplifier further comprises a filtering module;
the input end of the filtering module is connected with the output end of the output unit, and the output end of the filtering module is used for outputting the radio frequency output signal after filtering.
9. The radio frequency power amplifier of claim 8, wherein the filtering module comprises a 4 th order LC ladder filter.
10. An electronic device comprising a radio frequency power amplifier according to any one of claims 1-9.
CN202111070536.7A 2021-09-13 2021-09-13 Radio frequency power amplifier and electronic equipment Pending CN113809990A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6285230B1 (en) * 1999-04-07 2001-09-04 Hyundai Electronics Industries Co., Ltd. Input buffer circuit with adjustable delay via an external power voltage
CN102487240A (en) * 2010-12-01 2012-06-06 中芯国际集成电路制造(上海)有限公司 Control circuit of voltage switching rate and output circuit
CN102594272A (en) * 2010-02-26 2012-07-18 比亚迪股份有限公司 Circuit for reducing electromagnetic interference of class-D audio-frequency power amplifier
CN205725660U (en) * 2016-03-31 2016-11-23 大唐恩智浦半导体有限公司 Power driving circuit
US20190229684A1 (en) * 2018-01-19 2019-07-25 Silicon Laboratories Inc. System and method for reducing output harmonics
US20200112251A1 (en) * 2018-10-09 2020-04-09 Stmicroelectronics (Rousset) Sas Control of a power stage of a switched-mode power supply

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6285230B1 (en) * 1999-04-07 2001-09-04 Hyundai Electronics Industries Co., Ltd. Input buffer circuit with adjustable delay via an external power voltage
CN102594272A (en) * 2010-02-26 2012-07-18 比亚迪股份有限公司 Circuit for reducing electromagnetic interference of class-D audio-frequency power amplifier
CN102487240A (en) * 2010-12-01 2012-06-06 中芯国际集成电路制造(上海)有限公司 Control circuit of voltage switching rate and output circuit
CN205725660U (en) * 2016-03-31 2016-11-23 大唐恩智浦半导体有限公司 Power driving circuit
US20190229684A1 (en) * 2018-01-19 2019-07-25 Silicon Laboratories Inc. System and method for reducing output harmonics
US20200112251A1 (en) * 2018-10-09 2020-04-09 Stmicroelectronics (Rousset) Sas Control of a power stage of a switched-mode power supply

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