CN113809206A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN113809206A
CN113809206A CN202010534238.8A CN202010534238A CN113809206A CN 113809206 A CN113809206 A CN 113809206A CN 202010534238 A CN202010534238 A CN 202010534238A CN 113809206 A CN113809206 A CN 113809206A
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CN
China
Prior art keywords
buffer layer
layer
mask layer
dbr
dbr structure
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Pending
Application number
CN202010534238.8A
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Chinese (zh)
Inventor
朱丹丹
程凯
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Enkris Semiconductor Inc
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Enkris Semiconductor Inc
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Priority to CN202010534238.8A priority Critical patent/CN113809206A/en
Priority to PCT/CN2020/111004 priority patent/WO2021248693A1/en
Priority to TW110121052A priority patent/TWI834041B/en
Publication of CN113809206A publication Critical patent/CN113809206A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
    • H01S5/18363—Structure of the reflectors, e.g. hybrid mirrors comprising air layers
    • H01S5/18366—Membrane DBR, i.e. a movable DBR on top of the VCSEL
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
    • H01S5/187—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL] using Bragg reflection

Abstract

The application provides a semiconductor structure and a preparation method thereof, wherein the preparation method of the semiconductor structure comprises the following steps: preparing a buffer layer on a substrate; preparing a mask layer on the buffer layer; patterning the mask layer to expose part of the buffer layer; preparing a first DBR structure at the part of the buffer layer exposed by the mask layer; and preparing a light-emitting structure on the first DBR structure. The patterned mask layer can improve the growth quality of the first DBR structure and is beneficial to the preparation of a subsequent light-emitting structure.

Description

Semiconductor structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
The wide band gap semiconductor material III group nitride as a typical representative of the third generation semiconductor material has the excellent characteristics of large band gap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity and easy formation of a high-quality heterostructure, and is very suitable for manufacturing high-temperature, high-frequency and high-power electronic devices.
A GaN-based cavity light emitting device including a cavity light emitting diode and a vcsel generally employs a Distributed Bragg Reflector (DBR) structure, and a stress generated by a lattice mismatch in a first DBR structure of al (ga) N/GaN may cause a crack or the like.
Disclosure of Invention
The application provides a preparation method of a semiconductor structure, which comprises the following steps: preparing a buffer layer on a substrate; preparing a mask layer on the buffer layer; patterning the mask layer to expose part of the buffer layer; preparing a first DBR structure at the part of the buffer layer exposed by the mask layer; preparing a light emitting structure on the first DBR structure; and fabricating a second DBR structure on the light emitting structure. Through the patterned mask layer, a high-quality first DBR structure can be grown. In addition, the existence of the mask layer is also beneficial to the selective preparation of the subsequent light-emitting structure on the first DBR structure.
Optionally, after patterning the mask layer to expose a portion of the buffer layer, the buffer layer exposed by the mask layer is partially etched to form a groove in the buffer layer, and then a first DBR structure is prepared on the portion of the buffer layer exposed by the mask layer. By continuing to etch the buffer layer, a thicker first DBR structure can be fabricated, thereby increasing its reflectivity.
Optionally, after forming the groove in the buffer layer, a mask layer is first prepared on the sidewall of the groove, and then the first DBR structure is prepared on the portion of the buffer layer exposed by the mask layer. The mask layer can well protect the side wall of the groove, and parasitic growth of the side wall of the groove is prevented when the first DBR structure is prepared subsequently.
Optionally, the substrate comprises silicon, sapphire, gallium nitride, silicon carbide.
Optionally, the mask layer includes silicon oxide and silicon nitride.
Optionally, the buffer layer, the first DBR structure, the light emitting structure comprise a group iii nitride material.
The present application provides a semiconductor structure comprising: a substrate; a buffer layer on the substrate; the graphical mask layer is positioned on the buffer layer; the first DBR structure is positioned on the buffer layer and between the mask layers; a light emitting structure located over the first DBR structure; and a second DBR structure located above the second DBR structure.
Optionally, the first DBR structure extends into the buffer layer.
Optionally, a mask layer is disposed between the portion of the first DBR structure extending to the buffer layer and the buffer layer.
Drawings
Fig. 1 a-1 f are schematic diagrams of a semiconductor structure according to a first embodiment of the present application.
Fig. 2 a-2 c are schematic diagrams of a semiconductor structure according to a second embodiment of the present application.
Fig. 3a-3b are schematic diagrams of a semiconductor structure according to a second embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance. In the description of the embodiments of the present invention, it will be understood that: when a layer (or film), a region, a pattern, or a structure is referred to as being "on" or "under" another substrate, another layer (or film), another region, another pad, or another pattern, it can be "directly" or "indirectly" on the other substrate, layer (or film), region, pad, or pattern, or one or more intervening layers may also be present. Such positions of the layers have been described with reference to the drawings. The thickness and size of each layer shown in the drawings may be exaggerated, omitted, or schematically drawn for convenience or clarity. In addition, the size of the element does not completely reflect the actual size.
Fig. 1a to 1e show a process flow of a method for manufacturing a semiconductor structure according to a first embodiment of the present application.
Step S1, referring to fig. 1a, a buffer layer 110 is prepared on a substrate 100.
The substrate 100 includes silicon, sapphire, gallium nitride, silicon carbide, and the like, and the type of material of the substrate 100 is not particularly limited in the present application. The buffer layer 110 includes a group iii nitride material, such as GaN, AlGaN, or the like.
In step S2, referring to fig. 1b, a mask layer 120 is prepared on the buffer layer 110.
The mask layer 130 includes silicon oxide, silicon nitride, or the like.
In step S3, referring to fig. 1c, the mask layer 120 is patterned to partially expose the buffer layer 110.
In step S4, referring to fig. 1d, a first DBR structure 130 is prepared on the exposed buffer layer 110. Preferably, the height of the first DBR structure 130 does not exceed the height of the mask layer 120.
The first DBR structure includes a periodic structure of alternating group III nitride materials, such as GaN and AlGaN.
In step S5, referring to fig. 1e, the light emitting structure 140 is prepared on the first DBR structure 130. The light emitting structure 140 includes a first doping layer 141, a quantum well layer 142, and a second doping layer 143. The first doping layer 141 of the light emitting structure 140 may be, for example, n-type doped, and the second doping layer 143 may be, for example, p-type doped.
Step S6, referring to fig. 1f, continues to grow the second DBR structure 150 in the light emitting structure 140.
The second DBR structure 150 includes a periodic structure of alternating group III nitride materials, such as GaN and AlGaN, and may also include a dielectric material, such as Ta2O5/SiO2AlternatingAnd forming a periodic structure.
Through the patterned mask layer 120, the first DBR structure is selectively grown, which can release pressure well and grow a high-quality first DBR structure. In addition, the presence of the mask layer 120 facilitates the selective preparation of the subsequent light emitting structure 140 on the first DBR structure 130.
In the second embodiment of the present application, as shown in fig. 2a, after step S3, the buffer layer 110 exposed by the mask layer 120 is partially etched, and a groove 111 is formed in the buffer layer 110; then, as shown in fig. 2b and 2c, a first DBR structure 130 is prepared on the exposed buffer layer 110; preparing a light emitting structure 140 on the first DBR structure 130; a second DBR structure 150 is fabricated on the light emitting structure 140. By continuing to etch the buffer layer, a thicker first DBR structure can be fabricated, thereby increasing its reflectivity.
In a third embodiment of the present application, as shown in fig. 3a to 3b, the buffer layer 110 exposed by the mask layer 120 is partially etched in the second embodiment, and after the groove 111 is formed in the buffer layer 110, the mask layer is prepared, so that the mask layer 120 covers the sidewall of the groove 111, and the buffer layer 110 at the bottom of the groove 111 is exposed. The mask layer can well protect the side wall of the groove 111, and parasitic growth of the side wall of the groove 111 is prevented when the first DBR structure is prepared subsequently.
In an embodiment of the present application, a semiconductor structure is further disclosed, as shown in fig. 1e, the semiconductor structure includes a substrate 100, a buffer layer 110 on the substrate 100, a mask layer 130 patterned on the buffer layer 110, first DBR structures 130 on the buffer layer 110 and between the mask layers 130, a light emitting structure 140 on the first DBR structure 130, and a second DBR structure 150 on the light emitting structure 140. The light emitting structure 140 includes a first doping layer 141, a quantum well layer 142, and a second doping layer 143. Preferably, the height of the first DBR structure 130 does not exceed the height of the mask layer 120.
Through the patterned mask layer 120, a high quality first DBR structure may be grown. In addition, the presence of the mask layer 120 facilitates the selective preparation of the subsequent light emitting structure 140 on the first DBR structure 130.
The substrate 100 includes silicon, sapphire, gallium nitride, silicon carbide, and the like, and the type of material of the substrate 100 is not particularly limited in the present application. The buffer layer 110 includes a group iii nitride material, such as GaN, AlGaN, or the like. The first DBR structure includes a periodic structure of alternating group III nitride materials, such as GaN and AlGaN. The second DBR structure 150 includes a periodic structure of alternating group III nitride materials, such as GaN and AlGaN, and may also include a dielectric material, such as Ta2O5/SiO2Alternately formed periodic structures.
In another embodiment of the present application, as shown in fig. 2c, in the semiconductor structure, the first DBR structure 130 extends into the buffer layer 130. By continuing to etch the buffer layer, a thicker first DBR structure can be fabricated, thereby increasing its reflectivity.
In yet another embodiment of the present application, as shown in fig. 3b, in the semiconductor structure, a mask layer 120 is disposed between a portion of the first DBR structure 130 extending to the buffer layer 110 and the buffer layer 110. The mask layer can well protect the side wall of the groove 111, and parasitic growth of the side wall of the groove 111 is prevented when the first DBR structure is prepared subsequently.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (9)

1. A method for fabricating a semiconductor structure, comprising:
preparing a buffer layer on a substrate;
preparing a mask layer on the buffer layer;
patterning the mask layer to expose part of the buffer layer;
preparing a first DBR structure at the part of the buffer layer exposed by the mask layer;
preparing a light emitting structure on the first DBR structure; and
a second DBR structure is prepared on the light emitting structure.
2. The method of claim 1, wherein after patterning the mask layer to partially expose the buffer layer, the buffer layer exposed by the mask layer is partially etched to form a recess in the buffer layer, and then the first DBR structure is formed on the portion of the buffer layer exposed by the mask layer.
3. The method of claim 2, wherein after forming the recess in the buffer layer, a mask layer is formed on sidewalls of the recess, and then the first DBR structure is formed on a portion of the buffer layer exposed by the mask layer.
4. The method of claim 1, wherein the substrate comprises silicon, sapphire, gallium nitride, or silicon carbide.
5. The method of claim 1, wherein the mask layer comprises silicon oxide or silicon nitride.
6. The method of claim 1, wherein the buffer layer, the first DBR structure, and the light emitting structure comprise a group III nitride material, and the second DBR structure comprises a group III nitride material, a dielectric material.
7. A semiconductor structure, comprising:
a substrate;
a buffer layer on the substrate;
the graphical mask layer is positioned on the buffer layer;
the first DBR structure is positioned on the buffer layer and between the mask layers; and
a light emitting structure located over the first DBR structure.
8. The semiconductor structure of claim 7, wherein: the first DBR structure extends into the buffer layer.
9. The semiconductor structure of claim 8, wherein: a mask layer is arranged between the part of the first DBR structure extending to the buffer layer and the buffer layer.
CN202010534238.8A 2020-06-11 2020-06-11 Semiconductor structure and preparation method thereof Pending CN113809206A (en)

Priority Applications (3)

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CN202010534238.8A CN113809206A (en) 2020-06-11 2020-06-11 Semiconductor structure and preparation method thereof
PCT/CN2020/111004 WO2021248693A1 (en) 2020-06-11 2020-08-25 Semiconductor structure and preparation method therefor
TW110121052A TWI834041B (en) 2020-06-11 2021-06-09 Semiconductor structures and preparation methods thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010534238.8A CN113809206A (en) 2020-06-11 2020-06-11 Semiconductor structure and preparation method thereof

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273367A (en) * 1994-04-01 1995-10-20 Mitsubishi Cable Ind Ltd Manufacture of semiconductor substrate and light-emitting device
US20090278165A1 (en) * 2008-05-09 2009-11-12 National Chiao Tung University Light emitting device and fabrication method therefor
CN101621109A (en) * 2008-07-02 2010-01-06 台湾积体电路制造股份有限公司 Semiconductor structure and light-emitting diode
US20140377459A1 (en) * 2013-06-19 2014-12-25 Canon Kabushiki Kaisha Semiconductor dbr, semiconductor light-emitting device, solid-state laser, photoacoustic apparatus, image-forming apparatus, and method for manufacturing semiconductor dbr
US20170117437A1 (en) * 2015-10-23 2017-04-27 Sensor Electronic Technology, Inc. Light Extraction from Optoelectronic Device
CN107833878A (en) * 2017-11-29 2018-03-23 北京工业大学 A kind of Micro LED upside-down mounting array preparation methods of panchromatic stacking-type extension
CN109786517A (en) * 2019-01-25 2019-05-21 京东方科技集团股份有限公司 Light emitting structure, light emitting diode and preparation method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102881791A (en) * 2012-09-17 2013-01-16 聚灿光电科技(苏州)有限公司 Sapphire light-emitting diode (LED) patterned substrate and preparation method thereof
CN108010932B (en) * 2017-11-29 2019-10-29 北京工业大学 A kind of Micro-LED array preparation method of panchromatic stacking-type extension

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273367A (en) * 1994-04-01 1995-10-20 Mitsubishi Cable Ind Ltd Manufacture of semiconductor substrate and light-emitting device
US20090278165A1 (en) * 2008-05-09 2009-11-12 National Chiao Tung University Light emitting device and fabrication method therefor
CN101621109A (en) * 2008-07-02 2010-01-06 台湾积体电路制造股份有限公司 Semiconductor structure and light-emitting diode
US20140377459A1 (en) * 2013-06-19 2014-12-25 Canon Kabushiki Kaisha Semiconductor dbr, semiconductor light-emitting device, solid-state laser, photoacoustic apparatus, image-forming apparatus, and method for manufacturing semiconductor dbr
US20170117437A1 (en) * 2015-10-23 2017-04-27 Sensor Electronic Technology, Inc. Light Extraction from Optoelectronic Device
CN107833878A (en) * 2017-11-29 2018-03-23 北京工业大学 A kind of Micro LED upside-down mounting array preparation methods of panchromatic stacking-type extension
CN109786517A (en) * 2019-01-25 2019-05-21 京东方科技集团股份有限公司 Light emitting structure, light emitting diode and preparation method thereof

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TW202205768A (en) 2022-02-01

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