CN113809143A - Schottky diode with multi-guard ring structure - Google Patents

Schottky diode with multi-guard ring structure Download PDF

Info

Publication number
CN113809143A
CN113809143A CN202010547044.1A CN202010547044A CN113809143A CN 113809143 A CN113809143 A CN 113809143A CN 202010547044 A CN202010547044 A CN 202010547044A CN 113809143 A CN113809143 A CN 113809143A
Authority
CN
China
Prior art keywords
guard ring
layer
ion implantation
metal layer
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010547044.1A
Other languages
Chinese (zh)
Other versions
CN113809143B (en
Inventor
蔡宜龙
赛德·萨瓦·伊玛目
庄曜维
董铭楼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN202010547044.1A priority Critical patent/CN113809143B/en
Publication of CN113809143A publication Critical patent/CN113809143A/en
Application granted granted Critical
Publication of CN113809143B publication Critical patent/CN113809143B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A Schottky diode with a multi-guard ring structure comprises a semiconductor substrate, a back metal layer, an epitaxial layer, a dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer is stacked on the semiconductor substrate and includes a terminal trench structure, a first ion implantation guard ring, a second ion implantation guard ring and a third ion implantation guard ring. The dielectric layer is stacked on the epitaxial layer in a termination region. The first metal layer is stacked on the terminal groove structure and the dielectric layer and is provided with a groove. The passivation layer is stacked on the first metal layer and the dielectric layer. The second metal layer is stacked on the first metal layer and the passivation layer. The voltage is effectively distributed in a step manner by sequentially decreasing the widths of the first ion implantation guard ring, the second ion implantation guard ring and the third ion implantation guard ring.

Description

Schottky diode with multi-guard ring structure
Technical Field
The present invention relates to a schottky diode, and more particularly to a schottky diode with multiple guard ring structures.
Background
Generally, an ideal rectifier has characteristics of low forward voltage drop, high reverse breakdown voltage and zero leakage current, wherein the schottky diode using the metal-semiconductor junction as the schottky barrier has characteristics of low forward voltage drop and high-speed switching, and thus is widely used in power rectifier devices, but the schottky diode still has disadvantages of low reverse bias and large reverse leakage current, and thus the application of the schottky diode is limited.
As mentioned above, Schottky diodes can be mainly classified into conventional planar Schottky diodes (planar Schottky) and Trench Schottky diodes (Trench Schottky). Planar schottky diodes are mainly formed by stacking a semiconductor and a metal layer by layer to form a stacked structure, and usually require a trade-off between forward voltage drop and leakage current, so that the breakdown voltage is increased without increasing leakage current.
The trench schottky diode is mainly to refill polysilicon after the silicon layer is etched to form a trench, so that the polysilicon in the trench effectively depletes the drift electrons in the drift region to make the electric field uniformly distributed, and the trench schottky diode has lower forward voltage drop (Low VF) and lower reverse leakage current (LowIR) than the conventional planar schottky diode.
Referring to FIG. 1, FIG. 1 is a schematic cross-sectional view of a conventional trench Schottky diode. As shown, a trench Schottky diode PA100 comprises a semiconductor base layer PA1, a back metal layer PA2, an epitaxial layer PA3, a dielectric layer PA4, a first metal layer PA5, a passivation layer PA6 and a second metal layer PA 7.
The back metal layer PA2 is formed on the back surface of the semiconductor base layer PA 1. Epitaxial layer PA3 is formed on the front surface of semiconductor substrate PA1, and has a cell area PA3a and a termination area PA3b adjacent to each other, and epitaxial layer PA3 further includes a plurality of cell structures PA31 (only two are shown), a termination trench structure PA32, and a guard ring structure PA 33. The cell structures PA31 are spaced apart from each other in the cell area PA3a, and the termination trench structure PA32 is located at the intersection of the cell area PA3a and the termination area PA3b, and is spaced apart from one of the cell structures PA31 adjacent to the termination area PA3 b. Guard ring structure PA33 is adjacent to termination trench structure PA 32.
Dielectric layer PA4 is stacked in termination region PA3b over termination trench structure PA32 and guard ring structure PA 33. The first metal layer PA5 is stacked on the epitaxial layer PA3 in the cell area PA3a, and extends to the termination area PA3b and is stacked on the dielectric layer PA 4. The passivation layer PA6 is stacked on the first metal layer PA5 and extends from the cell area PA3a to the dielectric layer PA4 of the termination area PA3 b. The second metal layer PA7 is stacked on the first metal layer PA5 and the passivation layer PA6, and extends from the cell area PA3a to the termination area PA3 b.
As described above, the conventional trench schottky diode PA100 mainly extends the first metal layer PA5 and the second metal layer PA7 to the termination region to increase the reverse bias voltage, and has the guard ring structure PA33 in the epitaxial layer PA3 to disperse the potential, but the potential buffering capability achieved by the guard ring structure PA33 is limited, so that the charges of the trench schottky diode PA100 are still easily concentrated in the termination region at the edge, and the phenomenon of premature breakdown easily occurs.
Disclosure of Invention
In view of the fact that the prior art trench schottky diode extends the first metal layer and the second metal layer to the termination region for increasing the reverse bias voltage, but the surface of the epitaxial layer is easy to accumulate surface charges, although the prior art trench schottky diode is provided with a guard ring structure to prevent the drastic change of the potential, the effect is still limited; accordingly, the primary objective of the present invention is to provide a schottky diode that can reduce the accumulation of surface charges through structural changes and avoid premature breakdown.
The present invention provides a schottky diode with multiple guard ring structures, which comprises a semiconductor substrate, a back metal layer, an epitaxial layer, a dielectric layer, a first metal layer, a passivation layer and a second metal layer.
The back metal layer is arranged on one side of the semiconductor base layer. The epitaxial layer is formed on the other side of the semiconductor substrate opposite to the back metal layer and has a cell region and a termination region, and the epitaxial layer includes a termination trench (termination trench) structure, a first ion implantation guard ring, a second ion implantation guard ring and a third ion implantation guard ring.
The terminal groove structure is positioned at the junction of the unit cell area and the termination area; the first ion implantation guard ring is adjacent to the terminal trench structure in the termination region and has a first width. The second ion implantation guard ring is spaced apart from the first ion implantation guard ring in the termination region and has a second width less than the first width. The third ion implantation guard ring is spaced apart from the second ion implantation guard ring within the termination region and has a third width less than the second width.
A dielectric layer is stacked within the termination region over the termination trench structure, the first ion implantation guard ring, the second ion implantation guard ring, and the third ion implantation guard ring.
The first metal layer includes a main body portion and a separation portion. The body portion is stacked in the cell region over the terminal trench structure and extends from the cell region to the termination region to stack a dielectric layer over the first ion implant guard ring. The spacer is stacked on the dielectric layer in the termination region and extends through the dielectric layer toward the epitaxial layer to electrically contact the third ion implantation guard ring, and the spacer and the body portion form a trench exposing the dielectric layer.
The passivation layer is partially stacked on the body portion in the cell region and extends to the termination region and is stacked on the body portion, the trench, the partition portion and the dielectric layer. The second metal layer is stacked on the first metal layer and the passivation layer in the cell region, and the passivation layer is stacked on the first ion implantation protection ring by extending from the cell region to the termination region.
In an implementation derived from the above-mentioned necessary implementation, the second ion implantation guard ring is spaced apart from the first ion implantation guard ring by a first distance, and the third ion implantation guard ring is spaced apart from the second ion implantation guard ring by a second distance, wherein the second distance is greater than the first distance. Preferably, the ratio of the first pitch to the second pitch is 1: 1.2.
in a subsidiary technical means derived from the above-mentioned essential technical means, a ratio of the first width, the second width and the third width is 4:2: 1.
in an ancillary measure derived from the above-mentioned necessary measures, the dielectric layer comprises a tetraethyl orthosilicate (TEOS) film and a borophosphosilicate glass (BPSG) film, the TEOS film is stacked on the epitaxial layer in the termination region, and the borophosphosilicate glass film is stacked on the TEOS film in the termination region.
In one implementation derived from the above-mentioned necessary implementation, the epitaxial layer further includes a plurality of cell trenches (cell trenches) structure, and the cell trenches structure is located in the cell region.
In summary, the schottky diode with multiple guard ring structures of the present invention can effectively utilize the separating portion to prevent the accumulation of surface charges by dividing the first metal layer into the body portion and the separating portion which are spaced apart from each other, and because the schottky diode with multiple guard ring structures of the present invention further has the first ion implantation guard ring, the second ion implantation guard ring and the third ion implantation guard ring in the termination region, the widths of the first ion implantation guard ring, the second ion implantation guard ring and the third ion implantation guard ring gradually decrease from the cell region to the termination region, the potential curve of the entire schottky diode with multiple guard ring structures can be effectively changed in a stepwise manner, thereby effectively preventing the occurrence of premature breakdown.
The present invention will be further described with reference to the following examples and accompanying drawings.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional trench Schottky diode;
FIG. 2 is a schematic cross-sectional view of a Schottky diode having a multi-guard ring structure according to a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram showing the potential distribution curves of a Schottky diode having a multi-guard ring structure according to the preferred embodiment of the present invention; and
FIG. 4 is a schematic diagram showing the reverse bias curves of a Schottky diode having a multi-guard ring structure according to the preferred embodiment of the present invention.
Wherein the reference numerals are as follows:
PA 100: trench schottky diode
PA 1: semiconductor substrate
PA 2: back metal layer
PA 3: epitaxial layer
PA3 a: cell area
PA3 b: termination region
PA 31: cell structure
PA 32: terminal trench structure
PA 33: guard ring structure
PA 4: dielectric layer
PA 5: a first metal layer
PA 6: passivation layer
PA 7: second metal layer
100: schottky diode with multi-guard ring structure
1: semiconductor substrate
11: back side of the panel
12: front side
2: back metal layer
3: epitaxial layer
3 a: cell area
3 b: termination region
31: cell trench structure
32: terminal trench structure
321: grid oxide layer
322: polycrystalline silicon layer
33: first ion implantation guard ring
34: second ion implantation guard ring
35: third ion implantation guard ring
4: dielectric layer
41: film of tetraethoxysilane
42: boron phosphorus silicon glass film
5: a first metal layer
51: body part
511: nickel platinum alloy layer
512: titanium metal layer
513: titanium tungsten alloy layer
514: aluminum metal layer
52: partition part
521: titanium metal layer
522: titanium tungsten alloy layer
523: aluminum metal layer
6: passivation layer
7: second metal layer
71: titanium metal layer
72: nickel metal layer
73: silver metal layer
w 1: first width
w 2: second width
w 3: third width
d 1: first interval
d 2: second pitch
d 4: slotting
C1, C2, C3, C4: curve line
Detailed Description
Referring to FIG. 2, FIG. 2 is a schematic cross-sectional view of a Schottky diode having a multi-guard ring structure according to a preferred embodiment of the present invention. As shown in the figure, a Schottky diode 100 with a multi-guard ring structure comprises a semiconductor substrate 1, a back metal layer 2, an epitaxial layer 3, a dielectric layer 4, a first metal layer 5, a passivation layer 6 and a second metal layer 7.
The semiconductor substrate 1 has a back surface 11 and a front surface 12 disposed opposite to each other, and the semiconductor substrate 1 is an N-type heavily doped silicon layer. The back metal layer 2 is formed on the back surface 11 of the semiconductor substrate 1, and the back metal layer 2 comprises titanium, nickel, silver or a combination thereof. The epitaxial layer 3 is formed on the front surface 12 of the semiconductor substrate 1 and has a cell region 3a and a termination region 3b adjacent to each other, and the epitaxial layer 3 is an N-type lightly doped silicon crystal layer, wherein the light doping of the epitaxial layer 3 is relative to the heavy doping of the semiconductor substrate 1; in addition, the epitaxial layer 3 includes a plurality of cell trench (cell trench) structures 31 (only one is labeled in the figure), a termination trench (termination trench) structure 32, a first ion implantation guard ring 33, a second ion implantation guard ring 34, and a third ion implantation guard ring 35.
A plurality of cell trench structures 31 are located in the cell area 3a at intervals from each other. The termination trench structure 32 is located at the intersection of the cell region 3a and the termination region 3b, i.e., the termination trench structure 32 spans the cell region 3a and the termination region 3 b. In the present embodiment, the terminal trench structure 32 further includes a gate oxide (gate oxide)321 and a polysilicon (polysilicon) layer 322; the gate oxide layer 321 and the polysilicon layer 322 are formed in a practical manner by forming a groove on the surface of the epitaxial layer 3, oxidizing the inner wall of the groove to form the gate oxide layer 321, and then filling the polysilicon layer into the groove to form the polysilicon layer 322. In addition, the structure of the cell trench structures 31 is similar to that of the terminal trench structure 32, and the cell trench structure 31 also includes a gate oxide layer (not shown) and a polysilicon layer (not shown).
The first ion implantation guard ring 33 is adjacent to the gate oxide 321 of the terminal trench structure 32 within the stop region 3b, and the first ion implantation guard ring 33 has a first width w 1. The second ion implantation guard ring 34 is spaced apart from the first ion implantation guard ring 33 by a first spacing d1 within the termination region 3b and has a second width w2 that is less than the first width w 1. The third ion implantation guard ring 35 is spaced apart from the second ion implantation guard ring 34 within the termination region 3b by a second spacing d2 that is greater than the first spacing d1 and has a third width w3 that is less than the second width w 2. Wherein the ratio of the first width w1, the second width w2 and the third width w3 is 4:2:1, the ratio of the first spacing d1 to the second spacing d2 is 1:1.2, in the embodiment, the first width w1 is 8 μm, the second width w2 is 4 μm, the third width w3 is 2 μm, and the first distance d1 is 10 μm and the second distance d2 is 12 μm.
In addition, in practical applications, the first ion implantation guard ring 33, the second ion implantation guard ring 34 and the third ion implantation guard ring 35 are formed by implanting boron ions into the surface of the epitaxial layer 3 in the termination region 3b, and the first width w1, the second width w2 and the third width w3 are widths when implanting boron ions, which may increase the width range due to diffusion after the implantation.
The dielectric layer 4 includes a tetraethyl orthosilicate (TEOS) film 41 and a borophosphosilicate glass (BPSG) film 42. An ethyl orthosilicate film 41 is stacked on the termination trench structure 32, the first ion implantation guard ring 33, the second ion implantation guard ring 34 and the third ion implantation guard ring 35 of the epitaxial layer 3 in the termination region 3b, and a borophosphosilicate glass film 42 is stacked on the ethyl orthosilicate film 41 in the termination region 3 b.
The first metal layer 5 includes a body portion 51 and a partition portion 52. The body portion 51 is stacked on the terminal trench structure 32 in the cell region 3a, and is stacked on the dielectric layer 4 over the first ion implantation guard ring 33 extending from the cell region 3a to the termination region 3 b. The body 51 includes a nickel-platinum alloy layer 511, a titanium metal layer 512, a titanium-tungsten alloy layer 513 and an aluminum metal layer 514, wherein the nickel-platinum alloy layer 511 is formed in the cell region 3a and stacked on the epitaxial layer 3 to contact the polysilicon layer (not shown) of the cell trench structure 31. The ti layer 512 is stacked on the ni-pt alloy layer 511 in the cell region 3a, and extends from the cell region 3a to the stop region 3b to stack the dielectric layer 4 above the first ion implantation guard ring 33. The titanium tungsten alloy layer 513 is stacked on the titanium metal layer 512 in the cell region 3a, and is stacked on the titanium metal layer 512 extending from the cell region 3a to the termination region 3 b. The aluminum metal layer 514 is stacked on the titanium tungsten alloy layer 513 in the cell region 3a, and is stacked on the titanium tungsten alloy layer 513 extending from the cell region 3a to the termination region 3 b.
Spacer 52 is stacked on dielectric 4 in termination region 3b and extends through dielectric 4 toward epitaxial layer 3 to electrically contact third ion implantation guard ring 35, and a trench (not shown) is further formed between spacer 52 and body 51 to expose dielectric 4. The partition portion 52 further includes a titanium metal layer 521, a titanium tungsten alloy layer 522, and an aluminum metal layer 523. The titanium metal layer 521 is stacked on the borophosphosilicate glass film 42 of the dielectric layer 4, the titanium tungsten alloy layer 522 is stacked on the titanium metal layer 521, the aluminum metal layer 523 is stacked on the titanium tungsten alloy layer 522, and the aluminum metal layer 523 extends through the titanium metal layer 521, the titanium tungsten alloy layer 522, the borophosphosilicate glass film 42 of the dielectric layer 4 and the tetraethoxysilane film 41 toward the epitaxial layer 3 to electrically contact the third ion implantation guard ring 35, and in practice, the trench d4 of the tetraethoxysilane film 41 is, for example, 2 μm.
In practical manufacturing, the titanium metal layer 512 and the titanium metal layer 521 are formed by the same sputtering process, the titanium-tungsten alloy layer 513 and the titanium-tungsten alloy layer 522 are formed by the same sputtering process, then the aluminum metal layer 514 and the aluminum metal layer 523 are formed by the same sputtering process, and the aluminum metal layer 523, the titanium-tungsten alloy layer 522 and the titanium metal layer 521 pass through the dielectric layer 4, and the titanium metal layer 521 is further electrically contacted with the third ion implantation guard ring 35, so that the aluminum metal layer 522 and the titanium metal layer 521 can be electrically connected to the third ion implantation guard ring 35 through the titanium-tungsten alloy layer 522 and the titanium metal layer 521. Before forming the titanium metal layer 521, the titanium-tungsten alloy layer 522, and the aluminum metal layer 523, the dielectric layer 4 above the third ion implantation guard ring 35 is grooved by etching or laser, so that the titanium metal layer 521, the titanium-tungsten alloy layer 522, and the aluminum metal layer 523 penetrate through the dielectric layer 4 and electrically contact the third ion implantation guard ring 35.
In addition, after the titanium metal layers 512 and 521, the titanium tungsten alloy layers 513 and 522, and the aluminum metal layers 514 and 523 are formed, a recess is formed by an etching process, thereby separating the body portion 51 and the separation portion 52.
The passivation layer 6 is partially stacked on the body portion 51 in the cell region 3a, and extends to the groove stacked between the body portion 51, the separating portion 52 and the dielectric layer 4 in the termination region 3 b. In the present embodiment, the passivation layer 6 is a silicon nitride layer.
The second metal layer 7 is stacked on the first metal layer 5 and the passivation layer 6 in the cell region 3a, and the passivation layer 6 is stacked over the first ion implantation guard ring 33 extending from the cell region 3a to the termination region 3 b. The second metal layer 7 includes a titanium metal layer 71, a nickel metal layer 72 and a silver metal layer 73, the titanium metal layer 71 is stacked on the aluminum metal layer 514 of the first metal layer 5 and the passivation layer 6, the nickel metal layer 72 is stacked on the titanium metal layer 71, and the silver metal layer 73 is stacked on the nickel metal layer 72.
With continuing reference to FIGS. 3 and 4, FIG. 3 is a schematic diagram illustrating potential distribution curves of a Schottky diode having a multi-guard ring structure according to a preferred embodiment of the present invention; FIG. 4 is a schematic diagram showing the reverse bias curves of a Schottky diode having a multi-guard ring structure according to the preferred embodiment of the present invention.
Referring to FIGS. 1-3, curve C1 of FIG. 3 corresponds to the conventional trench Schottky diode PA100 of FIG. 1, and curve C2 of FIG. 3 corresponds to the Schottky diode 100 with multiple protection ring structure provided in the preferred embodiment of the present invention of FIG. 2; wherein, the guard ring structure PA33 of the trench Schottky diode PA100 maintains the potential of the curve C1 at about 35V, so that the potential can change to 250V rapidly after passing through the guard ring structure PA 33; however, the schottky diode 100 with multiple guard rings of the present invention can first maintain the potential at about 35V through the first ion implantation guard ring 33, then maintain the potential at about 100V through the second ion implantation guard ring 34, and finally maintain the potential at about 200V through the third ion implantation guard ring 35, so that the schottky diode 100 with multiple guard rings of the present invention can indeed generate a stepwise change in the potential through the first ion implantation guard ring 33, the second ion implantation guard ring 34, and the third ion implantation guard ring 35, thereby effectively dispersing the potential and preventing the breakdown voltage from occurring too early.
In addition, since the schottky diode 100 with multiple guard ring structures of the present invention further includes the spacer 52 disposed above the third ion implanted guard ring 35 to electrically contact the third ion implanted guard ring 35, the accumulation of surface charges can be effectively prevented.
On the other hand, as shown in FIG. 4, curve C3 of FIG. 4 corresponds to the reverse voltage variation of the conventional trench Schottky diode PA100 of FIG. 1, and curve C4 of FIG. 4 corresponds to the reverse voltage variation of the Schottky diode 100 with multiple protection ring structure of the present invention, so that the Schottky diode 100 with multiple protection ring structure of the present invention can maintain the reverse bias performance similar to that of the conventional trench Schottky diode PA 100.
In summary, compared with the trench schottky diode of the prior art, in order to increase the reverse bias voltage, the first metal layer and the second metal layer are extended to the termination region, thereby leading the surface of the epitaxial layer to be easy to accumulate surface charges, the Schottky diode with the multi-guard ring structure of the invention divides the first metal layer into the body part and the separating part which are separated, the spacer can be effectively used to prevent the accumulation of surface charges, and because the Schottky diode having a multi-guard ring structure of the present invention further has a first ion implantation guard ring, a second ion implantation guard ring and a third ion implantation guard ring in the termination region, the first ion implantation guard ring, the second ion implantation guard ring and the third ion implantation guard ring having gradually decreasing widths from the cell region to the termination region, therefore, the potential curve of the whole Schottky diode with the multi-guard ring structure can be effectively changed in a staged manner, and the phenomenon of premature breakdown can be effectively prevented.
The above detailed description of the preferred embodiments is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of the present invention by the preferred embodiments disclosed above. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

Claims (6)

1. A schottky diode having a multiple guard ring structure, comprising:
a semiconductor substrate;
a back metal layer disposed on one side of the semiconductor substrate;
an epitaxial layer formed on the other side of the semiconductor substrate opposite to the back metal layer and having a cell region and a termination region, the epitaxial layer comprising:
a termination trench structure located at the interface of the cell region and the termination region;
a first ion implantation guard ring adjacent to the termination trench structure within the termination region and having a first width;
a second ion implantation guard ring spaced apart from the first ion implantation guard ring within the termination region and having a second width less than the first width; and
a third ion implantation guard ring spaced apart from the second ion implantation guard ring within the termination region and having a third width less than the second width;
a dielectric layer stacked within the termination region over the termination trench structure, the first ion implantation guard ring, the second ion implantation guard ring, and the third ion implantation guard ring;
a first metal layer comprising:
a body portion stacked over the termination trench structure in the cell region and extending from the cell region to the termination region to stack the dielectric layer over the first ion implant guard ring; and
a spacer stacked on the dielectric layer in the termination region and extending through the dielectric layer toward the epitaxial layer to electrically contact the third ion implantation guard ring, wherein the spacer and the body portion form a trench exposing the dielectric layer;
a passivation layer partially stacked on the body portion in the cell region and extending to the termination region and stacked on the body portion, the trench, the partition portion and the dielectric layer; and
a second metal layer overlying the first metal layer and the passivation layer in the cell region and extending from the cell region to the termination region to overlie the passivation layer over the first ion implant guard ring.
2. The schottky diode of claim 1, wherein the second ion implanted guard ring is spaced apart from the first ion implanted guard ring by a first spacing, the third ion implanted guard ring is spaced apart from the second ion implanted guard ring by a second spacing, and the second spacing is greater than the first spacing.
3. The schottky diode of claim 2, wherein the ratio of the first pitch to the second pitch is 1: 1.2.
4. The schottky diode with multiple guard ring structures of claim 1, wherein the ratio of the first width, the second width and the third width is 4:2: 1.
5. The schottky diode with multiple guard ring structures of claim 1, wherein said dielectric layer comprises an tetraethoxysilane film and a borophosphosilicate glass film, said tetraethoxysilane film is stacked on said epitaxial layer in said termination region, said borophosphosilicate glass film is stacked on said tetraethoxysilane film in said termination region.
6. The schottky diode with multiple guard ring structures of claim 1, wherein said epitaxial layer further comprises a plurality of cell trench structures, said cell trench structures being located in said cell region.
CN202010547044.1A 2020-06-16 2020-06-16 Schottky diode with multi-guard ring structure Active CN113809143B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010547044.1A CN113809143B (en) 2020-06-16 2020-06-16 Schottky diode with multi-guard ring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010547044.1A CN113809143B (en) 2020-06-16 2020-06-16 Schottky diode with multi-guard ring structure

Publications (2)

Publication Number Publication Date
CN113809143A true CN113809143A (en) 2021-12-17
CN113809143B CN113809143B (en) 2024-08-06

Family

ID=78892508

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010547044.1A Active CN113809143B (en) 2020-06-16 2020-06-16 Schottky diode with multi-guard ring structure

Country Status (1)

Country Link
CN (1) CN113809143B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094100A (en) * 2011-10-28 2013-05-08 比亚迪股份有限公司 Method of forming schottky diode
US20130168765A1 (en) * 2012-01-04 2013-07-04 Vishay General Semiconductor Llc Trench dmos device with improved termination structure for high voltage applications
US20170243964A1 (en) * 2016-02-19 2017-08-24 Toyota Jidosha Kabushiki Kaisha Semiconductor device
CN108346688A (en) * 2018-01-25 2018-07-31 中国科学院微电子研究所 SiC trench junction barrier Schottky diode with CS L transport layer and manufacturing method thereof
CN110838517A (en) * 2018-08-17 2020-02-25 三菱电机株式会社 Semiconductor device and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094100A (en) * 2011-10-28 2013-05-08 比亚迪股份有限公司 Method of forming schottky diode
US20130168765A1 (en) * 2012-01-04 2013-07-04 Vishay General Semiconductor Llc Trench dmos device with improved termination structure for high voltage applications
US20170243964A1 (en) * 2016-02-19 2017-08-24 Toyota Jidosha Kabushiki Kaisha Semiconductor device
CN108346688A (en) * 2018-01-25 2018-07-31 中国科学院微电子研究所 SiC trench junction barrier Schottky diode with CS L transport layer and manufacturing method thereof
CN110838517A (en) * 2018-08-17 2020-02-25 三菱电机株式会社 Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
CN113809143B (en) 2024-08-06

Similar Documents

Publication Publication Date Title
US7777278B2 (en) Lateral semiconductor component with a drift zone having at least one field electrode
US9018698B2 (en) Trench-based device with improved trench protection
WO2013103491A1 (en) Trench dmos device with improved termination structure for high voltage applications
KR100884078B1 (en) Schottky rectifier and method of forming the same
JP6026418B2 (en) Bipolar non-punch-through power semiconductor device
US9716187B2 (en) Trench semiconductor device having multiple trench depths and method
KR20030038718A (en) Trench schottky rectifier
JP2004529506A5 (en)
EP2650920B1 (en) Trenched semiconductor structure
US10847660B2 (en) Trench semiconductor device having multiple active trench depths and method
KR102281493B1 (en) Power semiconductor device and manufacturing method thereof
US11038019B2 (en) Power semiconductor device and method for manufacturing the same
WO2015105573A1 (en) Trench mos device having a termination structure with multiple field-relaxation trenches for high voltage applications
EP3723137A1 (en) Diode structure and manufacturing method thereof
TWI743818B (en) Schottky diode with multiple guard ring structures
JP2008251925A (en) Diode
CN113809143B (en) Schottky diode with multi-guard ring structure
CN112864255A (en) Schottky diode structure and manufacturing method thereof
TWI757758B (en) Multi-trench schottky diode
EP2650921A1 (en) Semiconductor structure comprising active region trenches arranged in a dispersed manner
CN113809144A (en) Multi-trench schottky diode
JP2023005783A (en) diode

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant