CN113809144A - Multi-trench schottky diode - Google Patents

Multi-trench schottky diode Download PDF

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Publication number
CN113809144A
CN113809144A CN202010547068.7A CN202010547068A CN113809144A CN 113809144 A CN113809144 A CN 113809144A CN 202010547068 A CN202010547068 A CN 202010547068A CN 113809144 A CN113809144 A CN 113809144A
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Prior art keywords
layer
trench
metal layer
trench structure
region
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Inventor
蔡宜龙
赛德·萨瓦·伊玛目
庄曜维
董铭楼
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/0692—Surface layout
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Abstract

A multi-trench Schottky diode comprises a semiconductor substrate, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer is stacked on the semiconductor base layer and comprises a terminal groove structure, a first groove structure, a second groove structure and a third groove structure. The interlayer dielectric layer is stacked on the epitaxial layer in a termination region. The first metal layer is stacked on the terminal groove structure and the interlayer dielectric layer and extends to a position between the second groove structure and the third groove structure. The passivation layer is stacked on the first metal layer and the interlayer dielectric layer. The second metal layer is stacked on the first metal layer and the passivation layer and extends to the first groove structure. By arranging a plurality of trench structures in the termination region, the electric field can be effectively dispersed and premature breakdown voltage can be avoided.

Description

Multi-trench schottky diode
Technical Field
The present invention relates to schottky diodes, and more particularly to a multi-trench schottky diode having a plurality of trenches.
Background
Generally, an ideal rectifier has characteristics of low forward voltage drop, high reverse breakdown voltage and zero leakage current, wherein the schottky diode using the metal-semiconductor junction as the schottky barrier has characteristics of low forward voltage drop and high-speed switching, and thus is widely used in power rectifier devices, but the schottky diode still has disadvantages of low reverse bias and large reverse leakage current, and thus the application of the schottky diode is limited.
As mentioned above, Schottky diodes can be mainly classified into conventional Planar Schottky diodes (Planar Schottky) and Trench Schottky diodes (Trench Schottky). Planar schottky diodes are mainly formed by stacking a semiconductor and a metal layer by layer to form a stacked structure, and usually require a trade-off between forward voltage drop and leakage current, so that the breakdown voltage is increased without increasing leakage current.
The trench schottky diode is mainly to refill polysilicon after the silicon crystal layer is etched to the trench, so as to effectively deplete the drift electrons in the drift region by the polysilicon in the trench and make the electric field uniformly distributed, and has lower forward voltage drop (Low VF) and lower reverse leakage current (Low IR) than the conventional planar schottky diode.
Referring to FIG. 1, FIG. 1 is a schematic cross-sectional view of a conventional trench Schottky diode. As shown, a trench Schottky diode PA100 comprises a semiconductor base layer PA1, a back metal layer PA2, an epitaxial layer PA3, a dielectric layer PA4, a first metal layer PA5, a passivation layer PA6 and a second metal layer PA 7.
The back metal layer PA2 is formed on the back surface of the semiconductor base layer PA 1. The epitaxial layer PA3 is formed on the front surface of the semiconductor substrate PA1, and has a cell region PA3a and a termination region PA3b adjacent to each other, and the epitaxial layer PA3 further includes a plurality of cell structures PA31 (only two are shown), a termination trench structure PA32, and a guard ring structure PA 33. The cell structures PA31 are spaced apart from each other in the cell area PA3a, and the termination trench structure PA32 is located at the boundary between the cell area PA3a and the termination area PA3b, and is spaced apart from one of the cell structures PA31 adjacent to the termination area PA3 b. Guard ring structure PA33 is adjacent to termination trench structure PA 32.
Dielectric layer PA4 is stacked in termination region PA3b over termination trench structure PA32 and guard ring structure PA 33. The first metal layer PA5 is stacked on the epitaxial layer PA3 in the cell region PA3a, and extends to the termination region PA3b where it is stacked on the dielectric layer PA 4. The passivation layer PA6 is stacked on the first metal layer PA5 and extends from the cell area PA3a to the dielectric layer PA4 of the termination area PA3 b. The second metal layer PA7 is stacked on the first metal layer PA5 and the passivation layer PA6, and extends from the cell area PA3a to the termination area PA3 b.
As described above, the conventional trench schottky diode PA100 mainly extends the first metal layer PA5 and the second metal layer PA7 to the terminal regions to increase the reverse bias voltage, and has the guard ring structure PA33 in the epitaxial layer PA3 to disperse the potential, but the potential buffering capability achieved by the guard ring structure PA33 is limited, so that the charges of the trench schottky diode PA100 are still easily concentrated in the terminal regions at the edge, and the phenomenon of premature breakdown is easily caused.
Disclosure of Invention
In view of the fact that the prior art trench schottky diode extends the first metal layer and the second metal layer to the termination region for increasing the reverse bias voltage, but the surface of the epitaxial layer is easy to accumulate surface charges, although the prior art trench schottky diode is provided with a guard ring structure to prevent the drastic change of the potential, the effect is still limited; accordingly, the primary objective of the present invention is to provide a schottky diode that can reduce the accumulation of surface charges through structural changes and avoid premature breakdown.
The present invention provides a multi-trench schottky diode, which comprises a semiconductor substrate, a back metal layer, an epitaxial layer, an interlayer dielectric (ILD), a first metal layer, a passivation layer and a second metal layer.
The back metal layer is formed on one side of the semiconductor substrate. The epitaxial layer is formed on the other side of the semiconductor substrate opposite to the back metal layer and is provided with a cell area and a terminal area, and the epitaxial layer comprises a terminal trench (termination trench) structure, a first trench structure, a second trench structure and a third trench structure.
The terminal trench structure is located at the interface of the cell region and the terminal region. The first trench structure is spaced apart from the termination trench structure in the termination region and has a first width. The second trench structure is spaced apart from the first trench structure in the termination region and has a second width less than the first width. The third trench structure is spaced apart from the second trench structure in the termination region and has a third width less than the second width.
The interlayer dielectric layer is stacked on the terminal groove structure, the first groove structure, the second groove structure and the third groove structure in the terminal area, and a first interlayer dielectric layer groove, a second interlayer dielectric layer groove and a third interlayer dielectric layer groove are respectively formed at the first groove structure, the second groove structure and the third groove structure.
The first metal layer is stacked in the cell region between the second trench structure and the third trench structure, and extends from the cell region to the terminal region, and a first metal layer trench and a second metal layer trench are formed in the first interlayer dielectric layer trench and the second interlayer dielectric layer trench.
The passivation layer is partially stacked on the first metal layer in the cell region, extends from the cell region to the terminal region and is stacked on the first metal layer and the third interlayer dielectric layer groove, and the passivation layer further forms a first passivation layer groove, a second passivation layer groove and a third passivation layer groove at the first metal layer, the second metal layer groove and the third interlayer dielectric layer groove respectively.
The second metal layer covers the first metal layer and the passivation layer in the cell region, extends from the cell region to the terminal region, and is partially stacked in the first passivation layer trench.
In a subsidiary technical means derived from the above-mentioned essential technical means, a ratio of the first width, the second width and the third width is 7:5: 3.
in an auxiliary technical means derived from the above-mentioned necessary technical means, the interlayer dielectric layer includes a tetraethyl orthosilicate (TEOS) film and a borophosphosilicate glass (BPSG) film, the tetraethyl orthosilicate film covers the epitaxial layer in the termination region, and the borophosphosilicate glass film covers the tetraethyl orthosilicate film in the termination region.
In an implementation derived from the above-mentioned necessary implementation, the epitaxial layer further includes a plurality of cell trenches (cell trenches), each cell trench including a gate oxide (gate oxide) and a low-doped polysilicon layer. The gate oxide layer is formed in the cell region. A low doped polysilicon layer is formed within the gate oxide layer.
In an additional technical means derived from the above-mentioned essential technical means, the terminal trench structure further includes a gate oxide layer and a low-doped polysilicon layer. The gate oxide layer is formed in the cell region and the termination region. A low doped polysilicon layer is formed within the gate oxide layer. Preferably, the first metal layer comprises a nickel-platinum alloy layer stacked on the epitaxial layer and electrically contacting the low-doped polysilicon layer. In addition, the first metal layer comprises a titanium metal layer, a titanium-tungsten alloy layer and an aluminum metal layer, wherein the titanium metal layer is stacked on the nickel-platinum alloy layer and the interlayer dielectric layer and extends from the cell area to a position between the second groove structure and the third groove structure of the terminal area, the titanium-tungsten alloy layer is stacked on the titanium metal layer, and the aluminum metal layer is stacked on the titanium-tungsten alloy layer.
In an auxiliary technical means derived from the above-mentioned essential technical means, the second metal layer includes a titanium metal layer, a nickel metal layer and a silver metal layer, the titanium metal layer is stacked on the first metal layer and the passivation layer, and extends from the cell region to the terminal region and is partially stacked in the first passivation layer trench, the nickel metal layer is stacked on the titanium metal layer, and the silver metal layer is stacked on the nickel metal layer.
In one implementation derived from the above-mentioned necessary implementation, the epitaxial layer further includes a plurality of cell trenches (cell trenches) structure, and the cell trenches structure is located in the cell region.
In summary, in the multi-trench schottky diode of the present invention, the first trench structure, the second trench structure and the third trench structure are formed in the terminal region, and the first metal layer is extended between the second trench structure and the third trench structure, so that the electric field in the terminal region can be effectively dispersed, and the electric field is prevented from being excessively concentrated on the surface of the terminal region; in addition, through the gradual reduction of the widths of the first trench structure, the second trench structure and the third trench structure, the potential of the terminal region can be effectively and gradually increased, and further the early occurrence of breakdown voltage can be effectively avoided.
The present invention will be further described with reference to the following examples and accompanying drawings.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional trench Schottky diode;
FIG. 2 is a cross-sectional view of a multi-trench Schottky diode according to the preferred embodiment of the present invention;
FIG. 3 is a schematic diagram showing the electromagnetic field distribution curves of a multi-trench Schottky diode according to the preferred embodiment of the present invention; and
FIG. 4 is a schematic diagram showing the potential curves of the multi-trench Schottky diode according to the preferred embodiment of the present invention.
Wherein the reference numerals are as follows:
PA 100: trench schottky diode
PA 1: semiconductor substrate
PA 2: back metal layer
PA 3: epitaxial layer
PA3 a: cell area
PA3 b: terminal area
PA 31: cell structure
PA 32: terminal trench structure
PA 33: guard ring structure
PA 4: dielectric layer
PA 5: a first metal layer
PA 6: passivation layer
PA 7: second metal layer
100: multi-trench schottky diode
1: semiconductor substrate
11: back side of the panel
12: front side
2: back metal layer
3: epitaxial layer
3 a: cell area
3 b: terminal area
31: cell trench structure
311: grid oxide layer
312: low doped polysilicon layer
32: terminal trench structure
321: grid oxide layer
322: low doped polysilicon layer
33: first trench structure
331: grid oxide layer
332: low doped polysilicon layer
34: second trench structure
341: grid oxide layer
342: low doped polysilicon layer
35: third trench structure
351: grid oxide layer
352: low doped polysilicon layer
4: interlayer dielectric layer
41: film of tetraethoxysilane
42: boron phosphorus silicon glass film
5: a first metal layer
51: nickel platinum alloy layer
52: titanium metal layer
53: titanium tungsten alloy layer
54: aluminum metal layer
6: passivation layer
7: second metal layer
71: titanium metal layer
72: nickel metal layer
73: silver metal layer
w 1: first width
w 2: second width
w 3: third width
C1, C2, C3, C4: curve line
Detailed Description
Referring to FIG. 2, FIG. 2 is a cross-sectional view of a multi-trench Schottky diode according to a preferred embodiment of the present invention. As shown, a multi-trench schottky diode 100 includes a semiconductor base layer 1, a back metal layer 2, an epitaxial layer 3, an interlayer dielectric (ILD) 4, a first metal layer 5, a passivation layer 6 and a second metal layer 7.
The semiconductor substrate 1 has a back surface 11 and a front surface 12 disposed opposite to each other, and the semiconductor substrate 1 is an N-type heavily doped silicon layer. The back metal layer 2 is formed on the back surface 11 of the semiconductor substrate 1. The epitaxial layer 3 is formed on the front surface 12 of the semiconductor substrate 1 and has a cell region 3a and a termination region 3b, and the epitaxial layer 3 is an N-type lightly doped silicon layer, wherein the light doping of the epitaxial layer 3 is relative to the heavy doping of the semiconductor substrate 1; in addition, the epitaxial layer 3 includes a plurality of cell trench structures 31 (only one is labeled), a termination trench structure 32, a first trench structure 33, a second trench structure 34, and a third trench structure 35.
A plurality of cell trench structures 31 are spaced apart from each other in the cell region 3a, and each cell trench structure 31 includes a gate oxide layer 311(gate oxide) and a low-doped polysilicon layer 312 (polysilicon), and the low-doped polysilicon layer 312 is filled in the trench of the gate oxide layer 311. The termination trench structure 32 is located at the boundary between the cell region 3a and the termination region 3b, i.e. the termination trench structure 32 spans the cell region 3a and the termination region 3 b. In the present embodiment, the terminal trench structure 32 further includes a gate oxide layer 321 and two low-doped polysilicon layers 322 (only one is labeled in the figure), the gate oxide layer 321 is formed in the cell region 3a and the terminal region 3b, and the two low-doped polysilicon layers 322 are respectively formed on two sides of the gate oxide layer 321; the gate oxide layer 321 and the low-doped polysilicon layer 322 are formed in a practical manner by forming a trench on the surface of the epitaxial layer 3, then oxidizing the inner wall of the trench to form the gate oxide layer 321, and then filling polysilicon into the two sidewalls of the trench, so that the two low-doped polysilicon layers 322 are formed on the two sides of the gate oxide layer 321, respectively.
The first trench structure 33 is spaced apart from the termination trench structure 32 in the termination region 3b and has a first width w 1; the first trench structure 33 further includes a gate oxide layer 331 and two low-doped polysilicon layers 332 (only one is labeled in the figure), wherein the gate oxide layer 331 is formed in the termination region 3b, and the two low-doped polysilicon layers 332 are respectively formed on two sides of the gate oxide layer 331. The second trench structure 34 is spaced apart from the first trench structure 33 in the termination region 3b and has a second width w2 smaller than the first width w 1; the second trench structure 34 further includes a gate oxide layer 341 and two low-doped polysilicon layers 342 (only one is labeled in the figure), the gate oxide layer 341 is formed in the termination region 3b, and the two low-doped polysilicon layers 342 are respectively formed on two sides of the gate oxide layer 341. The third trench structure 35 is spaced apart from the second trench structure 34 in the termination region 3b and has a third width w3 that is less than the second width w 2; the third trench structure 35 further includes a gate oxide layer 351 and two low-doped polysilicon layers 352 (only one is labeled in the figure), wherein the gate oxide layer 351 is formed in the termination region 3b, and the two low-doped polysilicon layers 352 are respectively formed on two sides of the gate oxide layer 351.
As mentioned above, the ratio of the first width w1, the second width w2 and the third width w3 is 7:5:3, in the embodiment, the first width w1 is, for example, 14 μm, the second width w2 is, for example, 10 μm, the third width w3 is, for example, 6 μm, the distance between the first trench structure 33 and the second trench structure 34 is 2.8 μm, and the distance between the second trench structure 34 and the third trench structure 35 is also 2.8 μm.
The interlayer dielectric layer 4 includes a tetraethyl orthosilicate (TEOS) film 41 and a borophosphosilicate glass (BPSG) film 42. The tetraethoxysilane film 41 covers the termination trench structure 32, the first trench structure 33, the second trench structure 34 and the third trench structure 35 of the epitaxial layer 3 in the termination region 3b, and the tetraethoxysilane film 41 further forms a first tetraethoxysilane trench (not shown), a second tetraethoxysilane trench (not shown) and a third tetraethoxysilane trench (not shown) in the first trench structure 33, the second trench structure 34 and the third trench structure 35, respectively. The borophosphosilicate glass thin film 42 covers the first, second and third trenches of the tetraethyl orthosilicate thin film 41 in the termination region 3b, and forms a first inter-layer dielectric trench (not shown), a second inter-layer dielectric trench (not shown) and a third inter-layer dielectric trench (not shown) in the first, second and third trench structures 33, 34 and 35, respectively.
The first metal layer 5 includes a nickel-platinum alloy layer 51, a titanium metal layer 52, a titanium-tungsten alloy layer 53 and an aluminum metal layer 54. The ni-pt alloy layer 51 is stacked on the epitaxial layer 3 in the cell region 3a and electrically contacts the lowly doped polysilicon layer 322. The titanium layer 52 is stacked on the nickel-platinum alloy layer 51 and the borophosphosilicate glass film 42 of the interlayer dielectric layer 4, and extends from the cell region 3a to a position between the second trench structure 34 and the third trench structure 35 of the termination region 3b, and the titanium layer 52 further forms a first titanium layer trench (not shown) and a second titanium layer trench (not shown) in the first interlayer dielectric layer trench and the second interlayer dielectric layer trench, respectively. The titanium-tungsten alloy layer 53 is stacked on the titanium metal layer 52 and extends from the cell region 3a to the terminal region 3b between the second trench structure 34 and the third trench structure 35, and the titanium-tungsten alloy layer 53 further forms a first titanium-tungsten alloy layer trench (not shown) and a second titanium-tungsten alloy layer trench (not shown) at the first titanium-metal layer trench and the second titanium-metal layer trench, respectively. The aluminum metal layer 54 is stacked on the titanium tungsten alloy layer 53 and extends from the cell region 3a to a position between the second trench structure 34 and the third trench structure 35 of the termination region 3b, and the aluminum metal layer 54 further forms a first metal layer trench (not shown) and a second metal layer trench (not shown) at the first titanium tungsten layer trench and the second titanium tungsten layer trench, respectively.
The passivation layer 6 is an aluminum layer 54 partially stacked on the first metal layer 5 in the cell region 3a, and extends from the cell region 3a to the termination region 3b to be stacked on the first metal layer 5 and the third ild layer trench, and the passivation layer 6 further forms a first passivation layer trench (not shown), a second passivation layer trench (not shown) and a third passivation layer trench (not shown) in the first metal layer trench, the second metal layer trench and the third ild layer trench, respectively. In the present embodiment, the passivation layer 6 is a silicon nitride layer.
The second metal layer 7 includes a titanium metal layer 71, a nickel metal layer 72, and a silver metal layer 73. The titanium metal layer 71 is stacked on the aluminum metal layer 54 and the passivation layer 6 of the first metal layer 5 in the cell region 3a, and extends from the cell region 3a to the termination region 3b to be partially stacked in the first passivation layer trench. The nickel metal layer 72 is stacked on the titanium metal layer 71 in the cell region 3a, and is stacked on the titanium metal layer 71 at the first passivation layer trench extending from the cell region 3a to the termination region 3 b. The silver metal layer 73 is stacked on the nickel metal layer 72 in the cell region 3a, and is stacked on the nickel metal layer 72 at the first passivation layer trench extending from the cell region 3a to the termination region 3 b.
With continuing reference to FIGS. 3 and 4, FIG. 3 is a schematic diagram illustrating electromagnetic field distribution curves of a multi-trench Schottky diode according to a preferred embodiment of the present invention; FIG. 4 is a schematic diagram showing the potential curves of the multi-trench Schottky diode according to the preferred embodiment of the present invention.
Referring to FIGS. 1-3, curve C1 of FIG. 3 corresponds to the electric field distribution of the conventional trench Schottky diode PA100 of FIG. 1, and curve C2 of FIG. 3 corresponds to the electric field distribution of the multi-trench Schottky diode 100 provided in the preferred embodiment of the present invention of FIG. 2. The electric field of the curve C1 at 0-10 μm is higher because of the cell structure PA31 corresponding to the cell area PA3a, however, since the first metal layer PA5 extends to the termination area PA3b, there is a charge concentration at the edge of the first metal layer PA5, which causes the electric field of the curve C1 at the measurement position about 25 μm to rise again; in contrast, although the multi-trench schottky diode 100 of the present embodiment extends the first metal layer 5 to the position between the second trench structure 34 and the third trench structure 35 of the termination region 3b, since the first metal layer 5 is formed with the first metal layer trench and the second metal layer trench at the first trench structure 33 and the second trench structure 34, respectively, the electric field of the multi-trench schottky diode 100 of the present embodiment can be effectively reduced at the position corresponding to 10 μm to 14 μm of the first metal layer trench and at the position corresponding to 26 μm to 30 μm of the second metal layer trench, and the electric field of the entire termination region 3b is dispersed without being excessively concentrated. In addition, since the electric field in the termination region 3b is dispersed because the first metal layer 5 extends to between the second trench structure 34 and the third trench structure 35 of the termination region 3b, the strong electric field can be effectively kept away from the cell trench structure 31 of the cell region 3a, thereby effectively preventing the schottky contact of the cell trench structure 31 from being interfered by the strong electric field.
On the other hand, as shown in FIG. 4, curve C3 of FIG. 4 corresponds to the potential variation of the conventional trench Schottky diode PA100 of FIG. 1, and curve C4 of FIG. 4 corresponds to the potential variation of the multi-trench Schottky diode 100 of the present invention; wherein, the guard ring structure PA33 of the trench Schottky diode PA100 corresponds to the measurement position of 10 μm-20 μm, so that the potential of the curve C1 is maintained below 50V, but after the guard ring structure PA33 is passed, the potential is changed to near 250V, which is easy to cause early breakdown voltage in practice; however, since the multi-trench schottky diode 100 of the present invention utilizes the first width w1 of the first trench structure 33, the second width w2 of the second trench structure 34 and the third width w3 of the third trench structure 35 to gradually decrease, and the first metal layer 5 extends to between the second trench structure 34 and the third trench structure 35, the potential of the multi-trench schottky diode 100 can be gradually increased, thereby effectively avoiding the premature occurrence of breakdown voltage.
In summary, compared with the prior art that the first metal layer and the second metal layer are extended to the terminal region to increase the reverse bias voltage, and thus the surface charge is easy to accumulate on the surface of the epitaxial layer, the multi-trench schottky diode of the present invention can effectively disperse the electric field in the terminal region by forming the first trench structure, the second trench structure and the third trench structure in the terminal region and extending the first metal layer between the second trench structure and the third trench structure, thereby preventing the electric field from being excessively concentrated on the surface of the terminal region; in addition, through the gradual reduction of the widths of the first trench structure, the second trench structure and the third trench structure, the potential of the terminal region can be effectively and gradually increased, and the early breakdown voltage is further effectively avoided.
The above detailed description of the preferred embodiments is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of the present invention by the preferred embodiments disclosed above. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

Claims (8)

1. A multi-trench schottky diode, comprising:
a semiconductor substrate;
a back metal layer formed on one side of the semiconductor substrate;
an epitaxial layer formed on the other side of the semiconductor substrate opposite to the back metal layer and having a cell region and a termination region, the epitaxial layer comprising:
a termination trench structure located at the interface of the cell region and the termination region;
a first trench structure spaced apart from the termination trench structure in the termination region and having a first width;
a second trench structure spaced from the first trench structure in the termination region and having a second width less than the first width; and
a third trench structure spaced from the second trench structure in the termination region and having a third width less than the second width:
an interlayer dielectric layer stacked on the terminal trench structure, the first trench structure, the second trench structure and the third trench structure in the terminal region, and forming a first interlayer dielectric layer trench, a second interlayer dielectric layer trench and a third interlayer dielectric layer trench at the first trench structure, the second trench structure and the third trench structure, respectively;
a first metal layer stacked on the terminal trench structure in the cell region and extending from the cell region to a position between the second trench structure and the third trench structure in the terminal region, wherein the first metal layer further forms a first metal layer trench and a second metal layer trench at the first interlayer dielectric layer trench and the second interlayer dielectric layer trench, respectively:
a passivation layer partially stacked on the first metal layer in the cell region, extending from the cell region to the termination region and stacked on the first metal layer and the third interlayer dielectric trench, wherein the passivation layer further forms a first passivation layer trench, a second passivation layer trench and a third passivation layer trench at the first metal layer, the second metal layer trench and the third interlayer dielectric trench, respectively; and
a second metal layer covering the first metal layer and the passivation layer in the cell region, extending from the cell region to the termination region and partially stacked in the first passivation layer trench.
2. The multi-trench schottky diode of claim 1, wherein the ratio of said first width, said second width and said third width is 7:5: 3.
3. The multi-trench schottky diode of claim 1, wherein said interlayer dielectric comprises an tetraethylorthosilicate film overlying said epitaxial layer in said termination region and a borophosphosilicate glass film overlying said tetraethylorthosilicate film in said termination region.
4. The multi-trench schottky diode of claim 1, wherein said epitaxial layer further comprises a plurality of cell trench structures, each said cell trench structure comprising:
a grid oxide layer formed in the unit cell area; and
a low doped polysilicon layer is formed in the gate oxide layer.
5. The multi-trench schottky diode of claim 1, wherein said termination trench structure further comprises:
a grid oxide layer formed on the unit cell region and the terminal region; and
a low doped polysilicon layer is formed in the gate oxide layer.
6. The multi-trench Schottky diode of claim 5 wherein the first metal layer comprises a nickel platinum alloy layer stacked on the epitaxial layer and electrically contacting the lowly doped polysilicon layer.
7. The multi-trench schottky diode of claim 6, wherein said first metal layer comprises a titanium metal layer stacked on said ni-pt alloy layer and said ild layer and extending from said cell region to between said second trench structure and said third trench structure in said termination region, a ti-w alloy layer stacked on said titanium metal layer, and an al metal layer stacked on said ti-w alloy layer.
8. The multi-trench schottky diode of claim 1, wherein said second metal layer comprises a titanium layer stacked on said first metal layer and said passivation layer and extending from said cell region to said termination region and partially stacked in said first passivation layer trench, a nickel layer stacked on said titanium layer, and a silver layer stacked on said nickel layer.
CN202010547068.7A 2020-06-16 2020-06-16 Multi-trench schottky diode Pending CN113809144A (en)

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Publication number Priority date Publication date Assignee Title
US20130168761A1 (en) * 2011-12-30 2013-07-04 Feei Cherng Enterprise Co., Ltd. Semiconductor power device having improved termination structure for mask saving
US20130270668A1 (en) * 2012-04-13 2013-10-17 Taiwan Semiconductor Co., Ltd. Trenched semiconductor structure
CN105097889A (en) * 2014-05-13 2015-11-25 帅群微电子股份有限公司 Terminal structure of semiconductor element, and manufacturing method thereof
US20200006580A1 (en) * 2018-06-27 2020-01-02 Semiconductor Components Industries, Llc Termination structure for insulated gate semiconductor device and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130168761A1 (en) * 2011-12-30 2013-07-04 Feei Cherng Enterprise Co., Ltd. Semiconductor power device having improved termination structure for mask saving
US20130270668A1 (en) * 2012-04-13 2013-10-17 Taiwan Semiconductor Co., Ltd. Trenched semiconductor structure
CN105097889A (en) * 2014-05-13 2015-11-25 帅群微电子股份有限公司 Terminal structure of semiconductor element, and manufacturing method thereof
US20200006580A1 (en) * 2018-06-27 2020-01-02 Semiconductor Components Industries, Llc Termination structure for insulated gate semiconductor device and method

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