CN113809000A - Manufacturing method of metal connecting line and semiconductor device - Google Patents
Manufacturing method of metal connecting line and semiconductor device Download PDFInfo
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- CN113809000A CN113809000A CN202111032885.XA CN202111032885A CN113809000A CN 113809000 A CN113809000 A CN 113809000A CN 202111032885 A CN202111032885 A CN 202111032885A CN 113809000 A CN113809000 A CN 113809000A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 321
- 239000002184 metal Substances 0.000 title claims abstract description 321
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 217
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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Abstract
The invention discloses a manufacturing method of a metal connecting line and a semiconductor device. The method comprises the following steps: providing a substrate with a metal circuit layer on the surface; and etching the metal circuit layer to form at least one metal connecting line on the etched metal circuit layer. The invention can avoid the length of the metal connecting wires from being shortened, avoid the reduction of the connecting windows of the metal connecting wires, shorten the space between the metal connecting wires and reduce the volume of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a metal connecting line and a semiconductor device.
Background
At present, the process of fabricating the metal connection line in the semiconductor device includes forming an oxide layer, forming an opening in the oxide layer through the hollow pattern on the photoresist, and filling the metal connection line in the opening. However, when forming the opening in the oxide layer, due to the diffraction effect of light, the formed opening may shrink, that is, the size of the opening is smaller than the size of the pattern on the photoresist, thereby causing the metal connection line filled in the opening to be shortened, and causing the connection window (bonding window) reserved for the contact structure at the end of the metal connection line to be reduced. Therefore, the size of the pattern on the photoresist is increased in the OPC stage to ensure that the size of the metal connecting line formed meets the required requirements.
However, if the end of the metal connection line is closer to the other metal connection lines, the pattern size on the photoresist is increased, which results in a closer distance between two patterns corresponding to the two metal connection lines, i.e. the photoresist area between the two patterns is smaller, which easily causes the photoresist to have a risk of detachment. If enough distance is reserved between the two patterns corresponding to the two metal connecting lines, the distance between the two metal connecting lines is larger, and therefore the size of the semiconductor device is increased.
Disclosure of Invention
The invention provides a manufacturing method of metal connecting lines and a semiconductor device, which can avoid the length of the metal connecting lines from being shortened, avoid the reduction of connecting windows of the metal connecting lines, shorten the space between the metal connecting lines and reduce the volume of the semiconductor device.
The invention provides a manufacturing method of a metal connecting wire, which comprises the following steps:
providing a substrate with a metal circuit layer on the surface;
and etching the metal circuit layer to form at least one metal connecting line on the etched metal circuit layer.
Further preferably, a distance between two end portions of the metal connecting line is smaller than a preset distance, or a distance between an end portion of the metal connecting line and an adjacent metal connecting line is smaller than the preset distance.
Further preferably, the step of providing a substrate with a metal wiring layer on the surface comprises:
forming a metal layer on the substrate;
and etching the metal layer to form the metal circuit layer.
Further preferably, the step of etching the metal layer to form the metal circuit layer includes:
forming a first mask layer on the metal layer;
etching the metal layer by adopting the first mask layer to obtain the metal circuit layer;
and removing the first mask layer.
Further preferably, the metal wiring layer includes a closed connection line;
the step of etching the metal circuit layer to form at least one metal connecting line on the etched metal circuit layer comprises the following steps:
an opening is formed in the closed connecting line so that the closed connecting line can be etched into a first metal connecting line and a second metal connecting line, the first end portion of the first metal connecting line and the first end portion of the second metal connecting line are oppositely arranged, and the distance between the first end portion of the first metal connecting line and the first end portion of the second metal connecting line is smaller than the preset distance, and the second end portion of the first metal connecting line and the second end portion of the second metal connecting line are oppositely arranged, and the distance between the second end portion of the first metal connecting line and the second end portion of the second metal connecting line is smaller than the preset distance.
Further preferably, the step of etching the metal circuit layer includes:
forming a first insulating layer covering the metal circuit layer on the substrate;
and etching the metal circuit layer and the first insulating layer.
Further preferably, the step of etching the metal circuit layer and the first insulating layer includes:
forming a second mask layer on the first insulating layer;
etching the metal circuit layer and the first insulating layer by adopting the second mask layer;
and removing the second mask layer.
Further preferably, the method further comprises:
and filling a second insulating layer in the etched metal circuit layer and the etched first insulating layer.
Further preferably, the material of the metal circuit layer is tungsten.
The present invention also provides a semiconductor device comprising:
a substrate; and the number of the first and second groups,
at least one metal connection line on the substrate; the distance between the two end parts of the metal connecting line is smaller than a preset distance, or the distance between the end part of the metal connecting line and the adjacent metal connecting line is smaller than the preset distance.
Further preferably, the at least one metal connection line comprises a first metal connection line and a second metal connection line;
the first end of the first metal connecting line and the first end of the second metal connecting line are oppositely arranged, and the distance between the first end of the first metal connecting line and the first end of the second metal connecting line is smaller than the preset distance, and the second end of the first metal connecting line and the second end of the second metal connecting line are oppositely arranged, and the distance between the second end of the first metal connecting line and the second end of the second metal connecting line is smaller than the preset distance.
Further preferably, the semiconductor device comprises a memory array structure and a peripheral structure bonded to the memory array structure;
the metal connecting line is a metal interconnecting line in the memory array structure or the peripheral structure.
The invention has the beneficial effects that: the substrate with the metal circuit layer on the surface is provided, then the metal circuit layer is etched, at least one metal connecting wire is obtained, the problem that the length of the metal connecting wire is shortened due to the fact that the metal connecting wire is filled in an opening formed by an oxidation layer is avoided, the connecting window of the metal connecting wire and a contact hole is further prevented from being reduced, the distance between the metal connecting wires can be shortened, and the size of a semiconductor device is reduced.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a metal connection line according to an embodiment of the present invention;
fig. 2a to fig. 2n are schematic structural diagrams illustrating a method for manufacturing a metal connection line according to an embodiment of the invention;
FIG. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention
FIG. 4 is a schematic diagram of another structure of a semiconductor device according to an embodiment of the present invention
Fig. 5 is a schematic view of another structure of the semiconductor device according to the embodiment of the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in fig. 1, the present embodiment provides a method for manufacturing a metal connection line, where the method includes steps 101 to 102, and specifically includes the following steps:
In the embodiment of the invention, the metal connecting wire can be applied to a semiconductor device, and the semiconductor device can comprise a storage array structure and a peripheral structure bonded with the storage array structure. The substrate may be a substrate in a memory array structure or a substrate in a peripheral structure. It should be noted that the metal connection line may also be applied to other devices, and is not limited herein.
When the base is a base in a memory array structure, the base may include a first substrate and a stack layer on the first substrate. The first substrate may be a semiconductor substrate, for example, a silicon substrate, or may be a substrate including another element semiconductor or a compound semiconductor. The stacked layer includes a plurality of gate layers and interlayer insulating layers alternately stacked in a vertical direction, where the vertical direction refers to a direction perpendicular to the upper surface of the first substrate, and the number of stacked layers of the gate layers and the interlayer insulating layers is not limited, for example, 48 layers, 64 layers, and the like. The base may also include a memory channel structure extending longitudinally through the stacked layers and into the first substrate. The memory channel structure may include an insulating layer, a channel layer disposed around the insulating layer, and a memory medium layer disposed around the channel layer, which will not be described in detail herein.
When the base is a base in the peripheral structure, the base may include a second substrate. The second substrate may be a semiconductor substrate, for example, a silicon substrate, or a substrate including another element semiconductor or a compound semiconductor.
The surface of the substrate is provided with a metal circuit layer, and the metal circuit layer can be obtained by etching the metal layer. Specifically, the providing a substrate with a metal circuit layer on the surface in step 101 includes:
forming a metal layer on the substrate;
and etching the metal layer to form the metal circuit layer.
As shown in fig. 2a, a metal layer 2 is formed on a substrate 1, and the metal layer 2 completely covers the substrate 1. Specifically, the metal layer 2 is deposited on the substrate 1 using a Deposition process, for example, a Physical Vapor Deposition (PVD) process. It should be noted that, the metal layer 2 formed by the physical vapor deposition process can reduce the resistance of the metal connection line formed subsequently by the metal layer 2. Preferably, the material of the metal layer 2 is metal tungsten.
And then, etching the metal layer by adopting the first mask layer. Specifically, the step of etching the metal layer to form the metal circuit layer includes:
forming a first mask layer on the metal layer;
etching the metal layer by adopting the first mask layer to obtain the metal circuit layer;
and removing the first mask layer.
As shown in fig. 2b, a first mask layer 3 is formed on the metal layer 2, and the first mask layer 3 includes a hard mask layer 31, an anti-reflection layer 32 and a photoresist layer 33 sequentially on the metal layer 2. The hard mask layer 31 may be amorphous carbon, and the anti-reflection layer 32 may be silicon oxynitride SiON. The photoresist layer 33 has a hollow pattern 34 thereon.
The metal layer 2 is primarily etched through the hollowed-out pattern 34 to obtain the metal circuit layer 20, as shown in fig. 2 c. The metal wiring layer 20 may include a closed connection line. Wherein, closed connecting line means end to end's connecting line, and closed connecting line is the closed shape. Preferably, as shown in fig. 2d, fig. 2d is a top view of the metal wiring layer 20. The metal lines in the metal line layer 20 are in a closed shape, such as a zigzag shape.
And 102, etching the metal circuit layer to form at least one metal connecting line on the etched metal circuit layer.
In the embodiment of the present invention, the metal layer 2 is etched for the second time, that is, the metal circuit layer 20 is etched, so that the metal circuit layer 20 is cut into at least one metal connection line. The distance between the two end parts of the metal connecting line is smaller than a preset distance, or the distance between the end part of the metal connecting line and the adjacent metal connecting line is smaller than the preset distance.
When the metal layer is preliminarily etched to be the metal circuit layer, metal between two end parts of the metal connecting line is not etched, or metal between the end part of the metal connecting line and the adjacent metal connecting line is not etched, so that the problem of shortening of the length of the metal connecting line cannot occur in preliminary etching.
In the etching process of the second time, only need carry out the sculpture to the metal between the both ends of metal connecting wire, perhaps carry out the sculpture to the tip of metal connecting wire and the metal between other metal connecting wires, effectively guarantee the sculpture precision, avoid the length of metal connecting wire to shorten, and then avoid metal connecting wire tip to reserve the connection window who gives the contact structure and reduce, and interval between the metal connecting wire can be less than preset distance, effectively shorten the interval between the metal connecting wire, reduce semiconductor device's volume, accord with semiconductor device's development trend.
The etching of the metal circuit layer 20 requires filling a first insulating layer between the metal circuits of the metal circuit layer 20 and then etching. Specifically, the step of etching the metal circuit layer includes:
forming a first insulating layer covering the metal circuit layer on the substrate;
and etching the metal circuit layer and the first insulating layer.
As shown in fig. 2e, the first insulating layer 4 is formed on the substrate 1 and the metal wiring layer 20, i.e. the first insulating layer 4 is formed between the metal wirings in the metal wiring layer 20 and on the metal wiring layer 20 to ensure the flatness of the upper surface on which the first insulating layer 4 is formed. The material of the first insulating layer 4 may be an oxide such as silicon oxide.
After the first insulating layer 4 is formed, the metal line layer 20 and the first insulating layer 4 may be etched using the second mask layer. Specifically, the step of etching the metal line layer and the first insulating layer includes:
forming a second mask layer on the first insulating layer;
etching the metal circuit layer and the first insulating layer by adopting the second mask layer;
and removing the second mask layer.
As shown in fig. 2f, a second mask layer 5 is formed on the first insulating layer 4, and the second mask layer 5 includes a hard mask layer 51, an anti-reflection layer 52 and a photoresist layer 53 sequentially formed on the first insulating layer 4. The hard mask layer 51 may be amorphous carbon, and the anti-reflection layer 52 may be silicon oxynitride SiON. The photoresist layer 53 has a hollowed-out pattern 54 thereon. Preferably, the metal wiring layer 20 includes a closed connection line. At least one opening is formed in the closed connection line through the hollowed-out pattern 54 to etch the closed connection line into at least one metal connection line.
In one embodiment, the number of the hollow patterns 54 is two, the metal circuit layer 20 and the first insulating layer 4 are etched through the hollow patterns 54 to form two openings in the metal circuit layer 20 and the first insulating layer 4, and the metal circuit layer 20 is divided into two metal connection lines by the two openings.
For example, as shown in fig. 2d, the metal circuit layer 20 has two hollow patterns 54, and orthogonal projections of the two hollow patterns 54 on the metal circuit layer 20 respectively cover two connecting line segments 22a and 22b in the metal circuit layer 20, as shown in fig. 2g, and fig. 2g is a top view of the photoresist layer 53. Through the two hollowed-out patterns 54, the first insulating layer 4 corresponding to the connection line segment 22a and the connection line segment 22a, the first insulating layer 4 corresponding to the connection line segment 22b, and the first insulating layer 4 corresponding to the connection line segment 22b are etched to form two openings 6 in the metal circuit layer 20 and the first insulating layer 4, and each opening 6 longitudinally penetrates through the metal circuit layer 20 and the first insulating layer 4. The metal line layer 20 is cut through the two openings 6 into a first metal connection line 21a and a second metal connection line 21b, as shown in the top view of fig. 2 h.
Because the hollow patterns 54 on the photoresist layer 53 can only correspond to the positions of the connecting line segments 22a and 22b, the size of the patterns 54 is small, the coverage area of the photoresist is ensured to be large, and the photoresist is prevented from being separated.
Further, the method further comprises:
and filling a second insulating layer in the etched metal circuit layer and the etched first insulating layer.
Due to the etching of the metal circuit layer and the first insulating layer, the second insulating layer needs to be filled in the etched metal circuit layer and the etched first insulating layer, so that the upper surface of the second insulating layer is flush with the upper surface of the first insulating layer.
As shown in fig. 2i, on the basis of fig. 2h, the opening 6 is filled with the second insulating layer 7, so that the upper surface of the second insulating layer 7 is flush with the upper surface of the first insulating layer 4. Subsequently, a contact structure may be formed in the first insulating layer 4, so that the metal connection line is connected with other metal layers through the contact structure.
In another embodiment, the metal wiring layer 20 is shown in fig. 2 d. The number of the hollow patterns 54 on the photoresist layer 53 of the second mask layer 5 is one, and the orthographic projection of the patterns 54 on the metal circuit layer 20 covers two connecting line segments 22a and 22b in the metal circuit layer 20. The pattern 54 extends transversely through the photoresist layer 53, the transverse direction being a direction A parallel to the upper surface of the substrate 1, as shown in FIG. 2j, where FIG. 2j is a top view of the photoresist layer 53.
Through the pattern 54, the connection line segments 22a and 22b in the metal circuit layer 20 and the first insulating layer 4 are etched to form an opening 6 penetrating through the first insulating layer 4 in both a transverse direction and a longitudinal direction, as shown in fig. 2k, where the transverse direction is a direction a parallel to the upper surface of the substrate 1, that is, an arrangement direction a of the connection line segments 22a and the connection line segments 22b, and the longitudinal direction is a direction perpendicular to the upper surface of the substrate 1. The length of the opening 6 (i.e., the length of the opening 6 in the direction a) is the same as the length of the first insulating layer 4 in the direction a, the width of the opening 6 (i.e., the length of the opening 6 in the direction B) is the same as the length of the connecting line segment 22a in the direction B (i.e., the distance between the first end of the first metal connecting line 21a and the first end of the second metal connecting line 21B), and is smaller than a predetermined distance, and the direction B is perpendicular to the direction a. Through the etching of the opening 6, the metal wiring layer 20 is etched into the first metal connection line 21a and the second metal connection line 21 b.
Because the length of the opening 6 is longer and the width is narrower, the retraction of the opening 6 in the width direction (i.e. the direction B) can be ignored, and the retraction of the opening 6 in the length direction (i.e. the direction a) has no influence on the metal connection line, so that the length of the etched metal connection line can be further ensured to meet the requirement by etching the opening 6, and the space between the metal connection lines is shortened, thereby reducing the volume of the semiconductor device.
Then, on the basis of fig. 2k, as shown in fig. 2l, the second insulating layer 7 is filled in the opening 6, so that the upper surface of the second insulating layer 7 is flush with the upper surface of the first insulating layer 4. Subsequently, a contact structure may be formed in the first insulating layer 4, so that the metal connection line is connected with other metal layers through the contact structure.
It should be noted that, when the metal circuit layer 20 is shown in fig. 2d, the number of the hollow patterns 54 on the photoresist layer 53 may also be one, and the orthographic projection of the pattern 54 on the metal circuit layer 20 only covers one connecting line segment in the metal circuit layer 20. The connecting line segment in the metal circuit layer 20 and the corresponding first insulating layer 4 on the connecting line segment are etched through the pattern 54, so that the metal circuit layer 20 is etched into a non-closed connecting line with an opening. The non-closed connecting line is a metal connecting line, i.e. a third metal connecting line 21c, two end portions of the third metal connecting line 21c are oppositely arranged, and a distance between the two end portions of the third metal connecting line 21c is smaller than a preset distance, as shown in fig. 2 m. Then, the second insulating layer 7 is filled in the etched metal circuit layer 20 and the first insulating layer 4, so that the upper surface of the second insulating layer 7 is flush with the upper surface of the first insulating layer 4.
The metal circuit layer 20 may also include other connecting lines, such as T-shaped connecting lines, which include connected horizontal connecting lines and vertical connecting lines. The number of the hollow patterns 54 on the photoresist layer 53 may be one, and the orthographic projection of the patterns 54 on the metal circuit layer 20 covers the line segment where the vertical connecting line is connected with the horizontal connecting line. The line segment in the metal line layer 20 and the corresponding first insulating layer 4 on the line segment are etched through the pattern 54 to form an opening at one end where the vertical connecting line is connected with the transverse connecting line, the metal line layer 20 is etched into two connecting lines which are not connected with each other, the two connecting lines are two metal connecting lines, namely a fourth metal connecting line 21d and a fifth metal connecting line 21e, and the distance between the end of the fifth metal connecting line 21e and the fourth metal connecting line 21d is smaller than the preset distance, as shown in fig. 2 n.
It should be noted that the shape of the metal circuit in the metal circuit layer 20 may be set according to actual requirements, the number and the position of the openings etched in the metal circuit layer 20 are different, and the shape and the number of the obtained metal connection lines are different, which is not specifically limited herein.
When the substrate 1 is a substrate in a memory array structure, the metal connection lines may be metal interconnection lines, such as bit lines, in a back-end process of the memory array structure; when the substrate 1 is a substrate in a peripheral structure, the metal connection line may be a metal interconnection line in a back-end process of the peripheral structure.
According to the manufacturing method of the metal connecting wire, provided by the embodiment of the invention, the substrate with the metal circuit layer on the surface is provided, then the metal circuit layer is etched to obtain at least one metal connecting wire, the problem that the length of the metal connecting wire is shortened due to the fact that the metal connecting wire is filled in the opening formed by the oxide layer is solved, the connection window of the metal connecting wire and the contact hole is further prevented from being reduced, the space between the metal connecting wires can be shortened, and the size of a semiconductor device is reduced.
Referring to fig. 3, an embodiment of the present invention further provides a semiconductor device, including:
a substrate 1; and the number of the first and second groups,
at least one metal connection line 21 on the substrate 1; the distance between the two ends of the metal connecting line 21 is smaller than a preset distance, or the distance between the end of the metal connecting line 21 and the adjacent metal connecting line 21 is smaller than a preset distance.
The semiconductor device may include a memory array structure and a peripheral structure bonded to the memory array structure. The substrate may be a substrate in a memory array structure or a substrate in a peripheral structure. When the base is a base in the memory array structure, the base may include a first substrate and a stack layer located on the first substrate, and the metal connection line may be a metal interconnection line in a back-end process in the memory array structure; when the base is a base in the peripheral structure, the base may include a second substrate, and the metal connection line may be a metal interconnection line of a back-end process in the peripheral structure.
Specifically, as shown in fig. 3, the at least one metal connection line may include a first metal connection line 21a and a second metal connection line 21 b. The first end of the first metal connecting line 21a and the first end of the second metal connecting line 21b are oppositely disposed and the distance D1 is less than a preset distance, and the second end of the first metal connecting line 21a and the second end of the second metal connecting line 21b are oppositely disposed and the distance D2 is less than a preset distance.
As shown in fig. 4, the at least one metal connecting line may also include a third metal connecting line 21c, two end portions of the third metal connecting line 21c are oppositely disposed, and a distance D3 between the two end portions of the metal connecting line 21c is smaller than a predetermined distance.
As shown in fig. 5, the at least one metal connecting line may also include a fourth metal connecting line 21D and a fifth metal connecting line 21e, and a distance D4 between an end of the fifth metal connecting line 21e and the fourth metal connecting line 21D is less than a preset distance.
The number and the position of the metal connecting wires can be set according to actual requirements, and the distance between at least one end part of the metal connecting wires and other end parts or other metal connecting wires is only required to be ensured to be smaller than a preset distance, so that specific limitation is not made here.
In addition, an insulating layer (not shown) may be further disposed on the substrate 1 and the metal connection line 21, so that a contact structure may be formed in the insulating layer in the following, so that the metal connection line 21 is connected to other metal layers through the contact structure.
Through shortening the interval between the metal connecting wire, can set up more metal connecting wires under the same semiconductor device volume, perhaps can reduce semiconductor device's volume under the prerequisite of same metal connecting wire, accord with semiconductor device and develop towards the direction of less volume.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (12)
1. A manufacturing method of a metal connecting line is characterized by comprising the following steps:
providing a substrate with a metal circuit layer on the surface;
and etching the metal circuit layer to form at least one metal connecting line on the etched metal circuit layer.
2. The method of claim 1, wherein a distance between two ends of the metal connection line is less than a predetermined distance, or a distance between an end of the metal connection line and an adjacent metal connection line is less than the predetermined distance.
3. The method for manufacturing a metal interconnection line according to claim 1, wherein the step of providing the substrate having the metal wiring layer on the surface thereof comprises:
forming a metal layer on the substrate;
and etching the metal layer to form the metal circuit layer.
4. The method of claim 3, wherein the step of etching the metal layer to form the metal circuit layer comprises:
forming a first mask layer on the metal layer;
etching the metal layer by adopting the first mask layer to obtain the metal circuit layer;
and removing the first mask layer.
5. The method of claim 1, wherein the metal circuit layer comprises a closed connection line;
the step of etching the metal circuit layer to form at least one metal connecting line on the etched metal circuit layer comprises the following steps:
an opening is formed in the closed connecting line so that the closed connecting line can be etched into a first metal connecting line and a second metal connecting line, the first end portion of the first metal connecting line and the first end portion of the second metal connecting line are oppositely arranged, and the distance between the first end portion of the first metal connecting line and the first end portion of the second metal connecting line is smaller than the preset distance, and the second end portion of the first metal connecting line and the second end portion of the second metal connecting line are oppositely arranged, and the distance between the second end portion of the first metal connecting line and the second end portion of the second metal connecting line is smaller than the preset distance.
6. The method for manufacturing a metal connection line according to claim 1, wherein the step of etching the metal circuit layer includes:
forming a first insulating layer covering the metal circuit layer on the substrate;
and etching the metal circuit layer and the first insulating layer.
7. The method of claim 6, wherein the step of etching the metal circuit layer and the first insulating layer comprises:
forming a second mask layer on the first insulating layer;
etching the metal circuit layer and the first insulating layer by adopting the second mask layer;
and removing the second mask layer.
8. The method of making a metal interconnect line of claim 6, further comprising:
and filling a second insulating layer in the etched metal circuit layer and the etched first insulating layer.
9. The method as claimed in any one of claims 1 to 8, wherein the metal wiring layer is made of tungsten.
10. A semiconductor device, comprising:
a substrate; and the number of the first and second groups,
at least one metal connection line on the substrate; the distance between the two end parts of the metal connecting line is smaller than a preset distance, or the distance between the end part of the metal connecting line and the adjacent metal connecting line is smaller than the preset distance.
11. The semiconductor device of claim 10, wherein the at least one metal connection line comprises a first metal connection line and a second metal connection line;
the first end of the first metal connecting line and the first end of the second metal connecting line are oppositely arranged, and the distance between the first end of the first metal connecting line and the first end of the second metal connecting line is smaller than the preset distance, and the second end of the first metal connecting line and the second end of the second metal connecting line are oppositely arranged, and the distance between the second end of the first metal connecting line and the second end of the second metal connecting line is smaller than the preset distance.
12. The semiconductor device of claim 10, wherein the semiconductor device comprises a memory array structure and a peripheral structure bonded to the memory array structure;
the metal connecting line is a metal interconnecting line in the memory array structure or the peripheral structure.
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