US20190371655A1 - Methods of Forming Metal Layer Structures in Semiconductor Devices - Google Patents
Methods of Forming Metal Layer Structures in Semiconductor Devices Download PDFInfo
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- US20190371655A1 US20190371655A1 US15/993,691 US201815993691A US2019371655A1 US 20190371655 A1 US20190371655 A1 US 20190371655A1 US 201815993691 A US201815993691 A US 201815993691A US 2019371655 A1 US2019371655 A1 US 2019371655A1
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Definitions
- Self-aligned double patterning or multiple patterning techniques are used to define conductive lines.
- the existing metal line forming techniques have tight process window and can result in the formation of relatively short dummy conductive lines that lead to increased parasitic capacitance. Accordingly, improvements in these areas are desired.
- FIG. 1 is a flowchart illustrating a method for fabricating conductive features on a substrate according to aspects of the present disclosure.
- FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 illustrate perspective views of a substrate that undergoes operations of the method in FIG. 1 , according to aspects of the present disclosure.
- FIGS. 14 and 15 illustrate perspective views of a substrate that undergoes operations of the method in FIG. 1 , according to another aspect of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- FIG. 1 Illustrated in FIG. 1 is a method 100 of fabricating conductive features of a semiconductor device on a substrate.
- the method 100 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operation can be provided before, during, and after the method 100 , and some operations can be replaced, eliminated, or moved around for additional embodiments of the method.
- the method 100 is described below in conjunction with FIGS. 2-15 , which are perspective views of a substrate in various stages of a fabrication process.
- the conductive features may be a part of an interconnect structure such as a multi-layer interconnect (MLI) structures.
- MLI multi-layer interconnect
- CMOS complementary metal-oxide-semiconductor
- the semiconductor device may include various other devices and features, such as field effect transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure.
- 2-15 may be an intermediate device fabricated during processing of an integrated circuit, or portion thereof, that may comprise static random access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field effect transistors (PFET), N-channel FET (NFET), metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.
- SRAM static random access memory
- PFET P-channel field effect transistors
- NFET N-channel FET
- MOSFET metal-oxide semiconductor field effect transistors
- CMOS complementary metal-oxide semiconductor
- the semiconductor device of FIGS. 2-15 may include multi-gate transistors or fin-type multi-gate transistors referred to herein as FinFET devices.
- Such a device may include a P-type FinFET device or an N-type FinFET device.
- the FinFET device may be a dual-gate device or a tri-gate device, built on a bulk substrate or a silicon-on-insulator (SOI) substrate.
- SOI silicon-on-insulator
- GAA gate-all-around
- ⁇ -gate Omega-gate
- ⁇ -gate Pi-gate
- nano-wire gate devices and nano-sheet gate devices.
- a planar device may be fabricated using one or more of the structures or methods discussed herein.
- the fins in FinFET semiconductor devices may be patterned by any suitable method.
- the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
- the semiconductor device of FIGS. 2-15 includes a plurality of passive and/or active components (e.g., transistors), which may be interconnected.
- the components may be interconnected using an interconnect structure formed according to the method 100 .
- the interconnect structure may provide a physical and/or electrical connection between components and/or between a component and a pad providing an external connection (e.g., to a package).
- An interconnect structure such as an MLI structure includes a plurality of conductive lines formed in various layers (e.g., metal 1 , metal 2 ) with conductive vias interconnecting the lines.
- An interconnect structure further includes one or more dielectric material (for example, interlayer dielectric (ILD) layers) to provide isolation between conductive features.
- ILD interlayer dielectric
- the method 100 receives a workpiece 200 (or device 200 ) such as shown in FIG. 2 .
- the device 200 includes a substrate 202 .
- the substrate 202 may be a semiconductor wafer that includes a plurality of layers.
- the semiconductor wafer includes silicon.
- the substrate 202 may include another elementary semiconductor, such as germanium Ge; a compound semiconductor including silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof.
- the substrate 202 includes a semiconductor on insulator (SOI).
- the substrate 202 may include a non-semiconductor material such as a glass substrate, fused quartz substrate, and/or other suitable materials.
- the substrate 202 may also include various features such as doped regions, dielectric features, conductive features such as multi-layer interconnects, and/or other suitable features (not shown).
- the substrate 202 includes features forming various semiconductor devices such as, for example, complementary metal-oxide-semiconductor field effect transistors (CMOSFET), imaging sensors, capacitors, memory cells, diodes, fin-type field-effect transistors (FINFETs), and/or other suitable devices.
- CMOSFET complementary metal-oxide-semiconductor field effect transistors
- imaging sensors e.g., imaging sensors, capacitors, memory cells, diodes, fin-type field-effect transistors (FINFETs), and/or other suitable devices.
- CMOSFET complementary metal-oxide-semiconductor field effect transistors
- FINFETs fin-type field-effect transistors
- the device 200 includes a plurality of layers formed over the substrate 202 .
- the device 200 includes a base layer 204 , a dielectric layer 206 , a first hard mask layer 208 , an etch stop layer (ESL) 210 , and a second hard mask layer 212 .
- these layers are exemplary and not intended to be limiting; one or more of the layers may be omitted, and additional layers may be added.
- one or more anti-reflective coating layers or ESL layers may be inserted between two of the layers illustrated in FIGS. 2-12 .
- Example compositions for the layers formed on the substrate 202 are provided below, however, except as specifically defined by the claims hereto, these compositions are merely examples and not intended to be limiting.
- the base layer 204 includes a dielectric material such as a low-k or an extreme low-k (ELK) dielectric material.
- ELK materials include dielectric materials having a dielectric constant k less than approximately 2.
- the base layer 204 may include dielectric materials such as, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.
- the layer may be deposited by a plasma enhanced chemical vapor deposition (PECVD) process or other suitable deposition technique.
- the base layer 204 may be an interlayer dielectric (ILD) layer or of a MLI structure.
- metallization layer may be formed within the base layer 204 .
- the dielectric layer 206 may include dielectric materials such as, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.
- TEOS tetraethylorthosilicate
- BPSG borophosphosilicate glass
- FSG fused silica glass
- PSG phosphosilicate glass
- BSG boron doped silicon glass
- the first and second hard mask layers 208 and 212 include a hard mask material, such as titanium oxide (Ti x O y ), tantalum oxide (Ta x O y ), titanium nitride (Ti x N y ), silicon nitride (Si x N y ), and silicon oxide (Si x O y ).
- a hard mask material such as titanium oxide (Ti x O y ), tantalum oxide (Ta x O y ), titanium nitride (Ti x N y ), silicon nitride (Si x N y ), and silicon oxide (Si x O y ).
- the ESL layer 210 may be formed of a dielectric material, such as silicon carbide (Si x C y ), silicon nitride (Si x N y ), silicon oxynitride (Si x O y N z ), silicon oxycarbide (Si x O y C z ), or combination thereof.
- the X and Y in the chemical formulae can be stoichiometric or can depend on the amount of precursors used to form the ESL layer 210 .
- the ESL layer 210 may include multiple etch stop layers formed of aforementioned dielectric materials.
- the ESL layer 210 may experience slower etch rate in an etching process. That way, when the hard mask layer 212 is etched, the etching process can substantially come to a stop within or near a boundary of the ESL layer 210 .
- the layers 204 , 206 , 208 , 210 , and/or 212 may be formed by suitable processes such as, for example, chemical vapor deposition (CVD) including PECVD, low-pressure CVD (LPCVD), or high density plasma CVD (HDP-CVD) process; spin-on coating; sputtering; physical vapor deposition (PVD); atomic layer deposition (ALD); and/or other suitable processes.
- CVD chemical vapor deposition
- LPCVD low-pressure CVD
- HDP-CVD high density plasma CVD
- PVD physical vapor deposition
- ALD atomic layer deposition
- a plurality of openings 214 may be optionally formed on the second hard mask layer 212 .
- Each of the plurality of openings 214 extends along a direction that is perpendicular to the direction of the to-be-formed conductive features. In the embodiment represented in FIG. 3 , the plurality of openings 214 extend along the Y direction.
- One-directional openings such as opening 214 can be formed with good precision.
- the plurality of openings 214 may result in formation of hard mask features that separate metal lines. For that reason, the formation of the plurality of openings 214 may be referred to as a first cut metal etch.
- a bottom antireflective coating (BARC) 216 may be formed over the second hard mask layer 212 .
- the BARC layer 216 may be formed of silicon oxynitride (SiON), a polymer, other suitable materials, or a combination thereof, using CVD, spin-on processes, or other suitable processes.
- Photoresist lines 218 are formed over the BARC layer 216 . Each of the photoresist lines 218 extends parallel along the X direction. The photoresist lines 218 may be formed using suitable processes. For example, a photoresist layer 218 may be formed on the BARC layer 216 by spin-on coating.
- the photoresist layer 218 may be then be exposed and developed by suitable lithography chemistry to turn into photoresist lines 218 . After the photoresist lines 218 are developed, they may be subject to post-bake processes. Then the BARC layer 216 and the second hard mask layer 212 are etched using the plurality of photoresist lines 218 as the etch mask. As shown in FIG. 5 , because the ESL 210 below the second hard mask layer 212 experiences a slower etch rate than the second hard mask layer 212 , the second hard mask layer 212 not under the plurality of photoresist lines 218 is removed, leaving a first plurality of hard mask lines 2120 over the ESL 210 . The openings 214 in FIG. 3 leave behind hard mask line cuts 2140 in FIG. 5 , dividing the hard mask line 2123 into segments.
- a spacer material layer 220 is formed over the first plurality of hard mask lines 2120 and the ESL 210 .
- the spacer material layer 220 is conformally formed and may also be referred to as a conformal layer 220 .
- the spacer material layer 220 is formed not only over top surfaces of the hard mask lines 2120 but also over sidewalls of the hard mask lines 2120 .
- the spacer material layer 220 over the sidewalls of the hard mask lines 2120 will result in spacer layers 2200 left behind after the hard mask lines 2120 is removed from the device 200 .
- the spacer material layer 220 may include a dielectric material, such as silicon dioxide (Si x O y ), silicon nitride (Si x N y ), silicon oxynitride (Si x O y N z ), and/or other suitable dielectric materials.
- the X and Y in the chemical formulae can be stoichiometric or can depend on the amount of precursors used to form the spacer material layer 220 . It is noted that because the spacer material layer 220 is conformal in nature, it also fills in the hard mask line cuts 2140 ( FIG. 5 ).
- the portions of the spacer material layer 220 filled in the hard mask line cuts 2140 create spacers that divide the hard mask line 2123 into segments.
- the spacer material layer 220 formed over the hard mask lines 2120 include spacer layer trenches 2210 , 2220 and 2230 .
- the method 100 of FIG. 1 proceeds to block 108 where a bottom antireflective coating (BARC) layer 222 is formed over the spacer material layer 220 .
- the BARC layer 222 may be formed of silicon oxynitride (SiON), a polymer, other suitable materials, or a combination thereof, using CVD, spin-on processes, or other suitable processes.
- the BARC layer 222 fills in the spacer layer trenches 2210 , 2220 and 2230 .
- the method 100 then proceeds to block 110 where an L-shaped opening (or L-shaped pattern) 224 is formed by removing the BARC layer 222 within the L-shaped opening 224 .
- a photoresist layer may be deposited over the BARC layer 222 .
- the photoresist layer can be exposed and developed to have an L-shaped opening corresponding to the L-shaped opening 224 and the BARC layer 222 is etched using the photoresist layer as an etch mask.
- the L-shaped opening 224 resembles an axe and may be referred to as the axe-shaped opening 224 .
- the L-shaped openings 224 may result in formation of fill material features that separate metal lines. For that reason, the formation of the L-shaped openings 224 may be referred to as a second cut metal etch.
- the L-shaped opening 224 is over the spacer layer trenches 2210 and 2220 and includes a first line-shaped portion 2241 (or first line portion 2241 ) and a second line-shaped portion 2242 (or second line portion 2242 ).
- the first line-shaped portion 2241 is perpendicular to the second line-shaped portion 2242 .
- the second line-shaped portion 2242 extends from an end of the first line-shaped portion 2241 .
- the first line-shaped portion 2241 extends parallel to and over the spacer layer trench 2220 .
- a width W of the first line-shaped portion 2241 can have a minimum equal to a width of the spacer layer trench 2220 in order to full expose the spacer layer trench 2220 .
- the width W of the first line-shaped portion 2241 can have a maximum equal to a pitch of the hard mask lines 2120 such that the first line-shaped opening does not expose an adjacent spacer layer trench, such as the spacer layer trench 2210 . That is, edges of the first line-shaped portion 2241 that define the width W can be over the spacer material layers 220 .
- the large range of the width W widens the process window of the method 100 .
- the second line-shaped portion 2242 spans over the hard mask line 2121 , the hard mask line 2122 , the spacer layer trenches 2210 and 2220 .
- the first line-shaped portion 2241 includes a length P.
- the device 200 includes a plurality of standard cells. Each of the standard cells includes gates of semiconductor devices that are disposed at a pitch. The pitch is substantially identical to the length P.
- the L-shaped opening 224 may be formed using one mask that includes an L-shaped pattern that resembles the L-shaped opening 224 .
- the L-shaped opening 224 may be formed using two separate masks: a first mask that includes a line pattern that resembles the first line-shaped portion 2241 and a second mask that includes a line pattern that resembles the second line-shaped portion 2242 . While only one L-shaped opening 224 is shown in FIG. 7 , multiple L-shaped openings that are substantially similar to the L-shaped opening 224 may be advantageously formed on the BARC layer 222 .
- L-shaped openings are described in the present disclosure, openings of other shapes that include two line-shaped portions coupled to one another are envisioned by the present disclosure.
- the first line-shaped portion 2241 can end in and connect to a middle portion of the second line-shaped portion 2242 , thus making the L-shaped opening appear like a T-shaped opening.
- the middle portion refers to any portion that is between the two terminal ends of a line-shaped portion.
- the method 100 can include additional operations between operations in block 108 and operations in block 110 . These additional operations are performed by a computer system that can access a layout of the device 200 . Based on the layout of the device 200 , such computer system can determine locations of metal line cuts. Taking the device 200 in FIG. 7 as an example, the metal line cuts include a first metal line cut located at an end 2243 of the first line-shaped portion 2241 and a second metal line cut that coincides with the second line-shaped portion 2242 .
- the first metal line cut 2243 will result in a cut of a metal line to be formed under the spacer layer trench 2220 and the second metal line cut 2242 will result in a cut of two metal lines to be formed under both the spacer layer trenches 2210 and 2220 .
- the computer system can then determine if a metal line segment between the first metal line cut 2243 and the second metal line cut 2242 (i.e. the metal line under the first line-shaped portion 2241 ) is functional. If the metal line segment is not functional (i.e. a dummy line), the method 100 will proceed to block 110 where the L-shaped opening will eventually result in the removal or non-formation of the dummy line under the first line-shaped portion 2241 .
- the method 100 does not apply to this specific location and only the portions of the BARC layer 222 that correspond to the first metal line cut 2243 and the second metal line cut 2242 will be removed.
- the method 100 then proceeds to block 112 where the L-shaped opening 224 is filled with a fill material 2240 .
- the fill material 2240 may be a silicon-containing antireflective coating (Si-ARC).
- the Si-ARC can include inorganic ARCs such as SiON, silicon containing organic ARCs such as polysilanes, and/or other suitable compositions.
- the silicon content is between approximately 30 and 40 atomic weight percent.
- the spacer layer trenches 2210 and 2220 may be filled using a spin-coating or other suitable deposition process.
- the fill material 2240 may also be referred to as reverse material 2240 .
- the method 100 proceeds to block 114 where the BARC layer 222 is removed.
- the device 200 is planarized by, for example, the use of a chemical mechanical polishing (CMP) process. Any excess fill material 2240 that is not in the spacer layer trenches 2210 and 2220 can be removed in the planarization process, resulting in a planar surface.
- CMP chemical mechanical polishing
- the BARC layer 222 is also planarized such that a top surface of the BARC layer 222 is flush with a top surface of the plurality of spacers 2200 .
- the planarized BARC layer 222 is then selectively etched away without substantially etching the fill material feature 2245 and 2247 .
- the BARC layer 222 and the fill material 2240 have different compositions.
- the BARC layer 222 can be a polymer and the fill material 2240 can be inorganic ARC such as SiON.
- the method 100 proceeds to block 116 where the spacer material layer 220 are etched back to expose the first plurality of hard mask lines 2120 .
- the hard mask lines 2120 are exposed and a plurality of spacers 2200 over the sidewalls of the hard mask lines 2120 are formed.
- the spacers 2200 may be said to track the hard mask lines 2120 .
- the portion of the spacer material layer 220 on the ESL layer 210 is also removed at block 116 .
- the hard mask line 2123 is separated by spacer material features 226 into segments.
- the spacers 2200 that track the hard mask lines 2120 also define spacer layer trenches 2210 , 2220 and 2230 .
- the transferred patterns of the spacer layer trenches 2210 , 2220 and 2230 will be filled with conductive materials to form conductive lines.
- the method 100 proceeds to block 118 where the hard mask lines 2120 are removed or stripped off the device 200 to form trenches 2310 , 2320 , 2330 , and 2340 .
- This process may include an etch-back process such as a wet etch, dry etch, plasma etch, and/or other suitable process.
- the material of the fill material 2240 (including fill material features 2245 and 2247 ) is selected to have etching selectivity with respect to the material in the hard mask lines 2121 , 2122 , 2123 , and 2124 in FIG. 11 . This etching selectivity between the hard mask material and the fill material ensures that hard mask material is preferentially etched away while the fill material is not substantially etched.
- the spacers 2200 define not only spacer layer trenches 2210 , 2220 and 2230 but also trenches 2310 , 2320 , 2330 , and 2340 . Out of these trenches, spacer layer trench 2210 is divided by the fill material feature 2245 into two segments; spacer layer trench 2220 is divided by the fill material feature 2247 into two segments; and trench 2330 is divided by the spacer material features 226 into three segments. These trenches represent the pattern of conductive lines once all operations in method 100 are carried out.
- a pattern of the spacers 2200 and the fill material 2240 (including fill material features 2245 and 2247 ) is transferred onto an underlying layer, such as the base layer 204 .
- the transferred pattern in the base layer 204 may be used to define a conductive layer (e.g., metal line) of an interconnect structure such as by a damascene or dual-damascene process.
- the base layer 204 is anisotropically etched using the spacers 2200 and the fill material 2240 as an etch mask.
- a conductive material 280 may then be filled or plated into the trenches in the base layer 204 .
- the workpiece 200 (device 200 ) is subject to a planarization process, such as a CMP process, to planarize the top surfaces of the conductive materials 280 filled in the trenches of the base layer 204 .
- the trenches in the base layer 204 track the pattern of the spacers 2200 and the fill material 2240 .
- the metal line cut 2610 correspond to the fill material feature 2245
- the metal line cut 2620 corresponds to the fill material feature 2247
- the metal line cuts 2630 and 2640 correspond to the spacer material features 226 .
- the conductive material formed in the trenches includes copper (Cu).
- other exemplary embodiments include conductive materials such as aluminum (Al), copper alloys, tungsten (W), and/or other suitable materials.
- the anisotropic etching processes used to transfer the pattern onto the base layer 204 may include dry etch, or plasma etch processes.
- the metal line cut 2620 of the present disclosure removes a short segment of conductive line formed within the area of the metal line cut 2620 .
- such a short conductive line segment can act as a dummy metal line between two adjacent gates of a semiconductor device in a standard cell.
- a dummy metal line may reduce the performance of the semiconductor device, such as the switching speed of the semiconductor device, for example, by increasing parasitic capacitance to nearby conductive features.
- the trench 2340 may be shortened by the leftover hard mask segment 2125 . Because the trench 2340 represents a conductive line to be formed, shortening of the trench 2340 also shortens the resulting conductive line.
- the pattern of the spacer layer 2200 , the leftover hard mask segment 2125 and the fill material features 2240 are transferred to the base layer 204 .
- the leftover hard mask segment 2125 can result in a base layer segment 2650 to be formed.
- the base layer segment 2650 cuts short the conductive metal line 2802 .
- This partial hard mask line removal process can be an alternative to the first metal cut etch process described above.
- the method 100 of the present disclosure not only widens the process window but also eliminates dummy conductive lines that may affect the performance of the semiconductor device.
- the first line-shaped portion 2241 of the L-shaped opening 224 can be substantially wider than the spacer layer trench 2220 .
- the L-shaped opening 224 aids the removal of BARC layer material in the spacer layer trench 2210 and 2220 and filling of the fill material 2240 .
- the fill material 2240 fills the spacer layer trench 2220 in the first line-shaped portion 2241 , no dummy conductive line will be formed in that area as a result.
- embodiments of the method 100 provide benefits of forming functional conductive lines without the drawback of having dummy metal lines that have a length substantially identical to a pitch of gates of semiconductor devices in a standard cell.
- the embodiments of the method 100 provide large process window and increase process fidelity by forming an L-shaped opening in the second cut metal etch step.
- the present disclosure is directed to a method of forming a semiconductor device.
- the method includes providing a workpiece having a substrate, a material layer over the substrate, and a hard mask layer over the material layer.
- the method further includes patterning the hard mask layer to form a first plurality of hard mask lines and forming a spacer material layer over the first plurality of hard mask lines, resulting in a second plurality of trenches defined by the spacer material layer, wherein the second plurality of trenches tracks the first plurality of hard mask lines.
- the method further includes forming an antireflective layer over the spacer material layer, including over the second plurality of trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the second plurality of trenches; filling the L-shaped opening with a fill material; etching the spacer material layer to expose the first plurality of hard mask lines; and removing the first plurality of hard mask lines.
- the method further includes transferring a pattern of the spacer material layer and the fill material onto the material layer, resulting in trenches tracking the pattern; and filling the trenches with a conductive material.
- the L-shaped opening includes a first line portion and a second line portion, and the second line portion extends from an end of the first line portion and is perpendicular to the first line portion.
- a width of the first line portion is greater than about a width of one of the second plurality of trenches and less than about a pitch of the first plurality of hard mask lines.
- the first line portion extends parallel to and is over one of the second plurality of trenches.
- the second line portion extends across at least two of the second plurality of trenches.
- the forming of the L-shaped opening in the antireflective layer comprises forming the L-shaped opening over more than one of the second plurality of trenches.
- the removing of the first plurality of hard mask lines includes removing a portion of the first plurality of hard mask lines, thereby resulting in a leftover hard mask segment; and the transferring the pattern of the spacer material layer and fill material onto the material layer includes transferring a pattern of the leftover hard mask segment on the material layer.
- the present disclosure is directed to a method of forming a semiconductor device.
- the method includes forming a first plurality of hard mask lines over a material layer on a substrate, the first plurality of hard mask lines extending along a first direction; and forming a spacer material layer over the first plurality of hard mask lines, resulting in a second plurality of trenches extending along the first direction, each of the second plurality of trenches having sidewalls formed of the spacer material layer, wherein the second plurality of trenches tracks the first plurality of hard mask lines.
- the method further includes forming a antireflective layer over the second plurality of trenches; forming a first line-shaped opening in the antireflective layer; filling the first line-shaped opening with a fill material, wherein the first line-shaped opening extends along the first direction; etching the spacer material layer to expose the first plurality of hard mask lines; and removing the first plurality of hard mask lines.
- the method further includes transferring a pattern of the spacer material layer and the fill material onto the material layer, resulting in trenches tracking the pattern; and filling the trenches with a conductive material.
- the method further includes forming a second line-shaped opening in the antireflective layer, wherein the second line-shaped opening extends from an end of the first line-shaped opening and along a second direction perpendicular to the first direction; and filling the second line-shaped opening with the fill material.
- the first line-shaped opening extends over one of the second plurality of trenches.
- the second line-shaped opening extends across at least two of the second plurality of trenches.
- a width of the first line-shaped opening is greater than about a width of one of the second plurality of trenches of the second plurality of trenches and less than about a pitch of the first plurality of hard mask lines.
- the forming of the first line-shaped opening in the antireflective layer comprises forming the first line-shaped opening over one of the second plurality of trenches.
- the removing of the first plurality of hard mask lines includes removing a portion of the first plurality of hard mask lines, thereby resulting in a leftover hard mask segment, and the transferring the pattern of the spacer material layer and fill material onto the material layer includes transferring a pattern of the leftover hard mask segment on the material layer.
- the present disclosure is directed to a method of forming a semiconductor device.
- the method includes providing a workpiece having a substrate, a material layer over the substrate, and a hard mask layer over the material layer; patterning the hard mask layer, thereby forming a first plurality of hard mask lines; forming a spacer material layer over the first plurality of hard mask lines, resulting in a second plurality of trenches that tracks the first plurality of hard mask lines; and forming a antireflective layer over the spacer material layer, including over the second plurality of trenches.
- the method further includes forming an L-shaped opening in the antireflective layer, wherein the L-shaped opening includes a first line portion and a second line portion perpendicular to the first line portion, wherein the first line portion extends parallel to and is over one of the second plurality of trenches.
- the method further includes filling the L-shaped opening with a fill material; etching the spacer material layer to expose the first plurality of hard mask lines; and removing the first plurality of hard mask lines. After removing the first plurality of hard mask lines, the method further includes transferring a pattern of the spacer material layer and the fill material onto the material layer, resulting in trenches tracking the pattern; and filling the trenches with a conductive material.
- the second line portion extends from an end of the first line portion and is perpendicular to the first line portion. In another embodiment, the second line portion extends across at least two of the second plurality of trenches. In some embodiments, a width of the first line portion is greater than about a width of one of the second plurality of trenches of the second plurality of trenches and less than about a pitch of the first plurality of hard mask lines.
- the removing of the first plurality of hard mask lines includes removing a portion of the first plurality of hard mask lines, thereby resulting in a leftover hard mask segment, and the transferring the pattern of the spacer material layer and fill material onto the material layer includes transferring a pattern of the leftover hard mask segment on the material layer.
- the fill material comprises a line-shaped portion that fills one of the second plurality of trenches.
Abstract
Description
- The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
- Self-aligned double patterning or multiple patterning techniques are used to define conductive lines. However, the existing metal line forming techniques have tight process window and can result in the formation of relatively short dummy conductive lines that lead to increased parasitic capacitance. Accordingly, improvements in these areas are desired.
- The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 is a flowchart illustrating a method for fabricating conductive features on a substrate according to aspects of the present disclosure. -
FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 illustrate perspective views of a substrate that undergoes operations of the method inFIG. 1 , according to aspects of the present disclosure. -
FIGS. 14 and 15 illustrate perspective views of a substrate that undergoes operations of the method inFIG. 1 , according to another aspect of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable percentage (e.g., +/−10%) of the number described as understood by a person having ordinary skill in the art, unless otherwise specified. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.
- Illustrated in
FIG. 1 is amethod 100 of fabricating conductive features of a semiconductor device on a substrate. Themethod 100 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operation can be provided before, during, and after themethod 100, and some operations can be replaced, eliminated, or moved around for additional embodiments of the method. Themethod 100 is described below in conjunction withFIGS. 2-15 , which are perspective views of a substrate in various stages of a fabrication process. In an embodiment, the conductive features may be a part of an interconnect structure such as a multi-layer interconnect (MLI) structures. - It is also understood that parts of the semiconductor device of
FIGS. 2-15 may be fabricated by complementary metal-oxide-semiconductor (CMOS) technology process flow, and thus some processes are only briefly described herein. Further, the semiconductor device may include various other devices and features, such as field effect transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure. Furthermore, the semiconductor device ofFIGS. 2-15 may be an intermediate device fabricated during processing of an integrated circuit, or portion thereof, that may comprise static random access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field effect transistors (PFET), N-channel FET (NFET), metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. - It is also noted that the semiconductor device of
FIGS. 2-15 may include multi-gate transistors or fin-type multi-gate transistors referred to herein as FinFET devices. Such a device may include a P-type FinFET device or an N-type FinFET device. The FinFET device may be a dual-gate device or a tri-gate device, built on a bulk substrate or a silicon-on-insulator (SOI) substrate. One of ordinary skill in the art may recognize other embodiments of semiconductor devices that may benefit from aspects of the present disclosure. For example, some embodiments as described herein may also be applied to gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, Pi-gate (Π-gate) devices, nano-wire gate devices, and nano-sheet gate devices. In other embodiments, a planar device may be fabricated using one or more of the structures or methods discussed herein. - The fins in FinFET semiconductor devices may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
- The semiconductor device of
FIGS. 2-15 includes a plurality of passive and/or active components (e.g., transistors), which may be interconnected. The components may be interconnected using an interconnect structure formed according to themethod 100. The interconnect structure may provide a physical and/or electrical connection between components and/or between a component and a pad providing an external connection (e.g., to a package). An interconnect structure such as an MLI structure includes a plurality of conductive lines formed in various layers (e.g., metal 1, metal 2) with conductive vias interconnecting the lines. An interconnect structure further includes one or more dielectric material (for example, interlayer dielectric (ILD) layers) to provide isolation between conductive features. - At
operation 102, the method 100 (FIG. 1 ) receives a workpiece 200 (or device 200) such as shown inFIG. 2 . Referring toFIG. 2 , thedevice 200 includes asubstrate 202. Thesubstrate 202 may be a semiconductor wafer that includes a plurality of layers. In an embodiment, the semiconductor wafer includes silicon. Alternatively, thesubstrate 202 may include another elementary semiconductor, such as germanium Ge; a compound semiconductor including silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. In yet another alternative, thesubstrate 202 includes a semiconductor on insulator (SOI). Alternatively, thesubstrate 202 may include a non-semiconductor material such as a glass substrate, fused quartz substrate, and/or other suitable materials. - The
substrate 202 may also include various features such as doped regions, dielectric features, conductive features such as multi-layer interconnects, and/or other suitable features (not shown). In one embodiment, thesubstrate 202 includes features forming various semiconductor devices such as, for example, complementary metal-oxide-semiconductor field effect transistors (CMOSFET), imaging sensors, capacitors, memory cells, diodes, fin-type field-effect transistors (FINFETs), and/or other suitable devices. - The
device 200 includes a plurality of layers formed over thesubstrate 202. As illustrated, thedevice 200 includes abase layer 204, adielectric layer 206, a firsthard mask layer 208, an etch stop layer (ESL) 210, and a secondhard mask layer 212. However, these layers are exemplary and not intended to be limiting; one or more of the layers may be omitted, and additional layers may be added. For example, one or more anti-reflective coating layers or ESL layers may be inserted between two of the layers illustrated inFIGS. 2-12 . Example compositions for the layers formed on thesubstrate 202 are provided below, however, except as specifically defined by the claims hereto, these compositions are merely examples and not intended to be limiting. - In some embodiments, the
base layer 204 includes a dielectric material such as a low-k or an extreme low-k (ELK) dielectric material. Exemplary ELK materials include dielectric materials having a dielectric constant k less than approximately 2. Thebase layer 204 may include dielectric materials such as, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The layer may be deposited by a plasma enhanced chemical vapor deposition (PECVD) process or other suitable deposition technique. In some embodiments, thebase layer 204 may be an interlayer dielectric (ILD) layer or of a MLI structure. In some instances, metallization layer may be formed within thebase layer 204. - The
dielectric layer 206 may include dielectric materials such as, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, the first and second hard mask layers 208 and 212 include a hard mask material, such as titanium oxide (TixOy), tantalum oxide (TaxOy), titanium nitride (TixNy), silicon nitride (SixNy), and silicon oxide (SixOy). - In some embodiments, the
ESL layer 210 may be formed of a dielectric material, such as silicon carbide (SixCy), silicon nitride (SixNy), silicon oxynitride (SixOyNz), silicon oxycarbide (SixOyCz), or combination thereof. The X and Y in the chemical formulae can be stoichiometric or can depend on the amount of precursors used to form theESL layer 210. In some embodiments, theESL layer 210 may include multiple etch stop layers formed of aforementioned dielectric materials. Generally, as compared to thehard mask layer 212, theESL layer 210 may experience slower etch rate in an etching process. That way, when thehard mask layer 212 is etched, the etching process can substantially come to a stop within or near a boundary of theESL layer 210. Thelayers - With reference now to
FIGS. 3, 4, and 5 , themethod 100 then proceeds to block 104 to pattern the secondhard mask layer 212 to form a first plurality ofhard mask lines 2120. As shown inFIG. 3 , in some implementations, a plurality ofopenings 214 may be optionally formed on the secondhard mask layer 212. Each of the plurality ofopenings 214 extends along a direction that is perpendicular to the direction of the to-be-formed conductive features. In the embodiment represented inFIG. 3 , the plurality ofopenings 214 extend along the Y direction. One-directional openings such asopening 214 can be formed with good precision. As will be described in more details inFIGS. 5, 6, 9, 10, 11, and 12 , the plurality ofopenings 214 may result in formation of hard mask features that separate metal lines. For that reason, the formation of the plurality ofopenings 214 may be referred to as a first cut metal etch. - Referring now to
FIG. 4 , a bottom antireflective coating (BARC) 216 may be formed over the secondhard mask layer 212. In some implementations, theBARC layer 216 may be formed of silicon oxynitride (SiON), a polymer, other suitable materials, or a combination thereof, using CVD, spin-on processes, or other suitable processes.Photoresist lines 218 are formed over theBARC layer 216. Each of thephotoresist lines 218 extends parallel along the X direction. The photoresist lines 218 may be formed using suitable processes. For example, aphotoresist layer 218 may be formed on theBARC layer 216 by spin-on coating. Thephotoresist layer 218 may be then be exposed and developed by suitable lithography chemistry to turn intophotoresist lines 218. After thephotoresist lines 218 are developed, they may be subject to post-bake processes. Then theBARC layer 216 and the secondhard mask layer 212 are etched using the plurality ofphotoresist lines 218 as the etch mask. As shown inFIG. 5 , because theESL 210 below the secondhard mask layer 212 experiences a slower etch rate than the secondhard mask layer 212, the secondhard mask layer 212 not under the plurality ofphotoresist lines 218 is removed, leaving a first plurality ofhard mask lines 2120 over theESL 210. Theopenings 214 inFIG. 3 leave behind hard mask line cuts 2140 inFIG. 5 , dividing thehard mask line 2123 into segments. - Referring now to
FIG. 6 , themethod 100 then proceeds to block 106 where aspacer material layer 220 is formed over the first plurality ofhard mask lines 2120 and theESL 210. Thespacer material layer 220 is conformally formed and may also be referred to as aconformal layer 220. As shown inFIG. 6 , thespacer material layer 220 is formed not only over top surfaces of thehard mask lines 2120 but also over sidewalls of thehard mask lines 2120. As will be illustrated below in conjunction withFIG. 11 , thespacer material layer 220 over the sidewalls of thehard mask lines 2120 will result inspacer layers 2200 left behind after thehard mask lines 2120 is removed from thedevice 200. Thespacer material layer 220 may include a dielectric material, such as silicon dioxide (SixOy), silicon nitride (SixNy), silicon oxynitride (SixOyNz), and/or other suitable dielectric materials. The X and Y in the chemical formulae can be stoichiometric or can depend on the amount of precursors used to form thespacer material layer 220. It is noted that because thespacer material layer 220 is conformal in nature, it also fills in the hard mask line cuts 2140 (FIG. 5 ). With respect to thehard mask line 2123 where the hard mask line cuts 2140 reside, the portions of thespacer material layer 220 filled in the hard mask line cuts 2140 create spacers that divide thehard mask line 2123 into segments. As shown inFIG. 6 , thespacer material layer 220 formed over thehard mask lines 2120 includespacer layer trenches - Reference is now made to
FIG. 7 . Themethod 100 ofFIG. 1 proceeds to block 108 where a bottom antireflective coating (BARC)layer 222 is formed over thespacer material layer 220. In some implementations, theBARC layer 222 may be formed of silicon oxynitride (SiON), a polymer, other suitable materials, or a combination thereof, using CVD, spin-on processes, or other suitable processes. TheBARC layer 222 fills in thespacer layer trenches FIG. 7 , themethod 100 then proceeds to block 110 where an L-shaped opening (or L-shaped pattern) 224 is formed by removing theBARC layer 222 within the L-shapedopening 224. To pattern theBARC layer 222 to form the L-shapedopening 224, a photoresist layer may be deposited over theBARC layer 222. The photoresist layer can be exposed and developed to have an L-shaped opening corresponding to the L-shapedopening 224 and theBARC layer 222 is etched using the photoresist layer as an etch mask. In some implementations, the L-shapedopening 224 resembles an axe and may be referred to as the axe-shapedopening 224. As will be described in more details inFIGS. 8, 9, 10, 11, 12, and 13 , the L-shapedopenings 224 may result in formation of fill material features that separate metal lines. For that reason, the formation of the L-shapedopenings 224 may be referred to as a second cut metal etch. - In embodiments represented in
FIG. 7 , the L-shapedopening 224 is over thespacer layer trenches portion 2241 is perpendicular to the second line-shapedportion 2242. In some implementations, the second line-shapedportion 2242 extends from an end of the first line-shapedportion 2241. In some instances, the first line-shapedportion 2241 extends parallel to and over thespacer layer trench 2220. In some implementations, a width W of the first line-shapedportion 2241 can have a minimum equal to a width of thespacer layer trench 2220 in order to full expose thespacer layer trench 2220. The width W of the first line-shapedportion 2241 can have a maximum equal to a pitch of thehard mask lines 2120 such that the first line-shaped opening does not expose an adjacent spacer layer trench, such as thespacer layer trench 2210. That is, edges of the first line-shapedportion 2241 that define the width W can be over the spacer material layers 220. The large range of the width W widens the process window of themethod 100. In some instances, the second line-shapedportion 2242 spans over thehard mask line 2121, thehard mask line 2122, thespacer layer trenches portion 2241 includes a length P. In some instances, thedevice 200 includes a plurality of standard cells. Each of the standard cells includes gates of semiconductor devices that are disposed at a pitch. The pitch is substantially identical to the length P. In some embodiments, the L-shapedopening 224 may be formed using one mask that includes an L-shaped pattern that resembles the L-shapedopening 224. In some other embodiments, the L-shapedopening 224 may be formed using two separate masks: a first mask that includes a line pattern that resembles the first line-shapedportion 2241 and a second mask that includes a line pattern that resembles the second line-shapedportion 2242. While only one L-shapedopening 224 is shown inFIG. 7 , multiple L-shaped openings that are substantially similar to the L-shapedopening 224 may be advantageously formed on theBARC layer 222. - While L-shaped openings are described in the present disclosure, openings of other shapes that include two line-shaped portions coupled to one another are envisioned by the present disclosure. For example, the first line-shaped
portion 2241 can end in and connect to a middle portion of the second line-shapedportion 2242, thus making the L-shaped opening appear like a T-shaped opening. As used herein, the middle portion refers to any portion that is between the two terminal ends of a line-shaped portion. - In an alternative implementation, the
method 100 can include additional operations between operations inblock 108 and operations inblock 110. These additional operations are performed by a computer system that can access a layout of thedevice 200. Based on the layout of thedevice 200, such computer system can determine locations of metal line cuts. Taking thedevice 200 inFIG. 7 as an example, the metal line cuts include a first metal line cut located at anend 2243 of the first line-shapedportion 2241 and a second metal line cut that coincides with the second line-shapedportion 2242. It is noted that in this example, the firstmetal line cut 2243 will result in a cut of a metal line to be formed under thespacer layer trench 2220 and the secondmetal line cut 2242 will result in a cut of two metal lines to be formed under both thespacer layer trenches metal line cut 2243 and the second metal line cut 2242 (i.e. the metal line under the first line-shaped portion 2241) is functional. If the metal line segment is not functional (i.e. a dummy line), themethod 100 will proceed to block 110 where the L-shaped opening will eventually result in the removal or non-formation of the dummy line under the first line-shapedportion 2241. If the computer system determines that the metal line segment between the firstmetal line cut 2243 and the secondmetal line cut 2242 is functional based on the layout of thedevice 200 and should not be removed, themethod 100 does not apply to this specific location and only the portions of theBARC layer 222 that correspond to the firstmetal line cut 2243 and the secondmetal line cut 2242 will be removed. - Referring to
FIG. 8 , themethod 100 then proceeds to block 112 where the L-shapedopening 224 is filled with afill material 2240. As illustrated inFIG. 8 , thefill material 2240 not only fills in the portions of thespacer layer trenches opening 224 but also cover thespacer material layer 220 exposed in the L-shapedopening 224. In some embodiments, thefill material 2240 may be a silicon-containing antireflective coating (Si-ARC). For example, the Si-ARC can include inorganic ARCs such as SiON, silicon containing organic ARCs such as polysilanes, and/or other suitable compositions. In an embodiment, the silicon content is between approximately 30 and 40 atomic weight percent. Thespacer layer trenches fill material 2240 may also be referred to asreverse material 2240. - Referring to
FIGS. 9 and 10 , themethod 100 proceeds to block 114 where theBARC layer 222 is removed. In an embodiment, after thefill material 2240 fills the L-shapedopening 224, thedevice 200 is planarized by, for example, the use of a chemical mechanical polishing (CMP) process. Anyexcess fill material 2240 that is not in thespacer layer trenches FIG. 9 . InFIG. 9 , theBARC layer 222 is also planarized such that a top surface of theBARC layer 222 is flush with a top surface of the plurality ofspacers 2200. Referring now toFIG. 10 , theplanarized BARC layer 222 is then selectively etched away without substantially etching thefill material feature BARC layer 222 and thefill material 2240, theBARC layer 222 and thefill material 2240 have different compositions. For example, theBARC layer 222 can be a polymer and thefill material 2240 can be inorganic ARC such as SiON. - Referring now to
FIG. 11 , themethod 100 proceeds to block 116 where thespacer material layer 220 are etched back to expose the first plurality ofhard mask lines 2120. As illustrated inFIG. 11 , after the portion of thespacer material layer 220 over the top surfaces of thehard mask lines 2120 is removed, thehard mask lines 2120 are exposed and a plurality ofspacers 2200 over the sidewalls of thehard mask lines 2120 are formed. Thespacers 2200 may be said to track thehard mask lines 2120. In some embodiments, the portion of thespacer material layer 220 on theESL layer 210 is also removed atblock 116. Also shown inFIG. 11 , thehard mask line 2123 is separated by spacer material features 226 into segments. Thespacers 2200 that track thehard mask lines 2120 also definespacer layer trenches spacer layer trenches - Reference is now made to
FIG. 12 . Themethod 100 proceeds to block 118 where thehard mask lines 2120 are removed or stripped off thedevice 200 to formtrenches fill material features 2245 and 2247) is selected to have etching selectivity with respect to the material in thehard mask lines FIG. 11 . This etching selectivity between the hard mask material and the fill material ensures that hard mask material is preferentially etched away while the fill material is not substantially etched. Upon completion of the operation inblock 118, thespacers 2200 define not onlyspacer layer trenches trenches spacer layer trench 2210 is divided by thefill material feature 2245 into two segments;spacer layer trench 2220 is divided by thefill material feature 2247 into two segments; andtrench 2330 is divided by the spacer material features 226 into three segments. These trenches represent the pattern of conductive lines once all operations inmethod 100 are carried out. - Referring now to
FIG. 13 , themethod 100 inFIG. 1 proceeds toblocks block 120, a pattern of thespacers 2200 and the fill material 2240 (includingfill material features 2245 and 2247) is transferred onto an underlying layer, such as thebase layer 204. The transferred pattern in thebase layer 204 may be used to define a conductive layer (e.g., metal line) of an interconnect structure such as by a damascene or dual-damascene process. In some embodiments, to perform the operations inblock 120, thebase layer 204 is anisotropically etched using thespacers 2200 and thefill material 2240 as an etch mask. Atblock 120, aconductive material 280 may then be filled or plated into the trenches in thebase layer 204. In some embodiments, the workpiece 200 (device 200) is subject to a planarization process, such as a CMP process, to planarize the top surfaces of theconductive materials 280 filled in the trenches of thebase layer 204. The trenches in thebase layer 204 track the pattern of thespacers 2200 and thefill material 2240. Particularly, as shown inFIG. 13 , themetal line cut 2610 correspond to thefill material feature 2245, themetal line cut 2620 corresponds to thefill material feature 2247, and themetal line cuts base layer 204 may include dry etch, or plasma etch processes. Compared to certain techniques where the fill material features divide thespacer layer trench 2220 into three segments (as opposed to two segments divided by thefill material feature 2247 in the present disclosure), the metal line cut 2620 of the present disclosure removes a short segment of conductive line formed within the area of themetal line cut 2620. In some instances, such a short conductive line segment can act as a dummy metal line between two adjacent gates of a semiconductor device in a standard cell. Such a dummy metal line may reduce the performance of the semiconductor device, such as the switching speed of the semiconductor device, for example, by increasing parasitic capacitance to nearby conductive features. - Referring now to
FIG. 14 , in some embodiments, only a portion of thehard mask line 2124 inFIG. 11 is removed and aleftover segment 2125 of thehard mask line 2124 is left in thetrench 2340 inFIG. 14 . In those embodiments, thetrench 2340 may be shortened by the leftoverhard mask segment 2125. Because thetrench 2340 represents a conductive line to be formed, shortening of thetrench 2340 also shortens the resulting conductive line. Referring now toFIG. 15 , the pattern of thespacer layer 2200, the leftoverhard mask segment 2125 and thefill material features 2240 are transferred to thebase layer 204. The leftoverhard mask segment 2125 can result in abase layer segment 2650 to be formed. Thebase layer segment 2650 cuts short theconductive metal line 2802. This partial hard mask line removal process can be an alternative to the first metal cut etch process described above. - By forming the L-shaped
opening 224 inblock 110, themethod 100 of the present disclosure not only widens the process window but also eliminates dummy conductive lines that may affect the performance of the semiconductor device. As shown inFIG. 7 , the first line-shapedportion 2241 of the L-shapedopening 224 can be substantially wider than thespacer layer trench 2220. The L-shapedopening 224 aids the removal of BARC layer material in thespacer layer trench fill material 2240. In addition, because thefill material 2240 fills thespacer layer trench 2220 in the first line-shapedportion 2241, no dummy conductive line will be formed in that area as a result. In summary, embodiments of themethod 100 provide benefits of forming functional conductive lines without the drawback of having dummy metal lines that have a length substantially identical to a pitch of gates of semiconductor devices in a standard cell. In addition, the embodiments of themethod 100 provide large process window and increase process fidelity by forming an L-shaped opening in the second cut metal etch step. - In one exemplary aspect, the present disclosure is directed to a method of forming a semiconductor device. The method includes providing a workpiece having a substrate, a material layer over the substrate, and a hard mask layer over the material layer. The method further includes patterning the hard mask layer to form a first plurality of hard mask lines and forming a spacer material layer over the first plurality of hard mask lines, resulting in a second plurality of trenches defined by the spacer material layer, wherein the second plurality of trenches tracks the first plurality of hard mask lines. The method further includes forming an antireflective layer over the spacer material layer, including over the second plurality of trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the second plurality of trenches; filling the L-shaped opening with a fill material; etching the spacer material layer to expose the first plurality of hard mask lines; and removing the first plurality of hard mask lines. After removing the first plurality of hard mask lines, the method further includes transferring a pattern of the spacer material layer and the fill material onto the material layer, resulting in trenches tracking the pattern; and filling the trenches with a conductive material.
- In an embodiment of the method, the L-shaped opening includes a first line portion and a second line portion, and the second line portion extends from an end of the first line portion and is perpendicular to the first line portion. In a further embodiment, a width of the first line portion is greater than about a width of one of the second plurality of trenches and less than about a pitch of the first plurality of hard mask lines. In another further embodiment, the first line portion extends parallel to and is over one of the second plurality of trenches. In an embodiment, the second line portion extends across at least two of the second plurality of trenches.
- In another embodiment of the method, the forming of the L-shaped opening in the antireflective layer comprises forming the L-shaped opening over more than one of the second plurality of trenches. In yet another embodiment, the removing of the first plurality of hard mask lines includes removing a portion of the first plurality of hard mask lines, thereby resulting in a leftover hard mask segment; and the transferring the pattern of the spacer material layer and fill material onto the material layer includes transferring a pattern of the leftover hard mask segment on the material layer.
- In another exemplary aspect, the present disclosure is directed to a method of forming a semiconductor device. The method includes forming a first plurality of hard mask lines over a material layer on a substrate, the first plurality of hard mask lines extending along a first direction; and forming a spacer material layer over the first plurality of hard mask lines, resulting in a second plurality of trenches extending along the first direction, each of the second plurality of trenches having sidewalls formed of the spacer material layer, wherein the second plurality of trenches tracks the first plurality of hard mask lines. The method further includes forming a antireflective layer over the second plurality of trenches; forming a first line-shaped opening in the antireflective layer; filling the first line-shaped opening with a fill material, wherein the first line-shaped opening extends along the first direction; etching the spacer material layer to expose the first plurality of hard mask lines; and removing the first plurality of hard mask lines. After removing the first plurality of hard mask lines, the method further includes transferring a pattern of the spacer material layer and the fill material onto the material layer, resulting in trenches tracking the pattern; and filling the trenches with a conductive material.
- In an embodiment, the method further includes forming a second line-shaped opening in the antireflective layer, wherein the second line-shaped opening extends from an end of the first line-shaped opening and along a second direction perpendicular to the first direction; and filling the second line-shaped opening with the fill material. In another embodiment, the first line-shaped opening extends over one of the second plurality of trenches. In a further embodiment, the second line-shaped opening extends across at least two of the second plurality of trenches.
- In another embodiment, a width of the first line-shaped opening is greater than about a width of one of the second plurality of trenches of the second plurality of trenches and less than about a pitch of the first plurality of hard mask lines. In some embodiments, the forming of the first line-shaped opening in the antireflective layer comprises forming the first line-shaped opening over one of the second plurality of trenches. In some embodiments, the removing of the first plurality of hard mask lines includes removing a portion of the first plurality of hard mask lines, thereby resulting in a leftover hard mask segment, and the transferring the pattern of the spacer material layer and fill material onto the material layer includes transferring a pattern of the leftover hard mask segment on the material layer.
- In yet another exemplary aspect, the present disclosure is directed to a method of forming a semiconductor device. The method includes providing a workpiece having a substrate, a material layer over the substrate, and a hard mask layer over the material layer; patterning the hard mask layer, thereby forming a first plurality of hard mask lines; forming a spacer material layer over the first plurality of hard mask lines, resulting in a second plurality of trenches that tracks the first plurality of hard mask lines; and forming a antireflective layer over the spacer material layer, including over the second plurality of trenches. The method further includes forming an L-shaped opening in the antireflective layer, wherein the L-shaped opening includes a first line portion and a second line portion perpendicular to the first line portion, wherein the first line portion extends parallel to and is over one of the second plurality of trenches. The method further includes filling the L-shaped opening with a fill material; etching the spacer material layer to expose the first plurality of hard mask lines; and removing the first plurality of hard mask lines. After removing the first plurality of hard mask lines, the method further includes transferring a pattern of the spacer material layer and the fill material onto the material layer, resulting in trenches tracking the pattern; and filling the trenches with a conductive material.
- In an embodiment of the method, the second line portion extends from an end of the first line portion and is perpendicular to the first line portion. In another embodiment, the second line portion extends across at least two of the second plurality of trenches. In some embodiments, a width of the first line portion is greater than about a width of one of the second plurality of trenches of the second plurality of trenches and less than about a pitch of the first plurality of hard mask lines.
- In some embodiments, the removing of the first plurality of hard mask lines includes removing a portion of the first plurality of hard mask lines, thereby resulting in a leftover hard mask segment, and the transferring the pattern of the spacer material layer and fill material onto the material layer includes transferring a pattern of the leftover hard mask segment on the material layer. In some embodiments, after the removing of the first plurality of hard mask lines, the fill material comprises a line-shaped portion that fills one of the second plurality of trenches.
- The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
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CN201910208953.XA CN110556300A (en) | 2018-05-31 | 2019-03-19 | method of forming semiconductor device |
US16/704,195 US10727113B2 (en) | 2018-05-31 | 2019-12-05 | Methods of forming metal layer structures in semiconductor devices |
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US10727113B2 (en) | 2020-07-28 |
US10504775B1 (en) | 2019-12-10 |
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US20200111702A1 (en) | 2020-04-09 |
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