CN113806687A

CN113806687A - Signal processing circuit and signal processing method

Info

Publication number: CN113806687A
Application number: CN202111106090.9A
Authority: CN
Inventors: 吴华强; 魏秋萌; 唐建石; 高滨; 钱鹤
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2021-09-22
Filing date: 2021-09-22
Publication date: 2021-12-17

Abstract

A signal processing circuit and a signal processing method are provided. The signal processing circuit includes: a drive control circuit; a signal acquisition circuit configured to acquire a plurality of input analog signals; a memristor array, wherein the memristor array is configured to perform K-order convolution processing on a plurality of input analog signals, K being an integer greater than 1; and the output circuit is configured to sequentially obtain K first analog accumulated signals obtained after the memristor array executes K-order convolution processing according to a first time interval under the control of the driving control circuit, and add the K first analog accumulated signals to obtain first data fusion signals corresponding to the plurality of input analog signals. The signal processing circuit can directly operate the received analog signals without analog-to-digital conversion, avoids introducing a digital conversion circuit, realizes delay and temporary storage of the analog signals in a post-sampling mode, and simultaneously improves computing power and energy efficiency by utilizing the memristor array.

Description

Signal processing circuit and signal processing method

Technical Field

Embodiments of the present disclosure relate to a signal processing circuit and a signal processing method.

Background

With the development of the application of the internet of things and intelligent sensing, the demand of rapid real-time analysis on sensor data is increasing day by day, for example, in the automatic driving technology, signals of image sensing and vehicle-mounted radar need to be processed in time to deal with complex traffic conditions; meanwhile, the number of sensors is also increasing to extract more information for improving system performance, for example, a microphone array is used for realizing voice enhancement, and the recognition accuracy and robustness of a voice interaction system are improved. This puts higher demands on the computational power of both the transmission of the sensing data and the back-end processing. Therefore, more and more technologies are beginning to search for data preprocessing at the sensor terminal and filtering the received signals, so as to reduce the amount of transmitted data and improve the response capability of the whole system.

Disclosure of Invention

At least one embodiment of the present disclosure provides a signal processing circuit, including: a drive control circuit; a signal acquisition circuit configured to acquire a plurality of input analog signals; a memristor array, wherein the memristor array is configured to perform K-order convolution processing on a plurality of input analog signals, K being an integer greater than 1; and the output circuit is configured to sequentially obtain K first analog accumulated signals obtained after the memristor array executes K-order convolution processing according to a first time interval under the control of the driving control circuit, and add the K first analog accumulated signals to obtain first data fusion signals corresponding to the plurality of input analog signals.

For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the output circuit sequentially obtains K first analog accumulated signals at a first time interval from a first time point under the control of the driving control circuit, and is further configured to sequentially obtain K second analog accumulated signals after the memristor array performs K-order convolution processing according to the first time interval from a time point i × T after the first time point under the control of the driving control circuit, and add the K second analog accumulated signals to obtain an ith second data fusion signal corresponding to the input analog signals, where i is a positive integer less than or equal to m-1, and i sequentially takes

values

1, 2,. m-1, m is a positive integer greater than 1 and less than or equal to K in time order, and T represents the second time interval, and the ratio of the second time interval to the first time interval is N, where N is K/m and is a positive integer.

For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the memristor array includes K column signal output ends, the K column signal output ends are used for outputting K first analog accumulated signals of K-order convolution processing correspondingly, the output circuit includes K switch sub-circuits and an accumulation circuit, input ends of the K switch sub-circuits are electrically connected to the K column signal output ends one by one, output ends of the K switch sub-circuits are electrically connected to input ends of the accumulation circuit, the K switch sub-circuits are configured to, under control of the driving control circuit, sequentially turn on connection of the corresponding column signal output ends and input ends of the accumulation circuit according to a first time interval, transmit the K first analog accumulated signals obtained after convolution processing is performed on the memristor array to the accumulation circuit, the accumulation circuit is configured to perform summation processing on the K first analog accumulated signals, to obtain a first data fusion signal.

For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the accumulation circuit is an integration circuit, and the drive control circuit is further configured to reset the integration circuit after obtaining the first data fusion signal.

For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the memristor array further includes K column signal output ends, where the K column signal output ends are used to correspondingly output K second analog accumulation signals or K first analog signals processed by K-order convolution, the output circuit includes K switch sub-circuits and an accumulation circuit, each switch sub-circuit includes 1 first input end and m first output ends, the accumulation circuit includes m accumulation sub-circuits, each of the m accumulation sub-circuits includes a second input end and a second output end, the K column signal output ends are respectively electrically connected to the K column signal output ends in a one-to-one correspondence manner, the m first output ends of each switch sub-circuit are respectively electrically connected to the m second input ends of the m accumulation sub-circuits in a one-to-one correspondence manner, and each of the m accumulation sub-circuits is configured to perform summation processing to respectively obtain the first data fusion signal, The 1 st second data fusion signal, the 2 nd second data fusion signal, the m-1 st second data fusion signal, and the m second output ends of the m accumulation sub-circuits respectively output the first data fusion signal, the 1 st second data fusion signal, the 2 nd second data fusion signal, and the m-1 st second data fusion signal.

For example, in a signal processing circuit provided in at least one embodiment of the present disclosure, each switch sub-circuit is configured to: under the control of the drive control circuit, at the same time, the column signal output end electrically connected with the switch sub-circuit is only conducted with one second input end of the m second input ends of the accumulation circuit, and the column signal output end electrically connected with the switch sub-circuit is sequentially switched and connected to different second input ends according to a second time interval.

For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, under the control of the driving control circuit, from the first time, the K switching sub-circuits are further configured to sequentially turn on the K column signal output terminals and the second input terminal of the 1 st accumulation sub-circuit at first time intervals, so as to sequentially output the K first analog accumulation signals to the 1 st accumulation sub-circuit; and under the control of the drive control circuit, sequentially connecting the K column signal output ends with the second input end of the (i +1) th accumulation sub-circuit according to a first time interval from the i × T moment after the first moment, so as to sequentially output the K second analog accumulation signals to the (i +1) th accumulation sub-circuit.

For example, in a signal processing circuit provided by at least one embodiment of the present disclosure, the switch sub-circuit includes a 1-to-m switch circuit, and the 1-to-m switch circuit includes m channels, and the m channels are electrically connected to the m first output ends, respectively.

For example, in a signal processing circuit provided in at least one embodiment of the present disclosure, the accumulation sub-circuit is an integration circuit, and the drive control circuit is further configured to perform a reset operation on the integration circuit after the integration circuit outputs the first data fusion signal or the ith second data fusion signal.

For example, in a signal processing circuit provided in at least one embodiment of the present disclosure, the drive control circuit includes an array drive control circuit coupled to the memristor array and configured to set the memristor array, write data of a convolution parameter matrix corresponding to a K-order convolution process to the memristor array, and control the memristor array to operate to perform the K-order convolution process on the plurality of input analog signals.

For example, in a signal processing circuit provided by at least one embodiment of the present disclosure, the number of the plurality of input analog signals is J, the memristor array includes J rows and K columns of memristor cells arranged in an array, the J rows are respectively used for receiving the plurality of input analog signals, and the K columns respectively correspond to the K column signal output terminals.

At least one embodiment of the present disclosure provides a signal processing method, including: acquiring a plurality of input analog signals; performing K-order convolution processing on a plurality of input analog signals by using a memristor array, wherein K is an integer greater than 1; according to a first time interval, K first analog accumulated signals after the memristor array executes K-order convolution processing are sequentially obtained, and the K first analog accumulated signals are subjected to addition processing to obtain first data fusion signals corresponding to the plurality of input analog signals.

For example, in a signal processing method provided by at least one embodiment of the present disclosure, K first analog accumulation signals are sequentially obtained at a first time interval from a first time, and K second analog accumulation signals obtained after a memristor array performs K-order convolution processing are sequentially obtained at a first time interval from a time i × T after the first time, and the K second analog accumulation signals are summed to obtain an ith second data fusion signal corresponding to a plurality of input analog signals, where i is a positive integer less than or equal to m-1, i is sequentially valued as 1, 2,. m-1, m is a positive integer greater than 1 and less than or equal to K, T represents a second time interval, and a ratio of the second time interval to the first time interval is N, and N is K/m and is a positive integer.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Figure 1 shows a schematic diagram of a discrete broadband beamforming architecture;

FIG. 2A shows a schematic structure of a memristor array;

FIG. 2B is a schematic diagram of a memristor cell of the 1T1R structure;

FIG. 2C is a schematic diagram of a memristor cell of a 2T2R structure;

fig. 3A is a schematic structural diagram of a signal processing circuit based on a memristor array provided by at least one embodiment of the present disclosure;

fig. 3B is a schematic block diagram of an output circuit provided in at least one embodiment of the present disclosure;

fig. 3C illustrates a schematic diagram of an exemplary signal processing circuit provided by at least one embodiment of the present disclosure;

fig. 3D illustrates a sampling schematic diagram of a signal processing circuit provided by at least one embodiment of the present disclosure;

fig. 4A is a schematic block diagram of a signal processing circuit according to at least one embodiment of the present disclosure;

fig. 4B illustrates a schematic diagram of another exemplary signal processing circuit provided by at least one embodiment of the present disclosure;

FIG. 4C shows a switch connection schematic of the signal processing circuit shown in FIG. 4B;

fig. 4D is a schematic diagram illustrating a design flow of a signal processing circuit according to at least one embodiment of the disclosure;

fig. 5A illustrates a schematic diagram of a signal processing circuit provided by at least one embodiment of the present disclosure;

FIG. 5B shows a switch connection schematic of the signal processing circuit shown in FIG. 5A;

FIG. 6A is a schematic block diagram of a memristor array provided in at least one embodiment of the present disclosure;

FIG. 6B is a schematic diagram of another memristor array provided by at least one embodiment of the present disclosure;

FIG. 6C illustrates a signal processing circuit constructed with memristor cells of the 2T2R configuration;

FIG. 6D illustrates another signal processing circuit constructed with memristor cells of the 2T2R configuration;

fig. 7 shows a schematic flow chart of a signal processing method provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The data fusion technology is an information processing technology which is implemented by automatically analyzing and integrating a plurality of observation information obtained according to time sequence under a certain criterion by using a computer to complete required decision and evaluation tasks. The data fusion technique includes, for example, wideband beamforming, which forms a specific Response in time and space by filtering and superimposing each channel signal with a plurality of FIR (Finite Impulse Response) filters.

Figure 1 shows a schematic diagram of a discrete broadband beamforming architecture. As shown in FIG. 1, J sensors Sen [0], Sen [1] … … Sen [ J-1] respectively send input signals Sen [ i ] (t) (i is more than or equal to 0 and less than or equal to J-1, i is a positive integer, t represents time) to J groups of FIR filters for filtering processing, and then add and output all filtering results to finally obtain discrete beam forming results.

As shown in fig. 1, each FIR filter has an order of K and is composed of a delay unit and a weight multiplication unit. The calculation process of the beam forming is as follows:

for the ith sensor Sen [ i]In other words, the ith FIR filter will filter the ith sensor Sen [ i ]]Input signal Sen [ i ] of](t) performing a plurality of delay processes, e.g. delaying the signal by a usable vector a_i＝[Sen[i](t),Sen[i](t-τ),Sen[i](t-2τ),…,Sen[i](t-(K-1)τ)]^THere, τ denotes a first time interval, i.e. a sampling time interval of the input signal; and, the delay processing result and the corresponding weight w are set_i＝[w_i，0,w_i，1,w_i，2,…,w_i，K-1]^TMultiplying and superposing to obtain an output result

Thus, the final output of the beamforming system is

From another perspective, the computation process is analyzed, and the signals delayed by the channels of the jth column (j is more than or equal to 0 and less than or equal to K-1, and j is a positive integer) at time t can be used as a vector m_j(t)＝[Sen[0](t-jτ),Sen[1](t-jτ),Sen[2](t-jτ),…,Sen[J-1](t-jτ)]^TRepresents, vector m_j(t) and the column weight w_j＝[w_0,j,w_1,j,w_2,j,…,w_J-1,j]^TThe result of the superposition after multiplication is

The final output result can be expressed as:

for example, the wideband beamforming circuit shown in fig. 1 is usually implemented by a DSP (Digital Signal Processor), and this approach needs to integrate a large number of analog/Digital conversion interface circuits to convert the received Signal into a Digital Signal, and then perform a logic operation by the DSP. However, the requirement of low power consumption and small size of the terminal device is undoubted by integrating the analog/digital conversion interface circuit and the DSP in the sensor terminal in large quantities.

Memristors (such as resistive random access memories, phase change memories, conductive bridge memories and the like) are novel micro-nano electronic devices, and the conductance state of the micro-nano electronic devices can be adjusted by applying external excitation. The memristor is a two-terminal device and has the characteristics of adjustable resistance and non-volatilization. According to kirchhoff current law and ohm law, an array formed by the devices can complete analog multiplication and addition calculation in parallel, so that input analog signals are directly processed, and storage and calculation both occur in memristors of the array. Based on the computing architecture, the storage and computation integrated computing without a large amount of data movement can be realized, the data movement time is reduced, and the energy efficiency, the power consumption and the area are high during computing. Due to the integration and the non-volatility of the memristor device, the efficient parallel characteristic of the operation of the memristor array and the like, the signal processing circuit can be constructed by utilizing the memristor array.

The signal processing circuit provided by the embodiment of the disclosure can directly operate the received analog signal, avoids introducing a digital-to-analog conversion circuit, reduces the area and circuit power consumption overhead caused by a data interface and a logic operation unit, realizes the delay and temporary storage of the analog signal in a post-sampling mode, and realizes highly parallel multiply-add operation by using a memristor array, thereby improving the computational power and energy efficiency at the same time.

At least one embodiment of the present disclosure further provides an information processing method corresponding to the information processing circuit.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

FIG. 2A shows a schematic structure of a memristor array comprised of memristor cells making up an array of J rows and K columns, both J and K being positive integers. Each memristor cell includes a switching element and one or more memristors. In fig. 2A, WL <1>, WL <2> … … WL < K > respectively represent word lines of the first and second columns … … and K-th columns, and a control electrode (e.g., a gate of a transistor) of a switching element in a memristor cell of each row is connected to the word line corresponding to the row; BL <1>, BL <2> … … BL < J > respectively represent the bit lines of the first row and the second row … … and the J-th row, and the memristor in the memristor unit of each row is connected with the corresponding bit line of the row; SL <1>, SL <2> … … SL < K > respectively represent source lines of the first and second columns … … and kth columns, and the source of the transistor in the memristor cell of each column is connected to the source line corresponding to that column. According to kirchhoff's law, the memristor array may perform multiply-accumulate calculations in parallel by setting the state (e.g., resistance) of the memristor cells and applying corresponding word line and bit line signals to the word lines and bit lines.

The memristor cells in the memristor array of fig. 2A may have, for example, a 1T1R structure or a 2T2R structure, where the memristor cells of the 1T1R structure include one transistor and one memristor, and the memristor cells of the 2T2R structure include two transistors and two memristors, for example, the memristors include, but are not limited to, RRAM, PCRAM, ECRAM, Flash, and the like. It should be noted that the structure of the memristor unit is not limited in the present disclosure, and memristor units of other structural forms that can implement multiply-accumulate operations, such as structures 1S1F, 0T1R, and the like, may also be employed.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of them is directly described as a first pole, and the other is a second pole.

Fig. 2B is a schematic diagram of a memristor cell of a 1T1R structure. As shown in fig. 2B, the memristor cell of the 1T1R structure includes one transistor M1 and one memristor R1.

The embodiment of the present disclosure does not limit the type of the transistor used, for example, when the transistor M1 is an N-type transistor, its gate is connected to the word line WL, for example, the transistor M1 is turned on when the word line WL inputs a high level; the first pole of the transistor M1 may be a source and configured to be connected to a source line SL, e.g., the transistor M1 may receive a reset voltage through the source line SL; the second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the memristor R1, a first pole (e.g., an anode) of the memristor R1 is connected to the bit line BL, e.g., the memristor R1 may receive a set voltage through the bit line BL. For example, when the transistor M1 is a P-type transistor, its gate is connected to the word line WL, for example, the transistor M1 is turned on when the word line WL is input with a low level; the first pole of the transistor M1 may be a drain and configured to be connected to a source line SL, e.g., the transistor M1 may receive a reset voltage through the source line SL; a second pole of the transistor M1 may be a source and configured to be connected to a second pole (e.g., a cathode) of the memristor R1, a first pole (e.g., an anode) of the memristor R1 being connected to the bit line BL, e.g., the memristor R1 may receive a set voltage through the bit line BL. It should be noted that the memristor structure may also be implemented as other structures, for example, a structure in which the second pole of the memristor R1 is connected to the source line SL, and the embodiment of the present disclosure is not limited thereto.

In the following embodiments, the transistor M1 is exemplified by an N-type transistor.

The word line terminal WL is used to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. When the memristor R1 is operated, for example, a set operation or a reset operation, the transistor M1 needs to be turned on first, that is, a turn-on voltage needs to be applied to the gate of the transistor M1 through the word line terminal WL. After the transistor M1 is turned on, for example, a voltage may be applied to the memristor R1 by applying voltages to the memristor R1 at the source line terminal SL and the bit line terminal BL to change the resistance state of the memristor R1. For example, a set voltage may be applied through the bit line terminal BL to cause the memristor R1 to be in a low resistance state; for another example, a reset voltage may be applied across the source terminal SL to place the memristor R1 in a high resistance state. For example, the resistance value in the high resistance state is 100 times or more, for example 1000 times or more, the resistance value in the low resistance state.

It should be noted that, in the embodiment of the present disclosure, by applying voltages to the word line terminal WL and the bit line terminal BL at the same time, the resistance value of the memristor R1 may be made smaller and smaller, that is, the memristor R1 changes from the high resistance state to the low resistance state, and an operation of changing the memristor R1 from the high resistance state to the low resistance state is referred to as a set operation; by applying voltages to the word line terminal WL and the source line terminal SL simultaneously, the resistance value of the memristor R1 can be made larger and larger, that is, the memristor R1 changes from the low resistance state to the high resistance state, and the operation of changing the memristor R1 from the low resistance state to the high resistance state is called a reset operation. For example, the memristor R1 has a threshold voltage that does not change the resistance value (or conductance value) of the memristor R1 when the input voltage magnitude is less than the threshold voltage of the memristor R1. In this case, a calculation may be made with the resistance value (or conductance value) of the memristor R1 by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of the memristor R1 may be changed by inputting a voltage greater than a threshold voltage.

Fig. 2C is a schematic diagram of a memristor cell of a 2T2R structure. As shown in fig. 2C, the memristor cell of the 2T2R structure includes two transistors M1 and M2 and two memristors R1 and R2. In the following, the transistors M1 and M2 are both N-type transistors as an example.

The gate of the transistor M1 is connected to the word line terminal WL1, for example, when the word line terminal WL1 of M1 inputs a high level, the transistor M1 is turned on, the gate of the transistor M2 is connected to the word line terminal WL2, for example, when the word line terminal WL2 of M2 inputs a high level, the transistor M2 is turned on; the first pole of the transistor M1 may be a source and configured to be connected to a source line terminal SL, for example, the transistor M1 may receive a reset voltage through the source line terminal SL, the first pole of the transistor M2 may be a source and configured to be connected to the source line terminal SL, for example, the transistor M2 may receive a reset voltage through the source line terminal SL, and the first pole of the transistor M1 is connected to the first pole of the transistor M2 and is connected together to the source line terminal SL. The second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the memristor R1, a first pole (e.g., an anode) of the memristor R1 is connected to the bit line terminal BL1, e.g., the memristor R1 may receive a set voltage through the bit line terminal BL 1; the second pole of the transistor M2 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the memristor R2, a first pole (e.g., an anode) of the memristor R2 is connected to the bit line terminal BL2, e.g., the memristor R2 may receive a set voltage through the bit line terminal BL 2.

It should be noted that, the transistors M1 and M2 in the memristor unit with the 2T2R structure may also both adopt P-type transistors, and details are not described here.

Fig. 3A is a schematic structural diagram of a signal processing circuit based on a memristor array according to at least one embodiment of the present disclosure.

For example, the signal processing circuit can be located at the sensor end, and can complete part of preprocessing operations in data fusion to be processed, so as to realize direct real-time processing on analog signals input by the sensor.

As shown in fig. 3A, some embodiments of the present disclosure provide a signal processing circuit 300 including a memristor array 301, a signal acquisition circuit 302, a drive control circuit 303, and an output circuit 304.

For example, signal acquisition circuit 302 is configured to acquire a plurality of input analog signals. For example, the signal acquisition circuit 302 includes a plurality of sensors, the plurality of input analog signals may be analog signals collected by the plurality of sensors, and the signal acquisition circuit 302 inputs the plurality of input analog signals received and collected by the plurality of sensors to corresponding bit lines in the memristor array 301 to perform a K-order convolution process.

For example, the output circuit 304 is configured to sequentially obtain K first analog accumulated signals after the memristor array 301 performs the K-order convolution processing and add the K first analog accumulated signals at first time intervals under the control of the driving control circuit 303 to obtain first data fusion signals corresponding to the plurality of input analog signals.

For example, the drive control circuitry 303 includes array drive control circuitry coupled with the memristor array 301 and configured to set the memristor array 301, write data corresponding to a convolution parameter matrix of a K-order convolution process to the memristor array 301, and control the memristor array 301 to operate to perform the K-order convolution process on the plurality of input analog signals.

For example, the memristor array 301 may be configured as shown in fig. 2A, where the memristor array 301 includes a plurality of memristor units arranged in an array, and includes J rows and K columns, that is, K memristor units are arranged in each row, and J memristor units are arranged in each column. The memristor array further comprises K source lines, K word lines and J bit lines, wherein the K source lines correspond to K columns respectively, the K word lines correspond to K columns respectively, the J bit lines correspond to J rows respectively, and J and K are positive integers.

For example, the memristor array 301 includes K column signal outputs, i.e., K source lines, for outputting K first analog accumulation signals of the K-order convolution processing correspondingly.

For example, the input analog signals are respectively input to the signal acquisition circuit 302 and the drive control circuit of the memristor array 301303 control the memristor array 301 to operate to convolve a plurality of input analog signals. According to kirchhoff's law, a first analog accumulated signal output by the column signal output terminal is an output current of the memristor array 301, and the first analog accumulated signal can be obtained according to the following formula:

wherein J is 1, …, J, K is 1, …, K. In the above formula, V_jRepresenting a plurality of j-th input analog signals, I_kRepresenting the current signal output by the kth column signal output terminal of the plurality of column signal output terminals. G_jkRepresenting the memristor cell overall conductance values located in the jth row and kth column, in this embodiment the memristor conductance values are used to represent the coefficient vectors of the filter. According to kirchhoff's law, the memristor array can complete multiplication and accumulation calculation in parallel.

Fig. 3B is a schematic block diagram of an output circuit according to at least one embodiment of the disclosure. In fig. 3B, arrows indicate signal flow directions.

As shown in fig. 3B, the output circuit 304 includes K switch sub-circuits 305 and an accumulation circuit 306, where the K switch sub-circuits 305 are respectively a switch sub-circuit 305_1, a switch sub-circuit 305_2,. a switch sub-circuit 305_ K-1, and a switch sub-circuit 305_ K, input terminals of the K switch sub-circuits 305 are respectively electrically connected to the K column signal output terminals one by one, that is, electrically connected to the column signal output terminals SL [0] to SL [ K-1] of the memristor array, and output terminals of the K switch sub-circuits 305 are electrically connected to input terminals of the accumulation circuit 306. For example, the K switch sub-circuits 305 are all electrically connected (not shown) to the driving control circuit 303 to receive the control signal of the driving control circuit 303, and implement corresponding operations according to the control signal.

For example, the K switching sub-circuits 305 are configured to sequentially turn on the connection between the corresponding column signal output terminal and the input terminal of the accumulation circuit 306 at a first time interval under the control of the driving control circuit 303, and transmit K first analog accumulation signals obtained after the obtained memristor array 301 performs convolution processing to the accumulation circuit 306.

For example, the accumulation circuit 306 is configured to sum the K first analog accumulation signals to obtain a first data fusion signal.

For example, the switch sub-circuit 305 may be a circuit structure including a switch capable of being turned on and off under the control of the driving control circuit 303, thereby turning on and off the connection between the corresponding column signal output terminal and the input terminal of the accumulation circuit 306. Of course, the switch sub-circuit may also be implemented as other circuit structures, and the embodiment of the disclosure does not limit the circuit structure of the switch sub-circuit 305, and only the switch sub-circuit 305 needs to implement the functions of turning on and off.

For example, the accumulation circuit 306 is an integration circuit and is configured to reset after outputting the first data fusion signal, and restart the next round of accumulation operation.

For example, when the switch sub-circuit 305 has a circuit configuration including one switch, a schematic diagram of the signal processing circuit is shown in fig. 3C, and an exemplary signal processing circuit in an embodiment of the present disclosure is described below with reference to fig. 3C.

As shown in fig. 3C, the signal processing circuit includes a memristor array 301, for example, the number of the plurality of input analog signals is J, the memristor array 301 includes J rows and K columns of memristor cells arranged in an array, the J rows are respectively used for receiving the plurality of input analog signals, and the K columns respectively correspond to the K column signal output terminals. For example, the memristor array includes J bit lines (BL [0], BL [1] … … BL [ J-1]) and K source lines (SL [0], SL [1] … … SL [ K-1]), J being an integer greater than 1, and K being an integer greater than 1.

For example, the signal acquisition circuit 302 is used to acquire a plurality of input analog signals (not shown), and the signal acquisition circuit 302 inputs J input analog signals acquired by J sensors from corresponding bit lines into the memristor array. For example, one end of the memristor is connected with one source line of the memristor array, and the other end is connected with one bit line of the memristor array.

In this embodiment, the switch sub-circuit 305 shown in fig. 3A is a switch, and the accumulation circuit 306 shown in fig. 3A is an integration circuit, which is not limited to the structure shown in the figure. The end of each of the K source lines in the memristor array, that is, the K column signal output terminals, is electrically connected to the input terminal of the integration circuit 306 through a switch.

For example, for the ith column signal output end SL [ i ] of the memristor array, the tail end of the ith column signal output end SL [ i ] is electrically connected with the ith switch Sk [ i ] (0 ≦ i ≦ K-1, and i is a positive integer), when the switch Sk [ i ] is closed, the potential of the connected source line SL [ i ] (0 ≦ i ≦ K-1, and i is a positive integer) is zero, so that the connection between the column signal output end SL [ i ] and the input end of the integrating circuit is turned on, and the current signal output by the source line SL [ i ] is transmitted to the input end of the integrating circuit for accumulation calculation.

For example, under the control of the driving control circuit 303 shown in fig. 3A, the connections between the K column signal output terminals and the input terminals of the integration circuit are sequentially turned on at a first time interval τ (that is, the time interval for closing adjacent switches is τ), and the K first analog accumulation signals obtained by performing convolution processing on the memristor array sequentially are transmitted to the integration circuit.

For example, suppose that from time t, switch Sk [0]]To Sk [ K-1]Closed in sequence, only one switch being closed at the same time and each switch being closed for a time Δ τ_in(referred to as sample and hold time). For example, at time t + i τ, the ith switch Sk [ i [ i ] t ]]Input analog signals v from individual sensor channels when closed₀(t)、v₁(t)……v_J-1(t) has been delayed by i tau, so that the delay signal input by the memristor array bit line at this time can be used as vector c_i＝[v₀(t-iτ),v₁(t-iτ),v₂(t-iτ),…,v_J-1(t-iτ)]^TAnd (4) showing. According to kirchhoff's law, source line SL [ i ] in memristor array]Output current signal s_iFor delayed signals and conductance matrix w corresponding to the delayed signals_i＝[G_0,i,G_1,i,G_2,i,…,G_J-1,i]^TTo obtain the ith first analog accumulation signal

The first analog accumulated signal s is added_iVia a conducting switch Sk [ i ]]And transmitting the signal to an integrating circuit for integrating operation.

The above processes are performed in sequence, and after the K switches are closed in sequence, that is, at the time of t + K tau, the integration result s of the integration circuit is obtained_outComprises the following steps:

at this time, the integration result of the integration circuit is read and reset, and the next round of sampling integration is performed again, that is, the period of sampling integration is K τ.

It can be seen from the formula (2) and the formula (1) that the formula (2) and the formula (1) have the same form, in the formula (2), the coefficient vector of the filter is represented by the conductance value of the memristor, and the integral result represents a discrete filtering result.

Fig. 3D illustrates a sampling schematic diagram of a signal processing circuit provided by at least one embodiment of the present disclosure. As shown in fig. 3D, (1) represents the discrete output signal output by the signal processing circuit, and (2) represents the continuous output signal, and for example, the discrete output signal in (1) is subjected to interpolation, digital-to-analog conversion, or the like, so that the continuous output signal in (2) can be obtained.

As shown in fig. 3D, the time interval of closing of adjacent switches is τ, after K τ time, the output result of the integrating circuit is read and the integrating circuit is reset to enter the next sampling integration, so that the sampling time interval of the output signal is K τ.

For example, in a process of processing an analog signal, it is usually necessary to perform analog-to-digital conversion on the analog signal to convert the analog signal into a digital signal, and then perform processing on the digital signal to complete the processing on the analog signal.

The signal processing circuit provided by the embodiment of the disclosure can directly process an analog signal based on the memristor array, and does not need to convert the analog signal into a digital signal and then process the digital signal, so that the use of an analog-to-digital converter and the use of other hardware resources are reduced, the power consumption of the circuit is reduced, and the parallel multiply-add operation is performed by using the memristors, so that the computational power and the energy efficiency can be improved at the same time.

However, as shown in fig. 3D, the output sampling interval of the signal processing circuit is K τ, and the output sampling frequency decreases linearly as the length of the FIR filter increases. In order to increase the output sampling frequency, at least one embodiment of the present disclosure further provides a signal processing circuit, where the output circuit of the signal processing circuit sequentially obtains K first analog accumulated signals at a first time interval from a first time point under the control of the driving control circuit, and is further configured to sequentially obtain K second analog accumulated signals after the memristor array performs K-order convolution processing according to the first time interval from a time point i × T after the first time point under the control of the driving control circuit, and add the K second analog accumulated signals to obtain an ith second data fusion signal corresponding to a plurality of input analog signals, where i is a positive integer less than or equal to m-1, and i sequentially takes

values

1, 2, and. T represents a second time interval, and the ratio of the second time interval to the first time interval is N, N ═ K/m and is a positive integer.

For example, the sampling time interval of the first data fusion signal, the 1 st second data fusion signal, and the 2 nd second data fusion signal output by the signal processing circuit in sequence is a second time interval, that is, N τ, and since N is K/m, the output sampling frequency of the signal processing circuit is increased.

The schematic configuration of the signal processing circuit is shown in fig. 4A, and in fig. 4A, arrows indicate the signal flow direction.

As shown in fig. 4A, the output circuit 304 includes K switching sub-circuits 305 and an accumulation circuit 306. For example, the K switch sub-circuits 305 are switch sub-circuit 305_1, switch sub-circuit 305_2,. switch sub-circuit 305_ K-1, and switch sub-circuit 305_ K, respectively. Each switch sub-circuit 305The first input ends of the K switch sub-circuits 305 are respectively electrically connected with the K column signal output ends in a one-to-one correspondence manner, namely, are connected with the column signal output end SL [0] of the memristor array]To the column signal output terminal SL [ K-1]]One-to-one electrical connection, e.g. for switch sub-circuit 305_1, its first input terminal is connected to column signal input terminal SL [0]]Electrically connected, m first output terminals are respectively Sm₀[0]、Sm₀[1]、...Sm₀[m-1]For the switch sub-circuit 305_2, its first input terminal and the column signal input terminal SL [1]]Electrically connected, m first output terminals are respectively Sm₁[0]、Sm₁[1]、...Sm₁[m-1]And so on.

For example, accumulation circuit 306 includes m accumulation sub-circuits, which are accumulation sub-circuit 306_1, accumulation sub-circuit 306_ 2. Each accumulation sub-circuit includes a second input terminal and a second output terminal, e.g., accumulation sub-circuit 306_1 includes a second input terminal In [0] and a second output terminal Out [0], accumulation sub-circuit 306_2 includes a second input terminal In [1] and a second output terminal Out [1], and so on.

For example, m first output terminals of each switch sub-circuit 305 are electrically connected to m second input terminals of m accumulation sub-circuits in a one-to-one correspondence manner, for example, m first output terminals Sm of the switch sub-circuit 305_1₀[0]、Sm₀[1]、...Sm₀[m-1]Respectively and the second input terminal In [0] of the accumulation sub-circuit 306_1]Second input terminal In [1] of accumulation sub-circuit 306_2]A second input terminal In [ m-1] of the accumulation sub-circuit 306_ m]Electrically connected, m first output terminals Sm of the switch sub-circuit 305_2₁[0]、Sm₁[1]、...Sm₁[m-1]Respectively and the second input terminal In [0] of the accumulation sub-circuit 306_1]Second input terminal In [1] of accumulation sub-circuit 306_2]A second input terminal In [ m-1] of the accumulation sub-circuit 306_ m]Electrically connected, and so on.

For example, each of the m accumulation sub-circuits is configured to perform summation processing to obtain a first data fusion signal, a 1 st second data fusion signal, a 2 nd second data fusion signal, and an m-1 st second data fusion signal, respectively, and output the first data fusion signal, the 1 st second data fusion signal, the 2 nd second data fusion signal, and the m-1 st second data fusion signal through m second output terminals of the m accumulation sub-circuits, respectively. For example, the second output terminal Out [0] of the accumulation sub-circuit 306_1 outputs a first data fusion signal, the second output terminal Out [1] of the accumulation sub-circuit 306_2 outputs a 1 st second data fusion signal, and the second output terminal Out [ m-1] of the accumulation sub-circuit 306_ m outputs an m-1 th data fusion signal. For example, the K switch sub-circuits 305 are all electrically connected (not shown) to the driving control circuit 303 to receive the control signal of the driving control circuit 303, and implement corresponding operations according to the control signal.

For example, each of the switch sub-circuits 305 is configured to, under the control of the drive control circuit 303, at the same timing, make the column signal output terminal electrically connected to the switch sub-circuit 305 conductive with only one of the m second input terminals of the accumulation circuit 306, and make the column signal output terminal electrically connected to the switch sub-circuit 305 sequentially switch-connected to different second input terminals at the second time interval.

For example, for the switch sub-circuit 305_1, the switch sub-circuit 305_1 is configured to make the column signal output terminal SL [0] conduct only with the second input terminal In [0] at a first time T, conduct only with the second input terminal In [1] at a time T + T, and conduct only with the second input terminal In [ m-1] at a time T + (m-1) × T under the control of the driving control circuit 303.

For example, under the control of the drive control circuit 303, from a first time t, the K switch sub-circuits 305 are configured to sequentially turn on first input terminals of the K switch sub-circuits 305 and second input terminals of the 1 st accumulation sub-circuit at a first time interval, thereby sequentially outputting K first analog accumulation signals to the 1 st accumulation sub-circuit; and sequentially turning on first input terminals of the K switch sub-circuits 305 and second input terminals of the (i +1) th accumulation sub-circuit from i × T after the first time T according to a first time interval, thereby sequentially outputting K second analog accumulation signals to the (i +1) th accumulation sub-circuit, wherein i is a positive integer less than or equal to m-1, and i sequentially takes

values

1, 2,. m-1, m is a positive integer greater than 1 and less than or equal to K in time sequence, T represents a second time interval, and a ratio of the second time interval to the first time interval is N, and N is K/m and is a positive integer.

For example, under the control of the driving control circuit 303, at a first time t, the first input terminal of the switch sub-circuit 305_1 and the second input terminal In [0] of the accumulation sub-circuit 306_1]Is turned on to make the column signal output terminal SL [0]]The output first analog accumulated signal passes through the first output end Sm₀[0]Output to the accumulation sub-circuit 306_ 1; at time t + τ, the first input of switch sub-circuit 305_2 and the second input In [0] of accumulation sub-circuit 306_1]Is turned on to make the column signal output terminal SL [1]]The output first analog accumulated signal passes through the first output end Sm₁[0]Output to the accumulation sub-circuit 306_ 1; .., at time t + (K-1) τ, a first input of switch sub-circuit 305_ K and a second input In [0] of accumulation sub-circuit 306_1]Is turned on to make the column signal output terminal SL [ K-1]]The output first analog accumulated signal passes through the first output end Sm_K-1[0]Output to the accumulation sub-circuit 306_ 1.

For example, under the control of the driving control circuit 303, at time T after the first time T, i.e., at time T + T, the first input terminal of the switching sub-circuit 305_1 and the second input terminal In [1] of the accumulating sub-circuit 306_2]Is turned on to make the column signal output terminal SL [0]]The output second analog accumulated signal passes through the first output end Sm₀[1]Output to the accumulation sub-circuit 306_ 2; at time T + T + τ, the first input of switch sub-circuit 305_2 and the second input In [1] of accumulation sub-circuit 306_2]Is turned on to make the column signal output terminal SL [1]]The output second analog accumulated signal passes through the first output end Sm₁[1]Output to the accumulation sub-circuit 306_ 2. -, at time T + T + (K-1) τ, a first input terminal of the switch sub-circuit 305_ K and a second input terminal In [1] of the accumulation sub-circuit 306_2]Is turned on to make the column signal output terminal SL [ K-1]]The output second analog accumulated signal passes through the first output end Sm_K-1[1]Output to the accumulation sub-circuit 306_ 2.

For example, at time (m-1) T after the first time T, i.e., at time T + (m-1) T, the switch sub-circuit is switched under the control of the drive control circuit 303305_1 and a second input In [ m-1] of the accumulation sub-circuit 306_ m]Is turned on to make the column signal output terminal SL [0]]The output second analog accumulated signal passes through the first output end Sm₀[m-1]Output to the accumulation sub-circuit 306_ m; at time T + (m-1) T + τ, the first input of switch sub-circuit 305_2 and the second input In [ m-1] of accumulation sub-circuit 306_ m]Is turned on to make the column signal output terminal SL [1]]The output second analog accumulated signal passes through the first output end Sm₁[m-1]Output to the accumulation sub-circuit 306_ m., at time T + (m-1) T + (K-1) τ, a first input terminal of the switch sub-circuit 305_ K and a second input terminal In [ m-1] of the accumulation sub-circuit 306_ m]Is turned on to make the column signal output terminal SL [ K-1]]The output second analog accumulated signal passes through the first output end Sm_K-1[m-1]Output to the accumulation sub-circuit 306_ m.

For example, each switch has a closing time Δ τ_in(referred to as sample and hold time).

As shown in fig. 4B, the signal processing circuit includes a memristor array 301 and a signal obtaining circuit 302, and the description of the memristor array 301 and the signal obtaining circuit 302 may refer to the related contents of fig. 3C, and repeated descriptions are omitted.

In this embodiment, each switch sub-circuit 305 shown in FIG. 4A includes a switch of 1 to m, and the accumulation circuit 306 shown in FIG. 4A includes m integration circuits, i.e., each accumulation sub-circuit is 1 integration circuit, for example, as shown in FIG. 4B, the accumulation sub-circuit 306_1 is an integration circuit Int [0], the accumulation sub-circuit 306_ m is an integration circuit Int [ m-1], and so on. The integrating circuit is not limited to the configuration shown in the drawing, and may have another circuit configuration capable of realizing the accumulation function.

For example, the end of each of the K source lines in the memristor array 301, i.e., the K column signal outputs, is connected to the m integration circuits through one 1-to-m switch. For example, the ith column signal output terminal SL [ i ]]Is electrically connected with the 1 path input channel of a 1-to-m switch, and the m paths of the 1-to-m switch are respectively connected to the first output end Sm of the ith switch sub-circuit_i[0]A first output end Sm_i[1].., and a first output terminal Sm_i[m-1]A first output end Sm_i[0]A first output end Sm_i[1].., and a first output terminal Sm_i[m-1]Respectively connected with an integrating circuit Int [0]]Second input terminal In [0]]Int [1] integration circuit]Second input terminal In [1]]Integral circuit Int [ m-1]]Second input terminal In [ m-1]]And electrically connecting, wherein i is greater than or equal to 0 and less than m.

It should be noted that, in this embodiment, the number K of source lines and the number m of integration circuits satisfy K ═ Nm, N denotes a ratio of a sampling frequency of an input signal to a sampling frequency of an output signal, and m and N are positive integers. For example, for the ith column signal output SL [ i ] of the memristor array]Electrically connected 1-to-m switch Sk [ i ]]The 1-out-of-m switch switches to the next adjacent channel every second time interval, i.e., N τ. For example, a 1-to-m switch Sk [ i ]]Is switched to the first output terminal Sm at the time of t0_i[0]Thereby turning on the column signal output terminal SL [ i ]]And integration circuit Int [0]]Second input terminal In [0]]Are connected so that the column signal output terminal SL i]The output current signal is transmitted to an integrating circuit Int [0]]To accumulate; 1 m-selecting switch Sk [ i ]]The connection to the first output terminal Sm is switched at the time t0+ N τ_i[1]Thereby turning on the column signal output terminal SL [ i ]]And integrating circuit Int [1]]Second input terminal In [1]]Are connected so that the column signal output terminal SL i]The output current signal is transmitted to an integrating circuit Int [1]]Accumulating; 1 m-selecting switch Sk [ i ]]The connection to the first output terminal Sm is switched at the time t0+2N τ_i[2]Thereby turning on the column signal output terminal SL [ i ]]And integrating circuit Int [2 ]]Second input terminal In 2]Are connected so that the column signal output terminal SL i]The output current signal is transmitted to an integrating circuit Int [2 ]]And accumulating, and repeating the subsequent process in the same way.

For example, each integration circuit is connected to a different column signal input terminal at a first time interval τ apart, under the control of the drive control circuit 303. For example, at a first time t, 1 m-select switch Sk [0]]Is switched and connected to the first output end Sm₀[0]Thereby connecting the first column signal output terminal SL [0]]The output first analog accumulation signal is output to the integration circuit Int [0]]At time t + T, 1-to-m switch Sk [1]]Is switched and connected to the first output end Sm₁[0]Thereby connecting the second column signal output terminal SL [1]]The output first analog accumulation signal is output to the integration circuit Int [0]]And so on until m-selecting switch Sk [ K-1] is selected by 1 at the moment of t + (K-1) tau]Is switched and connected to the first output end Sm_K-1[0]So as to connect the K-th column signal output terminal SL [ K-1]]The output first analog accumulation signal is output to the integration circuit Int [0]]At an integrating circuit Int [0]]Output the first filtering result Out 0]Post reset integrator circuit Int [0]]。

For the switching connection process of the other m-from-1 switch, refer to the m-from-1 switch Sk [0] and the related contents in fig. 4A, and repeated descriptions are omitted.

For example, it is assumed that, from the first time t, the signal processing circuit performs signal processing in the manner described above, that is, for any one of the integration circuits, the signal processing circuit receives a first analog signal or a second analog signal every a first time interval τ, so that after K × τ, an integration result, that is, a filtering result, is output and reset. Because the time difference between the time when the two adjacent integrating circuits receive the first analog signal or the second analog signal is the second time interval N tau, the time delay of N tau exists between the integrating circuits in sequence, therefore, the time difference N tau of the filtering result output by each integrating circuit is N tau, and the output sampling interval is N tau.

For example, when the number of integrating circuits is K, i.e., m is K, where N is K/m is 1, the ratio of the input signal sampling frequency to the output signal sampling frequency is 1, and thus the output signal sampling time interval is also τ.

In this embodiment, the filtering result with the sampling interval shortened to N τ can be continuously output by sequentially reading the output result of the integrating circuit, and the output sampling interval can be shortened to be the same as the input sampling interval by configuring the number K of the accumulating sub-circuits, so that the sampling frequency is increased, and the sampling frequency is not limited by the order K of the filter.

Fig. 4C shows a switch connection diagram of the signal processing circuit shown in fig. 4B, and a connection flow of the K1-to-m switches is explained below with reference to fig. 4C.

In FIG. 4C, Sm_mN-N[0]Representing the first through mN-m switching sub-circuitsOutput end Sm_mN-N[0]Will be column signal output terminal SL [ mN-N]Is connected to an integrating circuit Int [0]]I.e. at time t0, the integrating circuit Int [0]]Receiving a signal from a column signal output terminal SL mN-N]Of the first analog sum signal Sm_mN-N+1[0]Denotes a first output terminal Sm passing through a mN-m +1 th switch sub-circuit_mN-N+1[0]The column signal output terminal SL [ mN-N +1]Is connected to Int [0]]I.e. at time t0+ tau, the integrating circuit Int [0 [ ]]Received from SL [ mN-N +1]The first analog accumulation signal, and so on.

Note that although the integration circuit Int [0]]The integration result is output and reset is performed at time t0+ (N-1) τ, but in practice it is already started before the first time t (not shown), i.e. at t- (K-N) τ via the first output Sm of the 1 st switching sub-circuit₀[0]Connected to the column signal output terminal SL [0]]And starts the integral calculation from the first time t.

Fig. 4D is a schematic diagram illustrating a design flow of a signal processing circuit according to at least one embodiment of the disclosure.

For example, as shown in fig. 4D, the design flow of the signal processing circuit includes steps S401 to S404.

Step S401: the filter order K, the sampling frequency f1 of the input signal, the sampling frequency f2 of the output signal, and the filter coefficient are obtained.

For example, in some embodiments, the user determines the sampling frequency f1 of the input signal and the sampling frequency f2 of the output signal as needed for use, and determines the FIR filter order K, filter coefficients, etc. as required for filtering.

Step S402: according to the sampling frequency f1 of the input signal and the sampling frequency f2 of the output signal, the frequency ratio N is calculated to be f1/f 2.

That is, the sampling time interval of the output signal divided by the sampling time interval of the input signal is N.

Step S403: and calculating the number m of the accumulation subcircuits to be K/N according to the order K of the filter and the frequency ratio N.

Step S404: the setting accumulation circuit comprises m accumulation sub-circuits, the setting output circuit comprises K switch sub-circuits, and each switch sub-circuit comprises m first output ends.

The specific connection modes among the switch sub-circuit, the memristor array and the accumulation sub-circuit refer to the embodiments described above, and are not described herein again.

For better understanding of the signal processing circuit shown in fig. 4B, K is 6 and m is 3.

Fig. 5A illustrates a signal processing circuit provided in at least one embodiment of the present disclosure.

According to the use requirement, the filter order K is 6, the sampling time interval of the input signal is τ, and the sampling time interval of the output signal is 2 τ, so that N is 2, and m is K/N is 3, that is, the accumulation circuit includes 3 accumulation sub-circuits, and the output circuit includes 6 switch sub-circuits, each of which includes 3 first output terminals.

As shown in FIG. 5A, the signal processing circuit includes a memristor array 301, the memristor array 301 includes 6 rows and 6 columns of memristor cells arranged in an array, 6 source lines (SL 0, SL 1 … … SL 5), 6 word lines, and 6 bit lines (word lines and bit lines are not shown), the 6 bit lines respectively receive input analog signals from 6 sensor channels (CH 0, CH 1 … … CH 5), and the output terminals of the 6 source lines respectively correspond to 6 column signal output terminals (SL 0, SL 1 … … SL 5).

The signal acquisition circuit 302 (not shown) is used to acquire input analog signals that are input to the memristor array 301 from the corresponding bit lines through 6 sensor channels.

In this embodiment, the switch sub-circuit 305 shown in fig. 4A includes a 1-to-3 switch, and the accumulation circuit 306 shown in fig. 4A includes 3 integration circuits, which are not limited to the structure shown in the figure. The output terminal of each of the 6 source lines in the memristor array 501, i.e. the 6 column signal output terminals, is connected to 3 integration circuits through one 3-out-of-1 switch, for example, each switch sub-circuit includes 3 first output terminals, for example, the switch sub-circuit 305_1 includes the first output terminal Sm₀[0]A first output end Sm₀[1]And a first output terminal Sm₀[2]。

For example, lettersSignal output terminal SL [0]]Through the first output Sm of the switch sub-circuit 305_1₀[0]Connected to an integrating circuit Int [0]]Column signal output terminal SL [0]]Through the first output Sm of the switch sub-circuit 305_1₀[1]Connected to an integrating circuit Int [1]]Column signal output terminal SL [0]]Through the first output Sm of the switch sub-circuit 305_1₀[2]Connected to an integrating circuit Int [2 ]]。

For example, for the column signal output SL [0] of the memristor array]Its end is connected to a switch Sk [0]]Electrically connected (the first output terminals Sm of the switch sub-circuits 305_1 are respectively turned on₀[0]、Sm₀[1]、Sm₀[2]) Switch Sk [0]]Switching to a different first output every interval 2 tau, i.e. 1-by-3 switching of Sk [0] at a first time t]Is switched and connected to the first output end Sm₀[0]Thereby connecting the first column signal output terminal SL [0]]The output first analog accumulation signal is output to the integration circuit Int [0]]Second input terminal In [0]]At time t +2 τ, 1 selects 3 switches Sk [0]]Is switched and connected to the first output end Sm₀[1]Thereby connecting the first column signal output terminal SL [0]]The output first analog accumulation signal is output to the integration circuit Int [1]]Second input terminal In [1]]At time t +4 τ, 1 selects 3 switches Sk [0]]Is switched and connected to the first output end Sm₀[2]Thereby connecting the first column signal output terminal SL [0]]The output first analog accumulation signal is output to the integration circuit Int [2 ]]Second input terminal In 2]Column signal output terminal SL [0]]And the second input terminal of the integrating circuit, the column signal output terminal SL [0]]The output current signal is transmitted to a second input end of the integrating circuit to carry out accumulation calculation.

For example, under the control of the drive control circuit 303 shown in FIG. 4A, each of the integration circuits is connected to a different column signal input terminal for a first time interval τ, e.g., a 3-out-of-1 switch Sk [0] at a first time t]Is switched and connected to the first output end Sm₀[0]Thereby connecting the first column signal output terminal SL [0]]The output first analog accumulation signal is output to the integration circuit Int [0]]At time t + T, 1 selects 3 switches Sk [1]]Is switched and connected to the first output end Sm₁[0]Thereby connecting the second column signal output terminal SL [1]]The output first analog accumulation signal is output to the integration circuit Int [0]]At time t +2 τ, 1Select 3 switch Sk 2]Is switched and connected to the first output end Sm₂[0]Thereby connecting the third column signal output terminal SL [2 ]]The output first analog accumulation signal is output to the integration circuit Int [0]]And so on until the moment t +5 tau, the switch Sk of 3 is selected from 1 to [5]]Is switched and connected to the first output end Sm₅[0]Thereby connecting the sixth column signal output terminal SL [5]]The output first analog accumulation signal is output to the integration circuit Int [0]]Int [0] integration circuit]Output the first filtering result Out 0]And reset integrating circuit Int [0]]. Since the multiplexer switches once at interval 2 τ, the results output by the plurality of integrating circuits are also spaced 2 τ apart.

Fig. 5B shows a switch connection schematic of the signal processing circuit shown in fig. 5A.

As shown in FIG. 5B, for example, an integrating circuit Int [0]]The first time interval tau is connected to different signal inputs. For example, as previously described, at a first time t, the switch Sk [0]]Is switched and connected to the first output end Sm₀[0]Thereby connecting the first column signal output terminal SL [0]]The output first analog accumulation signal is output to the integration circuit Int [0]]. At time t + T, switch Sk [0]]Is switched and connected to the first output end Sm₁[0]So that the second column signal output terminal SL [1] is connected]The output first analog accumulation signal is output to the integration circuit Int [0]]And so on until 1 selects 3 switches Sk [0] at time t +5 tau]Is switched and connected to the first output end Sm₅[0]Thereby connecting the sixth column signal output terminal SL [5]]The output first analog accumulation signal is output to the integration circuit Int [0]]. Integrating circuit Int [0]]、Int[1]And Int [2 ]]There is a 2 τ delay between them, so at time t +2 τ, the 1-to-3 switch Sk [1]]Is switched and connected to the first output end Sm₀[1]Thereby connecting the first column signal output terminal SL [0]]The output second analog accumulation signal is output to the integration circuit Int [1]]At time t + 3T, switch Sk [2 ] is selected from 3 to 1]Is switched and connected to the first output end Sm₁[1]Thereby connecting the second column signal output terminal SL [1]]The output second analog accumulation signal is output to the integration circuit Int [1]]And so on until 1 selects 3 switches Sk [6 ] at time t +7 tau]Is switched and connected to the first output end Sm₅[1]Thereby connecting the sixth column signal output terminal SL [5]]Output second analog accumulation signal outputTo an integrating circuit Int [1]]Reading Int [1] at time t +7 τ]Value of and reset Int [1]](ii) a At time t + 4T, 3 switches Sk [3 ] are selected 1]Is switched and connected to the first output end Sm₀[2]Thereby connecting the first column signal output terminal SL [0]]The output second analog accumulation signal is output to the integration circuit Int [2 ]]At time t + 5T, 3 switches Sk [4 ] are selected 1]Is switched and connected to the first output end Sm₁[2]Thereby connecting the second column signal output terminal SL [1]]The output second analog accumulation signal is output to the integration circuit Int [2 ]]And so on until 1 selects 3 switches Sk [6 ] at time t +9 tau]Is switched and connected to the first output end Sm₅[2]Thereby connecting the sixth column signal output terminal SL [5]]The output second analog accumulation signal is output to the integration circuit Int [2 ]]Reading Int [2 ] at time t +9 τ]Value of and reset Int [2 ]]。

For example, the drive control circuitry 303 includes array drive control circuitry coupled with the memristor array and configured to set the memristor array, write data corresponding to a convolution parameter matrix of a K-order convolution process to the memristor array, and control the memristor array to operate to perform the K-order convolution process on the plurality of input analog signals.

For example, the drive control circuit 303 includes a source line drive circuit, a word line drive circuit, and a bit line drive circuit. For example, the source line drive circuit is configured to control output signals of K source lines of the memristor array. For example, the word line drive circuit is configured to apply control signals to J word lines of the memristor array, respectively. For example, the bit line drive circuit is configured to apply input signals to J bit lines of a memristor array.

According to the method, time-sharing sampling is performed on a plurality of column signal output ends of a memristor array through a plurality of groups of integrating circuits, the requirements of a data conversion circuit and data temporary storage in a traditional implementation scheme (such as DSP) are eliminated, and highly parallel beam forming filtering is achieved by effectively utilizing multiply-add operation based on the memristor array. The output analog signals can be sent to a neural network computing unit based on a memristor array through a simple signal conditioning circuit to be subjected to back-end operation processing, and the intelligent sensing terminal integrating the sensor and the data processing unit can be conveniently and efficiently constructed.

For example, as described above, the conductance values of the memristors may be changed by applying a set voltage or a reset voltage to the memristors at the source line SL and the bit line BL, such that each memristor may be made to have a different conductance value, i.e., by changing the conductance values of the memristors to map the coefficient vector of the filter to the corresponding memristor.

In some embodiments of the present disclosure, a first memristor pair of two first memristors may be utilized to correspond to one element in a coefficient vector of a filter such that a negative value is included in the coefficient vector, such that a richer, complex filter may be implemented with multiple first memristors.

For example, one element of the coefficient vector of the filter may be implemented by two memristors. For example, two memristor arrays may be employed to form a plurality of memristor pairs, each memristor pair comprising two memristors. For example, the two memristors are disposed directly adjacent to each other in the memristor array; for another example, one memristor of each memristor pair is to receive an input analog signal, and the other memristor of the memristor pair is to receive an inverted input analog signal corresponding to the input analog signal.

Accordingly, in this embodiment, the signal acquisition circuit 302 is further configured to acquire a plurality of inverted input analog signals of the plurality of input analog signals, respectively.

An example of a memristor array capable of realizing a negative value element is specifically described below with reference to fig. 6A and 6B.

Fig. 6A is a schematic structural diagram of a memristor array provided in at least one embodiment of the present disclosure.

As shown in FIG. 6A, the memristor 701 and the memristor 702 may form a memristor pair, and the conductance value of the memristor 701 is represented as G₁₁The conductance value of the memristor 702 is denoted as G₁₂. Since the memristor 702 is connected to an inverter, when the memristor 701 is connected from the sensor channel CH [0]]The inverter can reverse the polarity of the voltage signal input from the sensor channel when receiving the input analog signal of positive polarity, thereby enablingThe memristor 702 receives an input analog signal of negative polarity. For example, at time t, the input analog signal received by the memristor 701 is v₀(t) denotes that the memristor 702 receives v₀(t) inverted input analog signal, i.e. -v₀(t) of (d). The

memristors

701 and 702 are connected to two different SLs, and the generation of the output current by the input analog signal through the memristors has been described in fig. 3A and will not be described again. The output current through the memristor 701 and the output current through the memristor 702 are superimposed at the SL termination. Thus, the result of the multiply-accumulate computation of

memristors

701 and 702 is v₀(t)G₁₁+(-v₀(t))G₁₂I.e. v₀(t)(G₁₁-G₁₂). Thus, a memristor pair consisting of memristor 701 and memristor 702 may correspond to one element in a coefficient vector of a filter, and the element is G₁₁-G₁₂By configuration G₁₁-G₁₂The numerical relationship of (c) may implement a negative element.

Fig. 6B is a schematic diagram of another memristor array provided in at least one embodiment of the present disclosure.

As shown in FIG. 6B, for example, the memristor 701 and memristor 702 may constitute a memristor pair, the conductance value of the memristor 701 being represented as G₁₁The conductance value of the memristor 702 is denoted as G₁₂. Unlike FIG. 6A, the memristor 702 is not connected to an inverter, so when the memristor 701 is from the sensor channel CH [0]]Upon receiving an input analog signal of positive polarity, the memristor 702 also receives an input analog signal of positive polarity. For example, at time t, the input analog signal received by the memristor 701 is v₀(t) the input analog signal received by the memristor 702 is also denoted by v₀(t) represents. The

memristors

701 and 702 are connected to two different SLs, and the output current through the memristor 701 and the output current through the memristor 702 are subtracted at the ends of the SLs. Thus, the result of the multiply-accumulate computation of

memristors

701 and 702 is v₀(t)G₁₁-v₀(t)G₁₂I.e. v₀(t)(G₁₁-G₁₂). Thus, a memristor pair composed of memristor 701 and memristor 702 may correspond to a coefficient direction of a filterAn element in the amount, and the element is G₁₁-G₁₂By configuration G₁₁-G₁₂The numerical relationship of (c) may implement a negative element.

In addition, the memristor cell of the 2T2R structure shown in fig. 2C may also be used to correspond to one element in the coefficient vector of the filter, so that a negative value is included in the coefficient vector, and thus a richer and more complex filter may be implemented by using the memristor cell of the 2T2R structure. An example of constructing a signal processing circuit using memristor cells of a 2T2R structure is described below with reference to fig. 6C and 6D.

Fig. 6C shows a signal processing circuit constructed with memristor cells of a 2T2R structure.

As shown in FIG. 6C, for example, a memristor cell of a 2T2R structure includes two memristors, memristor 701 and memristor 702 respectively, the conductance value of memristor 701 being denoted as G₁₁The conductance value of the memristor 702 is denoted as G₁₂The memristor 701 may be R1 in fig. 2C, and the memristor 702 may be R2 in fig. 2C. For example, since the memristor 702 is connected to an inverter, when the memristor 701 is from the sensor channel CH [0]]Upon receiving an input analog signal of positive polarity, the inverter may invert the polarity of the voltage signal input from the sensor channel, thereby causing the memristor 702 to receive an input analog signal of negative polarity. For example, at time t, the input analog signal received by the memristor 701 is v₀(t) denotes that the memristor 702 receives v₀(t) inverted input analog signal, i.e. -v₀(t) of (d). The

memristors

701 and 702 are connected to the same SL, at the end of which the output current through the memristor 701 and the output current through the memristor 702 are superimposed. Thus, the result of the multiply-accumulate computation of

memristors

701 and 702 is v₀(t)G₁₁+(-v₀(t))G₁₂I.e. v₀(t)(G₁₁-G₁₂). Thus, a memristor cell of a 2T2R

structure containing memristors

701 and 702 may correspond to one element in the coefficient vector of the filter, and that element is G₁₁-G₁₂By configuration G₁₁-G₁₂Can realize negativityA value element.

Fig. 6D shows another signal processing circuit constructed with memristor cells of the 2T2R structure.

As shown in FIG. 6D, for example, a memristor cell of a 2T2R structure includes two memristors, memristor 701 and memristor 702, respectively, the conductance value of memristor 701 being denoted as G₁₁The conductance value of the memristor 702 is denoted as G₁₂. Unlike FIG. 6C, the memristor 702 is not connected to an inverter, so when the memristor 701 is from the sensor channel CH [0]]Upon receiving an input analog signal of positive polarity, the memristor 702 also receives an input analog signal of positive polarity. For example, at time t, the input analog signal received by the memristor 701 is v₀(t) the input analog signal received by the memristor 702 is also denoted by v₀(t) represents. The

memristors

701 and 702 are connected to different SLs, and the output current through the memristor 701 and the output current through the memristor 702 are subtracted at the SL termination. Thus, the result of the multiply-accumulate computation of

memristors

701 and 702 is v₀(t)G₁₁-v₀(t)G₁₂I.e. v₀(t)(G₁₁-G₁₂). Thus, a memristor cell of a 2T2R

structure containing memristors

701 and 702 may correspond to one element in the coefficient vector of the filter, and that element is G₁₁-G₁₂By configuration G₁₁-G₁₂The numerical relationship of (c) may implement a negative element.

For example, the memristor array in the signal processing circuit provided by at least one embodiment of the present disclosure may adopt any one of the structures as provided in fig. 6A to 6D to implement the element negative value in the filter vector, which is not limited by the present disclosure.

For example, when the signal processing circuit is applied to a beamforming system, the signal processing circuit may also be applied to adaptive beamforming, for example, after filtering operation is performed for a certain period of time, an updated value of a filter coefficient is calculated by using a Least Mean Square (LMS) method, a Linear Constrained Minimum Variance (LCMV) method, or the like, and the updated value of the filter coefficient is mapped to a corresponding memristor unit by an array driving control circuit to continue the filtering operation. It should be noted that the signal processing circuitry may also be used to construct a system having multiple beamforming arrays, such as generalized sidelobe cancellation.

For example, as shown in fig. 7, the signal processing method provided by the embodiment of the present disclosure includes steps S601 to S603.

Step S601: a plurality of input analog signals are acquired.

For example, the plurality of input analog signals may be analog signals collected by a plurality of sensors.

Step S602: performing K-order convolution processing on a plurality of input analog signals by using a memristor array, wherein K is an integer larger than 1.

For example, a memristor array may refer to the schematic diagram of the memristor array shown in fig. 2A.

For example, step S602 may include: the method comprises the steps of inputting a plurality of input analog signals into a plurality of column signal input ends of a memristor array after setting, controlling the memristor array to operate so as to carry out convolution processing on the plurality of analog signals, and obtaining a plurality of second analog accumulated signals or second analog accumulated signals after K-order convolution processing at a plurality of row signal output ends of the memristor array.

Specifically, a plurality of input analog signals can be respectively applied to a plurality of bit lines of the memristor array after setting, meanwhile, a turn-on signal is applied to a plurality of word lines of the memristor array, and a plurality of current signals of a plurality of column signal output ends of the memristor array, namely a second analog accumulation signal or a second analog accumulation signal, can be detected and acquired.

Step S603: according to a first time interval, K first analog accumulated signals after the memristor array executes K-order convolution processing are sequentially obtained, and the K first analog accumulated signals are subjected to addition processing to obtain first data fusion signals corresponding to the plurality of input analog signals.

For example, the signal processing method may be applied to the signal processing circuit described above with reference to fig. 3A to 3C. In step S601, a plurality of input analog signals may be acquired by the signal acquisition circuit 302 in the signal processing circuit, for example; in step S603, the first data fusion signal corresponding to the plurality of input analog signals can be obtained by the output circuit 304 in the signal processing circuit shown in fig. 3A to 3C, for example.

In the following, referring to fig. 3A to fig. 3C, a brief description is given to an embodiment of a signal processing method provided by at least one embodiment of the present disclosure, and specifically, reference may be made to the foregoing description.

For example, the memristor array 301 includes K column signal output terminals, the K column signal output terminals are used for correspondingly outputting K first analog accumulation signals processed by K-order convolution, the output circuit 304 includes K switch sub-circuits 305 and an accumulation circuit 306, input terminals of the K switch sub-circuits 305 are respectively electrically connected with the K column signal output terminals one by one, and output terminals of the K switch sub-circuits 305 are all electrically connected with input terminals of the accumulation circuit 306. In this case, step S603 may include: sequentially conducting the connection between the corresponding column signal output ends and the input end of the accumulation circuit by using K switch sub-circuits according to a first time interval, and transmitting K first analog accumulation signals obtained after convolution processing is executed on the memristor array to the accumulation circuit; and the K first analog accumulated signals are subjected to summation processing by using an accumulation circuit to obtain a first data fusion signal.

According to the signal processing method provided by the embodiment, the received input analog signals are directly subjected to analog operation through the memristor array, a data conversion circuit is prevented from being introduced, delay and temporary storage of the input analog signals are realized through a post-sampling mode, highly parallel multiply-add operation is realized through the memristor array, and therefore computing power and energy efficiency are improved simultaneously.

For example, K first analog accumulation signals are sequentially obtained at a first time interval from a first time t, and the signal processing method according to at least one embodiment of the present disclosure further includes step S604: sequentially obtaining K second analog accumulation signals after K-order convolution processing is executed on the memristor array from i × T moment after the first moment T according to a first time interval, and performing summation processing on the K second analog accumulation signals to obtain an ith second data fusion signal corresponding to the input analog signals, wherein i is a positive integer less than or equal to m-1, i sequentially takes values of 1, 2,.. m-1, m is a positive integer greater than 1 and less than or equal to K, T represents a second time interval, and the ratio of the second time interval to the first time interval is N, and N is K/m and is a positive integer.

For example, the signal processing method may be applied to the signal processing circuit described above with reference to fig. 4A to 4C. In step S601, a plurality of input analog signals may be acquired by the signal acquisition circuit 302 in the signal processing circuit, for example; in step S603, for example, a first data fusion signal, a first second data fusion signal,. m-1 th second data fusion signal corresponding to the plurality of input analog signals may be obtained by the output circuit 304 in the signal processing circuit, and an output sampling time interval between the first data fusion signal, the first second data fusion signal,. m-1 th second data fusion signal is a second time interval.

In the following, referring to fig. 4A to 4C, a brief description is given to an embodiment of a signal processing method provided by at least one embodiment of the present disclosure, and specifically, reference may be made to the foregoing description.

For example, the memristor array 301 includes K column signal outputs for outputting K first analog accumulation signals of K order convolution processing, the output circuit 304 includes K switching sub-circuits 305 and an accumulation circuit 306, each switching sub-circuit 305 includes one switch of 1 to m, and the accumulation circuit 306 includes m integration circuits. Each switch sub-circuit 305 includes 1 first input terminal and m first output terminals, the first input terminals of the K switch sub-circuits 305 are electrically connected to the K column signal output terminals in a one-to-one correspondence, and the m first output terminals of each switch sub-circuit 305 are electrically connected to the m second input terminals of the m summation sub-circuits in a one-to-one correspondence. In this case, step S604 may include: starting from a first time t, sequentially connecting first input terminals of the K switch sub-circuits 305 with a second input terminal of a 1 st accumulation sub-circuit at a first time interval, thereby sequentially outputting K first analog accumulation signals to the 1 st accumulation sub-circuit; and sequentially turning on first input terminals of the K switch sub-circuits 305 and second input terminals of the (i +1) th accumulation sub-circuit from i × T after the first time T according to a first time interval, thereby sequentially outputting K second analog accumulation signals to the (i +1) th accumulation sub-circuit, wherein i is a positive integer less than or equal to m-1, and i sequentially takes

values

The signal processing method provided by the above embodiment can continuously output the sampling interval shortened to N τ by sequentially reading the output result of the integrating circuit, thereby improving the sampling frequency.

For the present disclosure, there are also the following points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Thicknesses and dimensions of layers or structures may be exaggerated in the drawings used to describe embodiments of the present invention for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A signal processing circuit, comprising:

a drive control circuit;

a signal acquisition circuit configured to acquire a plurality of input analog signals;

a memristor array, wherein the memristor array is configured to perform K-order convolution processing on the plurality of input analog signals, K being an integer greater than 1;

and the output circuit is configured to sequentially obtain K first analog accumulated signals obtained by the memristor array after the K-order convolution processing is executed and add the K first analog accumulated signals at a first time interval under the control of the driving control circuit, so as to obtain first data fusion signals corresponding to the input analog signals.

2. The signal processing circuit according to claim 1, wherein the output circuit obtains the K first analog accumulation signals in order at the first time interval from a first timing under control of the drive control circuit,

the output circuit is further configured to, under control of the drive control circuit, sequentially obtain, according to the first time interval, K second analog accumulation signals after the memristor array performs the K-order convolution processing from an i × T time after the first time, and add the K second analog accumulation signals to obtain an ith second data fusion signal corresponding to the plurality of input analog signals,

wherein i is a positive integer less than or equal to m-1, and i takes values 1, 2,. m-1 in chronological order, m is a positive integer greater than 1 and less than or equal to K, T represents a second time interval, and the ratio of the second time interval to the first time interval is N, and N is K/m and is a positive integer.

3. The signal processing circuit of claim 1, wherein the memristor array includes K column signal outputs to correspondingly output K first analog accumulation signals of the K-th order convolution processing,

the output circuit comprises K switching sub-circuits and an accumulation circuit,

the input ends of the K switch sub-circuits are respectively and electrically connected with the K row signal output ends one by one, the output ends of the K switch sub-circuits are all electrically connected with the input end of the accumulation circuit,

the K switching sub-circuits are configured to sequentially conduct the connection between the corresponding column signal output ends and the input end of the accumulation circuit according to the first time interval under the control of the driving control circuit, and transmit K first analog accumulation signals obtained after the memristor array performs the convolution processing to the accumulation circuit,

the summation circuit is configured to sum the K first analog summation signals to obtain the first data-fused signal.

4. The signal processing circuit of claim 3, wherein the accumulation circuit is an integration circuit, and the drive control circuit is further configured to reset the integration circuit after the first data fusion signal is derived.

5. The signal processing circuit of claim 2, wherein the memristor array further comprises K column signal outputs to correspondingly output the K second analog accumulated signals or the K first analog signals of the K-order convolution processing,

each switch sub-circuit comprises 1 first input terminal and m first output terminals,

the summation circuit comprises m summation sub-circuits, each of the m summation sub-circuits comprising a second input and a second output,

the first input ends of the K switch sub-circuits are respectively and correspondingly electrically connected with the K row signal output ends one by one,

the m first output ends of each switch sub-circuit are respectively and correspondingly electrically connected with the m second input ends of the m accumulation sub-circuits one by one,

each of the m accumulation sub-circuits is configured to perform summation processing to obtain the first data fusion signal, the 1 st second data fusion signal, the 2 nd second data fusion signal, and the m-1 st second data fusion signal, respectively, and output the first data fusion signal, the 1 st second data fusion signal, the 2 nd second data fusion signal, and the m-1 st second data fusion signal through m second output terminals of the m accumulation sub-circuits, respectively.

6. The signal processing circuit of claim 5,

each switch sub-circuit is configured to:

under the control of the drive control circuit, at the same time, the column signal output terminal electrically connected to the switch sub-circuit is made conductive with only one of the m second input terminals of the accumulation circuit, and

and sequentially switching and connecting the column signal output ends electrically connected with the switch subcircuits to different second input ends according to the second time interval.

7. The signal processing circuit of claim 5,

under the control of the driving control circuit, starting from the first time, the K switching sub-circuits are further configured to sequentially turn on the K column signal output terminals and the second input terminal of the 1 st accumulation sub-circuit at the first time interval, so as to sequentially output K first analog accumulation signals to the 1 st accumulation sub-circuit; and

under the control of the drive control circuit, sequentially turning on the K column signal output ends and the second input end of the (i +1) th accumulation sub-circuit according to the first time interval from the i × T time after the first time, thereby sequentially outputting the K second analog accumulation signals to the (i +1) th accumulation sub-circuit.

8. The signal processing circuit of any of claims 5-7, wherein the switch sub-circuit comprises a 1-to-m switch circuit,

the 1-to-m switch circuit comprises m channels, and the m channels are respectively electrically connected with the m first output ends.

9. The signal processing circuit of any of claims 5-7, wherein the accumulation sub-circuit is an integration circuit,

the drive control circuit is further configured to perform a reset operation on the integration circuit after the integration circuit outputs the first data fusion signal or the ith second data fusion signal.

10. The signal processing circuit of any of claims 1-7, wherein the drive control circuit comprises an array drive control circuit,

the array drive control circuit is coupled with the memristor array and configured to set the memristor array, write data of a convolution parameter matrix corresponding to a K-order convolution process into the memristor array, and control the memristor array to operate to perform the K-order convolution process on the plurality of input analog signals.

11. The signal processing circuit of claim 3 or 5,

the number of the plurality of input analog signals is J,

the memristor array comprises J rows and K columns of memristor units which are arranged in an array, the J rows are respectively used for receiving the plurality of input analog signals, and the K columns respectively correspond to the K column signal output ends.

12. A signal processing method, comprising:

acquiring a plurality of input analog signals;

performing K-order convolution processing on the plurality of input analog signals by using a memristor array, wherein K is an integer greater than 1;

and sequentially obtaining K first analog accumulated signals of the memristor array after the K-order convolution processing is executed according to a first time interval, and adding the K first analog accumulated signals to obtain first data fusion signals corresponding to the input analog signals.

13. The signal processing method of claim 12, wherein the K first analog accumulation signals are sequentially obtained at first time intervals from a first time,

the method further comprises the following steps:

sequentially obtaining K second analog accumulated signals after the memristor array executes the K-order convolution processing from the i x T moment after the first moment according to the first time interval, and adding the K second analog accumulated signals to obtain ith second data fusion signals corresponding to the input analog signals,

wherein i is a positive integer less than or equal to m-1, and i is sequentially set to 1, 2,. m-1, m is a positive integer greater than 1 and less than or equal to K, T represents a second time interval, and the ratio of the second time interval to the first time interval is N, and N is K/m and is a positive integer.