CN114268320A

CN114268320A - Digital-to-analog conversion circuit, electronic device and operation method

Info

Publication number: CN114268320A
Application number: CN202111591131.8A
Authority: CN
Inventors: 高滨; 贾郅平; 党琦; 唐建石; 钱鹤; 吴华强
Original assignee: Tsinghua University; Beijing Superstring Academy of Memory Technology
Current assignee: Tsinghua University; Beijing Superstring Academy of Memory Technology
Priority date: 2021-12-23
Filing date: 2021-12-23
Publication date: 2022-04-01

Abstract

A digital-to-analog conversion circuit, an electronic device and an operation method. The digital-to-analog conversion circuit includes: a first voltage terminal; a second voltage terminal; the memristor string module comprises M memristors, M first output ends and a mode switching module; the memristor setting module comprises M first input ends, a second control signal input end and M third voltage ends; the multi-path selection module comprises M second input ends, M digital signal input ends and second output ends, and is configured to correspondingly select one of the M second input ends to be electrically connected with the second output end according to the digital conversion signal; wherein M is 2M, and M is an integer greater than 1. The digital-to-analog conversion circuit can express multi-bit data to match various nonlinear functions, so that the generation interval of nonlinear analog signals is widened.

Description

Digital-to-analog conversion circuit, electronic device and operation method

Technical Field

Embodiments of the present disclosure relate to a digital-to-analog conversion circuit, an electronic apparatus, and an operating method.

Background

Digital-to-Analog Converter (DAC) is an important functional module in the field of integrated circuits, and is a key bridge for connecting Digital and Analog values in a circuit system. The corresponding digital-to-analog conversion circuit is manufactured according to a specific common nonlinear function, and each gear of the DAC can be fully utilized, so that the scale of the circuit can be reduced, the storage bit width of a digital signal is reduced, the generation interval of an analog signal is widened, and the like.

The memristor is a basic device capable of changing the resistance value according to the charge flowing through the device, and compared with a common resistor, the resistance value of the memristor can be set by applying a proper voltage pulse signal to two ends. The memristor naturally has the functions of resistance and the programmable characteristics, so that the memristor is very suitable for replacing the constant-value resistance in the resistance network of the traditional DAC.

Disclosure of Invention

At least one embodiment of the present disclosure provides a digital-to-analog conversion circuit, including: a first voltage terminal configured to receive a first voltage; a second voltage terminal configured to receive a second voltage; a memristor string module, comprising: the memristors are sequentially connected in series, two end points of a memristor string formed by the M memristors are respectively and electrically connected with the first voltage end and the second voltage end, M first output ends are respectively corresponding to the second voltage end and M-1 middle connection points between adjacent memristors in the M memristors, and the mode switching module comprises a first control signal input end, wherein the first control signal input end is configured to receive a first control signal, and the mode switching module is configured to disconnect or establish electrical connection between any pair of adjacent memristors in the M memristors according to the first control signal; a memristor setting module including M first input terminals configured to receive M operating voltages, a second control signal input terminal configured to receive a second control signal, and M third voltage terminals, the memristor setting module being coupled with the memristor string module and configured to couple the M memristors between the M first input terminals and the M third voltage terminals, respectively, according to the second control signal; and a multiplexing module, including M second input terminals, M digital signal input terminals and second output terminals, wherein the M second input terminals are electrically connected to the M first output terminals in a one-to-one correspondence, the M digital signal input terminals are configured to receive a digital conversion signal having M bits, the second output terminals are configured to output an analog voltage signal, and the multiplexing module is coupled to the memristor string module and configured to correspondingly select one of the M second input terminals to be electrically connected to the second output terminal according to the digital conversion signal; wherein M is 2M, and M is an integer greater than 1.

For example, the mode switching module further includes M-1 first switches M1, an ith first switch M1 of the M-1 first switches M1 connects an ith memristor of the M memristors and an i +1 th memristor, and a control terminal of the M-1 first switch M1 is electrically connected to the first control signal input terminal to receive the first control signal, where i is 1,2, …, M-1.

For example, the memristor setting module includes M second switches M2 and M-1 third switches M3, a first end of a jth second switch M2 of the M second switches M2 is electrically connected to a jth one of the M first input ends, a second end of the jth second switch M2 is electrically connected to a first end of a jth one of the M memristors, and a control end of the jth second switch M2 is electrically connected to the second control signal input end to receive the second control signal, where j is 1,2, …, M; in the M-1 third switches M3, a first end of an h-th third switch M3 is electrically connected to a second end of an h + 1-th of the M memristors, a second end of the h-th third switch M3 is electrically connected to an h-th of the M third voltage ends, and a control end of the h-th third switch M3 is electrically connected to the second control signal input end to receive the second control signal, wherein h is 1,2, …, M-1.

For example, the M third voltage terminals are electrically connected to each other.

For example, the multiplexing module includes m switch submodules, an a-th one of the m switch submodules being electrically connected to an a-th one of the m digital signal inputs, the a-th one of the m digital signal inputs being configured to receive an a-th bit of the digitally converted signal, where a is 0,1,2, …, m-1; among the m switch sub-modules, the a-th switch sub-module has 2^ (m-a) inputs and 2^ (m-a-1) outputs and is configured to select 2^ (m-a-1) outputs from the 2^ (m-a) pairs of inputs; except for the (m-1) th switch submodule, the output of the (a) th switch submodule is respectively used as the input of the (a + 1) th switch submodule.

For example, at least one pair of adjacent memristors of the M memristors has unequal resistances.

For example, the M accumulated values generated by sequentially accumulating the resistances of the M memristors vary nonlinearly.

For example, the M third voltage terminals are connected to the same voltage as the second voltage terminal.

At least one embodiment of the present disclosure further provides an electronic device including the digital-to-analog conversion circuit according to any one of the above embodiments.

For example, the electronic device further includes: a control module configured to provide the first control signal and the second control signal; and an operating voltage providing module coupled to the M first inputs and configured to provide the M operating voltages.

At least one embodiment of the present disclosure further provides an operating method of any one of the digital-to-analog conversion circuits, including: setting all the m digital signal input ends of the digital conversion signal of the multi-path selection module to be zero; receiving the first control signal and the second control signal, wherein the first control signal is an off potential to cause an electrical connection to be broken between any pair of adjacent memristors in the M memristors, and the second control signal is an on potential to cause the memristor string module to enter a set mode; receiving the M operating voltages at the M first input ends, and respectively carrying out setting operation on the M memristors according to the M operating voltages.

For example, the set operation includes: obtaining an array R '[ M ] of M target resistance values of the M memristors, and inputting the array R' [ M ] to a pulse signal generator; receiving the M operating voltages generated by the pulse signal generator according to an array R' [ M ]; inputting the M operating voltages to the M first input terminals to set resistance values of the M memristors, respectively.

For example, obtaining an array R "[ M ] of M target resistances for the M memristors includes: representing a resistance value of each of the M memristors as 2^ n resistance steps, where n is a positive integer; sampling a nonlinear signal curve to obtain M +1 gear values; carrying out forward difference on the M +1 gear values, calculating M relative values, respectively corresponding to the resistance values of the M memristors, and recording as an array R [ M ]; finding the maximum value Rmax in the array R [ M ]; calculating a mapping proportion k ^ 2^ n/Rmax so that the maximum value Rmax is mapped to a 2^ n gear in the 2^ n resistance gears; multiplying each numerical value in the array R [ M ] by the mapping proportion k to obtain a mapped array R' [ M ]; and performing nearest neighbor rounding on each numerical value in the array R ' [ M ] to obtain an array R ' [ M ] after the nearest neighbor rounding, so that the g-th numerical value in the array R ' [ M ] is mapped to the 2^ n resistance gears of the g-th memristor in the M memristors, wherein g is 1,2, … and M.

For example, at least one embodiment of the present disclosure further provides another method for operating a digital-to-analog conversion circuit, where the method includes: receiving the first control signal and the second control signal, wherein the second control signal is an off potential to cause the memristor string module to exit a set mode, the first control signal is an on potential to cause an electrical connection to be established between any pair of adjacent memristors among the M memristors, and M reference divided voltages are generated on the M memristors; and receiving the digital conversion signal, and inputting the digital conversion signal into the multi-path selection module, wherein the multi-path selection module selects a corresponding reference divided voltage from the M reference divided voltages according to the digital conversion signal, and outputs the selected reference divided voltage as the analog voltage signal from the second output terminal.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 is a schematic diagram of a non-linear signal;

fig. 2 is a schematic block diagram of a digital-to-analog conversion circuit provided in some embodiments of the present disclosure;

fig. 3 is a schematic diagram of a digital-to-analog conversion circuit according to some embodiments of the present disclosure;

fig. 4 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure;

fig. 5 is a flowchart of a setting mode operation method of a digital-to-analog conversion circuit according to some embodiments of the present disclosure;

fig. 6 is a flowchart of an operation method of an operation mode of a digital-to-analog conversion circuit according to some embodiments of the present disclosure; and

FIG. 7 is a flow chart of a memristor resistance nonlinear set operation method provided by some embodiments of the present disclosure;

fig. 8 is a schematic block diagram of memristor-based non-linear programmable digital-to-analog conversion circuitry provided in some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The present disclosure is illustrated by the following specific examples. Detailed descriptions of known functions and known components may be omitted in order to keep the following description of the embodiments of the present disclosure clear and concise. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numeral in each drawing.

In a traditional digital-to-analog conversion circuit, three indexes of conversion precision, circuit scale and delay time are difficult to be considered, especially when a nonlinear analog signal needs to be generated, the conversion precision of a part of intervals cannot be effectively utilized, and meanwhile, the digital-to-analog conversion precision of another part of intervals is insufficient, so that the minimum digital unit cannot reflect the fine difference required by the analog signal.

For the design of the non-linear digital-to-analog conversion circuit, the first kind of improvement method is to change the resistance relation in the resistance network, and most of the improvement methods are designed for a specific non-linear function, for example, a DAC with an exponential function curve or a DAC with a logarithmic function curve is separately implemented. The application field of the digital-to-analog conversion circuit is limited, and other nonlinear analog signals required by a user cannot be generated in time. The second kind of improvement method is to introduce a certain degree of programmable function, generally, the sampling result of the nonlinear function needs to be stored based on a time sequence circuit and a storage function module, so that the scale of the circuit is increased to a great extent, and the introduction of the time sequence module increases the delay of the digital-to-analog conversion circuit in the using process and reduces the speed of the digital-to-analog conversion circuit.

For example, fig. 1 shows a non-linear signal curve. If a proper nonlinear digital-to-analog conversion circuit is used for fitting 8 gears, namely, 3bit digital signals, in the curve, namely, dot1, dot2, … and dot 8. If a linear digital-to-analog conversion circuit is used, the minimum gear must be represented (0.6-0.0 ≈ 0.6), and the range width of the analog signal is about 32.1, at least one DAC with 32.1/0.6 ≈ 53.5 is required at this time, that is, an 8-bit digital signal can be represented. This not only increases the size and power of the digital-to-analog conversion circuit, but also makes digital storage redundant and inefficient.

At least one embodiment of the present disclosure provides a digital-to-analog conversion circuit, including a first voltage terminal, a second voltage terminal, a memristor string module, a memristor setting module, and a multi-path selection module. The first voltage terminal is configured to receive a first voltage; the second voltage terminal is configured to receive a second voltage. The memristor string module includes: the memristors are sequentially connected in series, and two end points of a memristor string formed by the M memristors are respectively and electrically connected with a first voltage end and a second voltage end; the M first output ends respectively correspond to the second voltage end and M-1 middle connection points between adjacent memristors in the M memristors; the mode switching module comprises a first control signal input end, wherein the first control signal input end is configured to receive a first control signal, and the mode switching module is configured to enable any pair of adjacent memristors in the M memristors to be electrically disconnected or electrically connected according to the first control signal. The memristor setting module includes M first input terminals configured to receive M operating voltages, a second control signal input terminal configured to receive a second control signal, and M third voltage terminals, and is coupled with the memristor string module and configured to couple the M memristors between the M first input terminals and the M third voltage terminals, respectively, according to the second control signal. The multi-path selection module comprises M second input ends, M digital signal input ends and second output ends, wherein the M second input ends are electrically connected with the M first output ends in a one-to-one correspondence mode, the M digital signal input ends are configured to receive digital conversion signals with M bits, the second output ends are configured to output analog voltage signals, and the multi-path selection module is coupled with the memristor string module and is configured to correspondingly select one of the M second input ends to be electrically connected with the second output end according to the digital conversion signals; wherein M is 2M, and M is an integer greater than 1.

At least one embodiment of the present disclosure further provides an electronic device including the digital-to-analog conversion circuit.

At least one embodiment of the present disclosure further provides an operating method corresponding to the digital-to-analog conversion circuit.

According to the digital-to-analog conversion circuit, the electronic device and the operation method, on the basis of a traditional digital-to-analog conversion circuit, an original resistor is replaced by a memristor, and two modes of setting and working of the digital-to-analog conversion circuit can be switched. By adjusting the resistance values of the memristors, the digital-to-analog conversion circuit can express multi-bit data to match various nonlinear functions, so that the generation interval of nonlinear analog signals is widened. In at least one embodiment of the present disclosure, since the storage function module and the sequential circuit do not need to be additionally introduced, the scale of the circuit is reduced, and the transmission efficiency is improved.

Some embodiments of the disclosure are described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic block diagram of a digital-to-analog conversion circuit according to some embodiments of the present disclosure.

For example, as shown in fig. 2, the digital-to-analog conversion circuit 100 includes a first voltage terminal, a second voltage terminal, a memristor string module 110, a memristor setting module 120, and a multiplexing module 130.

Two terminals of the memristor string module 110 are electrically connected with the first voltage terminal and the second voltage terminal, respectively. The first voltage terminal is configured to receive a first voltage V1, and the second voltage terminal is configured to receive a second voltage V2. For example, the first voltage V1 may be configured as a reference potential (Vref) for digital-to-analog conversion, and the second voltage V2 may be configured as Ground (GND). The memristor string module 110 also includes a first control signal input. The first control signal input is configured to receive a first control signal Von 1. For example, by setting the first control signal Von1 to be at an on or off potential, the electrical connection between adjacent memristors inside the memristor string module 110 may be controlled to be made or broken. The memristor string module 110 also includes M first outputs, M being an integer greater than 1. The M first outputs are configured to output the voltage signal on the memristor string module 110 to the multiplexing module 130.

In at least one embodiment of the present disclosure, the memristor may be, for example, a resistive switching memory, a phase change memory, a conductive bridge memory, or the like. For example, in the case where the memristor is a resistive random access memory, the memristor is a stacked structure prepared by a semiconductor process, including two opposing electrode layers (e.g., metal electrodes) and a memory material layer interposed between the two electrodes, the memory material layer may further be a stacked structure including a combination of a plurality of material layers. For example, the combination of the material layers may result in a laminated structure of TiN/HfAlO_x/TaO_x/TiN or TiN/HfO₂/TaO_x/TiN or TiN/HfO₂/TiN or TiN/HfZrO_x/TaO_x/TiN or TiN/HfAlZrO_x/TaO_x/TiN or TiN/SiO₂TiN, etc., as embodiments of the present disclosure are not limited in this regard.

For example, the memristor setting module 120 is coupled with the memristor string module 110 and includes M first input terminals, a second control signal input terminal, and M third voltage terminals (not shown in the figure). Wherein M is 2M, and M is an integer greater than 1. The M first input terminals are configured to receive M operation voltages VP <1>, VP <2> … … VP < M >. For example, the M third voltage terminals may be separately provided or electrically connected to each other and terminate at the same voltage as the second voltage terminal. For example, the M third voltages may be configured as Ground (GND).

The second control signal input is configured to receive a second control signal Von 2. The memristor setting module 120 is configured to couple the M memristors between the M first input terminals and the M third voltage terminals, respectively, according to the second control signal Von2, whereby each memristor may be set (e.g., initialized, set, reset, etc.) separately by selecting a voltage difference applied across each memristor. For example, a set voltage is applied to cause the memristor to be in a low resistance state; a reset voltage is applied to cause the memristor to be in a high resistance state. For example, the resistance value of the memristor in the high resistance state is more than 100 times, for example, more than 1000 times, the resistance value in the low resistance state, and different required operating voltages with different resistance values can be selected according to the electrical characteristic curve of the memristor.

For example, the multiplexing module 130 includes m digital signal inputs d <0>, d <1> … … d < m-1> configured to receive a digitally converted signal having m bits. The multiplexing module 130 is coupled to the memristor string module 110 through M second input terminals, and correspondingly selects one of the M second input terminals to be electrically connected to the second output terminal according to the digital conversion signal, and outputs the analog voltage signal Vout from the second output terminal. It should be noted that the M second input terminals are electrically connected to the M first output terminals in a one-to-one correspondence.

Fig. 3 is a circuit diagram illustrating an example of the digital-to-analog conversion circuit 100 of the embodiment shown in fig. 2.

For example, as shown in FIG. 3, in this example, the memristor string module 110 of the digital-to-analog conversion circuit 100 includes M memristors, M first output terminals O <1>, O <2> … … O < M >, and a mode switching module. M memristors R <1>, R <2> … … R < M > are sequentially connected in series, and two end points of a memristor string formed by the M memristors are respectively and electrically connected with a first voltage end and a second voltage end. For example, the first voltage terminal is configured to receive a first voltage V1, the first voltage V1 may be a reference voltage Vref; the second voltage terminal is configured to receive a second voltage V2, for example, the second voltage V2 may be configured as Ground (GND). The M first output ends O <1>, O <2> … … O < M > respectively correspond to the second voltage end O <1> and M-1 middle connection points O <2>, O <3> … … O < M > between adjacent memristors in the M memristors, so that voltage signals on the M memristors can be output to the multi-path selection module 130 in an operating state.

It should be noted that after the memristors are arranged in the M memristors, the resistances of at least one pair of adjacent memristors in the M memristors may not be equal, for example, M accumulated values generated by sequentially accumulating the resistances of the M memristors may have a nonlinear change, for example, the linear change may be as shown in fig. 1, but is not limited to the case shown in fig. 1; alternatively, the resistances of the M memristors may be equal, and at this time, the digital-to-analog conversion circuit 100 has the function of a linear digital-to-analog conversion circuit.

For example, the mode switching module includes a first control signal input terminal and M-1 first switches M1<1>, M1<2> … … M1< M-1 >. The mode switching module is configured to electrically disconnect or establish an electrical connection between any pair of adjacent memristors among the M memristors according to the first control signal Von 1. For example, the first control signal input is configured to receive a first control signal Von 1. For example, the ith first switch M1 connects the ith memristor R and the (i + 1) th memristor R , where i ═ 1,2, …, M-1; the control terminals of the M-1 first switches M1 are electrically connected with the first control signal input terminal to receive the first control signal Von1, and the first terminals and the second terminals of the M-1 first switches M1 are respectively connected with two adjacent memristors. Therefore, when the M-1 first switches M1 are turned on by receiving the first control signal Von1, the two memristors connected therewith will be electrically connected. When the M memristors are all electrically connected, a conductive path is established between the first voltage end and the second voltage end, and each memristor plays the role of a voltage dividing resistor, so that different voltage values are generated and can be output at M-1 intermediate connection points respectively. Conversely, when the M-1 first switches M1 are turned off by receiving the first control signal Von1, the electrical connection between the two memristors connected thereto will be broken.

It should be noted that the first switch M1 may be any suitable switching element, such as a metal-oxide semiconductor field effect transistor (MOSFET) or other three-terminal switching element, and the embodiments of the present disclosure are not limited thereto.

For example, as shown in fig. 3, the memristor setting block 120 of the digital-to-analog conversion circuit 100 includes M first input terminals, M second switches (M2<1>, M2<2> … … M2< M >), M-1 third switches (M3<1>, M3<2> … … M3< M-1>), a second control signal input terminal, and M third voltage terminals. The M first input terminals are configured to receive M operation voltages VP <1>, VP <2> … … VP < M >. The first end of the jth second switch M2< j > is electrically connected with the jth first input end to receive the jth operating voltage VP < j >; a second end of the jth second switch M2< j > is electrically connected with a first end of the jth memristor R < j >, and a control end of the M second switch M2 is electrically connected with the second control signal input end to receive the second control signal Von 2; wherein j is 1,2, …, M.

For example, a first terminal of an h-th third switch M3< h > is electrically connected to a second terminal of an h + 1-th memristor R < h +1>, a second terminal of an h-th third switch M3< h > is electrically connected to an h-th third voltage terminal, and a control terminal of an M-1 third switch M3 is electrically connected to a second control signal input terminal to receive the second control signal Von 2; wherein h is 1,2, …, M-1. The M third voltage terminals are electrically connected to each other and are connected to the same voltage as the second voltage terminal. For example, the M third voltages may be configured as Ground (GND).

Therefore, when the M second switches M2 and the M-1 third switches M3 receive the second control signal Von2 and are turned on, and M operation voltage signals VP <1>, VP <2> … … VP < M > are respectively input to the first ends of the M second switches M2, both ends of each memristor are respectively electrically connected to the corresponding operation voltage VP and the corresponding third voltage end, so that the M memristors can be respectively set according to the M operation voltages VP. Conversely, when the M second switches M2 and the M-1 third switches M3 are turned off upon receiving the second control signal Von2, the electrical connection of the respective memristors with the corresponding operating voltage VP and the corresponding third voltage terminal will be broken.

For example, by setting the first control signal Von1 and the second control signal Von2 to be on or off potentials, the mode switching module and the memristor setting module 120 may control the digital-to-analog conversion circuit 100 to enter a set mode or an operating mode, as shown in table 1.

TABLE 1 relationship of control signals to DAC patterns

Control signal	Set mode	Mode of operation
			Von1	Off potential	Conducting potential
Von2	Conducting potential	Off potential

It should be noted that the second switch M2 and the third switch M3 may be various suitable switching elements, such as MOSFETs or other three-terminal switching elements, and the embodiment of the disclosure is not limited thereto.

It should be noted that in other embodiments, the memristor string module 110 may also include only M-1 memristors, i.e., the uppermost memristor R < M > in fig. 3 and the corresponding second switch M2< M > and third switch M3< M-1> may be omitted.

For example, as shown in FIG. 3, the multiplexer module 130 of the DAC circuit 100 includes M second input terminals O <1>, O <2> … … O < M >, M switch sub-modules K <0>, K <1> … … K < M-1>, M digital signal input terminals, and a second output terminal (Vout). The m digital signal inputs d <0>, d <1> … … d < m-1> are configured to receive a digitally converted signal having m bits. The a-th switch submodule K < a > is electrically connected with an a-th digital signal input terminal d < a >, and the a-th digital signal input terminal d < a > is configured to receive an a-th digital conversion signal, wherein a is 0,1,2, …, m-1. The a-th switch submodule K < a > has 2^ (m-a) input ends and 2^ (m-a-1) output ends, and is configured to select 2^ (m-a-1) outputs from 2^ (m-a) pairs of inputs, and the step-by-step operation can finally realize the function of selecting one from 2^ m. Except the m-1 switch submodule K < m-1>, the output of the a switch submodule K < a > is respectively used as the input of the a +1 switch submodule.

For example, the a-th switch submodule includes 2^ (M-a) fourth switches M4. In each switch submodule K, every two fourth switches M4 form a switch group, and the fourth switches M4 included in any two switch groups are not repeated. For example, in the a-th switch submodule K < a >, the control terminals of the two fourth switches M4 in each switch group are electrically connected to the inverters connected to the a-th signal input terminal and the a-th signal input terminal, respectively, that is, the two fourth switches M4 in each switch group are controlled by a pair of signals with opposite logics, so that the on and off states of the two fourth switches M4 are opposite, and the function of selecting one from two is realized. The second terminals of the two fourth switches M4 in each switch group are connected and extracted as the reference voltage output terminal.

For example, in the a-th switch submodule K < a > except the 0-th switch submodule K <0>, the first terminal of the p-th fourth switch M4< a, p > is electrically connected to the p-th reference voltage output terminal in the a-1-th switch submodule K < a-1>, where p is 1,2, …,2^ (M-a). In the 0 th switch submodule, the first end of the pth fourth switch M4<0, p > is electrically connected to the pth second input end O , that is, the pth first output end O connected to the pth memristor R , so as to couple the multiplexing selection module 130 to the memristor string module 110. The (M-1) th switch submodule only comprises 2 fourth switches M4< M-2,1> and M4< M-2,2>, and the reference voltage output end is the second output end. The second output terminal is configured to output an analog voltage signal Vout.

It should be noted that, in the specific example shown in fig. 3, the naming rule of the fourth switch M4< x, y > is as follows: x represents the input digital conversion signal as the x-th bit; y indicates that the fourth switch M4 is the y-th fourth switch M4 in the switch submodule.

For example, in one specific example shown in fig. 3, taking a case where M is 2 (i.e., M is 4) as an example, when the input digital conversion signal is 01, when 01 is input, a first output terminal O <2> between R <1> and R <2> is selected as an output; when the input digital conversion signal is 10, the first output terminal O <3> between R <2> and R <3> is selected as an output.

It should be noted that the fourth switch M4 may be any suitable switching element, such as a MOSFET or other three-terminal switching element, and the embodiment of the disclosure is not limited thereto.

Fig. 4 is a schematic block diagram of an electronic device including a digital-to-analog conversion circuit according to at least one embodiment of the disclosure.

For example, as shown in fig. 4, the electronic device 200 includes a control module 210, an operating voltage providing module 220, and a digital-to-analog conversion circuit 230 as shown in fig. 2 and 3. The control module 210 is configured to provide a first control signal Von1 and a second control signal Von2 for switching the digital-to-analog conversion circuit 230 to a set state or an operating state, as shown in table 1 above, for example, the control module 210 may be implemented by a digital circuit or an analog circuit, which is not limited by the disclosure. The operating voltage providing module 220 is coupled to the M first input terminals and configured to provide M operating voltages VP <1>, VP <2> … … VP < M > for inputting appropriate pulse signals to the M memristors in the set state to set the M memristors to appropriate resistance values. For example, the operation voltage providing module 220 may be implemented by a digital circuit or an analog circuit, such as a CPU, a Programmable Logic Controller (PLC), and the like, which is not limited by the present disclosure. The digital-to-analog conversion circuit 230 is, for example, a digital-to-analog conversion circuit according to any embodiment of the present disclosure, and is therefore configured to convert an input m-bit digital conversion signal into an analog voltage signal Vout.

Fig. 5 is a flowchart of a set mode operation method of a digital-to-analog conversion circuit according to at least one embodiment of the disclosure. Fig. 6 is a flowchart of an operation method of an operation mode of a digital-to-analog conversion circuit according to at least one embodiment of the disclosure.

For example, as shown in fig. 5, before performing digital-to-analog conversion, if M memristors in the memristor string module 110 are not configured to appropriate resistance values, the digital-to-analog conversion circuit should first enter the set mode to perform resistance configuration, including the following steps S10-S30, for example.

Step S10: to prevent the influence of the multiplexing module 130, the m digital signal inputs d <0>, d <1> … … d < m-1> are all set to zero first.

Step S20: a first control signal Von1 and a second control signal Von2 are received, wherein the first control signal Von1 is an off potential to cause electrical disconnection between any pair of adjacent memristors among the M memristors, and the second control signal Von2 is an on potential to cause the memristor string module 110 to enter a set mode.

Step S30: m operating voltages VP <1>, VP <2> … … VP < M > are received at M first input ends, and setting operation is carried out on the M memristors according to the M operating voltages.

Through the above operation, for example, the resistances of the M memristors R <1>, R <2> … … R < M > may be set to match the resistance of the nonlinear signal in FIG. 1, for example, the resistance of R <1> corresponds to the difference of (dot1-dot0), the resistance of R <2> corresponds to the difference of (dot2-dot1), and so on, thereby achieving the nonlinear conversion capability of the digital-to-analog conversion circuit.

For example, as shown in fig. 6, after the M memristors are configured to appropriate resistance values, the digital-to-analog conversion circuit needs to be set to enter an operating mode, which includes the following steps S40 to S50:

step S40: the first control signal Von1 and the second control signal Von2 are received, wherein the second control signal Von2 is an off potential to cause the memristor string module 110 to exit the set mode, the first control signal Von1 is an on potential to cause an electrical connection to be established between any pair of adjacent memristors among the M memristors, and M reference divided voltages are generated on the M memristors.

Step S50: and receiving the M-bit digital conversion signal, and inputting the M-bit digital conversion signal to the control terminal of the multiplexer module 130 corresponding to the fourth switch M4, wherein the multiplexer module 130 selects a corresponding one of the M reference divided voltages as the finally output analog voltage signal Vout to be output from the second output terminal according to the M-bit digital conversion signal.

FIG. 7 is a flowchart of one example of a memristor resistance set operation method in step S30 of the method shown in FIG. 5.

For example, as shown in FIG. 7, for the case where memristors cannot achieve absolutely continuously adjustable, in at least one embodiment of the present disclosure, the adjustable precision of each memristor may be unified as n bits (bit), i.e., the resistance value of each memristor is first expressed as 2^ n resistance steps, where n is a positive integer. Then, the following operations are performed to obtain an array R "[ M ] of M target resistances for the M memristors: sampling a nonlinear signal curve to obtain M +1 gear values; carrying out forward difference on the M +1 gear values, calculating M relative values, respectively corresponding to the resistance values of the M memristors, and recording as an array R [ M ]; finding the maximum value Rmax in the array R [ M ]; calculating the mapping proportion k to be 2^ n/Rmax so that the maximum value Rmax is mapped to the 2^ n gear in the 2^ n resistance gears; multiplying each numerical value in the array R [ M ] by a mapping proportion k to obtain a mapped array R' [ M ]; and performing nearest neighbor rounding on each numerical value in the array R ' [ M ] to obtain an array R ' [ M ] after the nearest neighbor rounding, so that the g-th numerical value in the array R ' [ M ] is mapped to the g-th 2^ n resistance gears in the M memristors, wherein g is 1,2, … and M.

For example, after obtaining an array R '[ M ] of M target resistance values of M memristors, inputting the array R' [ M ] to a pulse signal generator; receiving M operating voltages VP <1>, VP <2> … … VP < M > generated by the pulse signal generator according to the array R' [ M ]; m operating voltages are input to M first input terminals to set resistance values of M memristors R <1>, R <2> … … R < M >, respectively.

For example, as shown in fig. 8, the digital-to-analog conversion circuitry includes a memristor resistance generation program, a pulse signal generator, a nonlinear programmable DAC, a digital signal, and an analog signal.

For example, the memristor resistance generation procedure may be the example memristor resistance setting operation method shown in fig. 7, the pulse signal generator may be the pulse signal generator described in fig. 7, the nonlinear programmable DAC may be the digital-to-analog conversion circuit according to any embodiment of the present disclosure, the digital signal may be a digital conversion signal with m bits according to any embodiment of the present disclosure, and the analog signal may be the analog voltage signal Vout shown in fig. 2 and 3.

For example, the memristor resistance generation program generates an array R '[ M ] of M target resistances corresponding to M memristors according to a nonlinear signal such as shown in FIG. 1, and then inputs the array R' [ M ] to the pulse signal generator. The pulse signal generator generates M operation voltages according to the array R' [ M ], and then inputs the M operation voltages into the nonlinear programmable DAC. The nonlinear programmable DAC sets resistance values of the M memristors according to the M operating voltages respectively. And after the resistance value configuration is completed, the nonlinear programmable DAC enters a working mode. And inputting the digital signal into the nonlinear programmable DAC to obtain an output analog signal.

For the present disclosure, there are the following points to be explained:

(1) in the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to general designs.

(2) Features of the disclosure in the same embodiment and in different embodiments may be combined with each other without conflict.

The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and shall be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A digital-to-analog conversion circuit comprising:

a first voltage terminal configured to receive a first voltage;

a second voltage terminal configured to receive a second voltage;

a memristor string module, comprising:

the M memristors are sequentially connected in series, two end points of a memristor string formed by the M memristors are respectively and electrically connected with the first voltage end and the second voltage end,

m first output terminals, wherein the M first output terminals respectively correspond to the second voltage terminal and M-1 intermediate connection points between adjacent ones of the M memristors, an

A mode switching module comprising a first control signal input configured to receive a first control signal, the mode switching module configured to cause an electrical connection to be broken or established between any pair of adjacent memristors among the M memristors according to the first control signal;

a memristor setting module including M first input terminals configured to receive M operating voltages, a second control signal input terminal configured to receive a second control signal, and M third voltage terminals, the memristor setting module being coupled with the memristor string module and configured to couple the M memristors between the M first input terminals and the M third voltage terminals, respectively, according to the second control signal; and

a multiplexing module, including M second input terminals, M digital signal input terminals, and second output terminals, wherein the M second input terminals are electrically connected to the M first output terminals in a one-to-one correspondence, the M digital signal input terminals are configured to receive a digital conversion signal having M bits, the second output terminals are configured to output an analog voltage signal, and the multiplexing module is coupled to the memristor string module and configured to correspondingly select one of the M second input terminals to be electrically connected to the second output terminal according to the digital conversion signal;

wherein M is 2M, and M is an integer greater than 1.

2. The digital-to-analog conversion circuit of claim 1, wherein the mode switching module further comprises M-1 first switches M1,

an ith first switch M1 of the M-1 first switches M1 connects an ith memristor of the M memristors and an i +1 th memristor, and a control terminal of the M-1 first switch M1 is electrically connected with the first control signal input terminal to receive the first control signal, wherein i is 1,2, …, M-1.

3. The digital-to-analog conversion circuit of claim 1, wherein the memristor setting block includes M second switches M2 and M-1 third switches M3,

a first terminal of a jth second switch M2 of the M second switches M2 is electrically connected to a jth one of the M first input terminals, a second terminal of the jth second switch M2 is electrically connected to a first terminal of a jth one of the M memristors, a control terminal of the jth second switch M2 is electrically connected to the second control signal input terminal to receive the second control signal, wherein j is 1,2, …, M;

in the M-1 third switches M3, a first end of an h-th third switch M3 is electrically connected to a second end of an h + 1-th of the M memristors, a second end of the h-th third switch M3 is electrically connected to an h-th of the M third voltage ends, and a control end of the h-th third switch M3 is electrically connected to the second control signal input end to receive the second control signal, wherein h is 1,2, …, M-1.

4. The digital-to-analog conversion circuit of claim 3, wherein the M third voltage terminals are electrically connected to each other.

5. The digital to analog conversion circuit of claim 1, wherein the multiplexing module includes m switching sub-modules,

an a-th one of the m switch submodules is electrically connected to an a-th one of the m digital signal inputs, the a-th one of the m digital signal inputs configured to receive an a-th bit of the digitally converted signal, wherein a is 0,1,2, …, m-1;

among the m switch sub-modules, the a-th switch sub-module has 2^ (m-a) inputs and 2^ (m-a-1) outputs and is configured to select 2^ (m-a-1) outputs from the 2^ (m-a) pairs of inputs;

except for the (m-1) th switch submodule, the output of the (a) th switch submodule is respectively used as the input of the (a + 1) th switch submodule.

6. The digital-to-analog conversion circuit of claim 1, wherein at least one pair of adjacent memristors of the M memristors has unequal resistances.

7. The digital-to-analog conversion circuit of claim 6, wherein the M accumulated values generated by sequentially accumulating the resistances of the M memristors vary non-linearly.

8. The digital to analog conversion circuit of claim 1, wherein the M third voltage terminals are connected to the same voltage as the second voltage terminal.

9. An electronic device comprising a digital to analog conversion circuit as claimed in any one of claims 1 to 8.

10. The electronic device of claim 9, further comprising:

a control module configured to provide the first control signal and the second control signal; and

an operating voltage providing module coupled to the M first inputs and configured to provide the M operating voltages.

11. A method of operating a digital to analogue conversion circuit as claimed in any one of claims 1 to 8, comprising:

setting all the m digital signal input ends of the digital conversion signal of the multi-path selection module to be zero;

receiving the first control signal and the second control signal, wherein the first control signal is an off potential to cause an electrical connection to be broken between any pair of adjacent memristors in the M memristors, and the second control signal is an on potential to cause the memristor string module to enter a set mode;

receiving the M operating voltages at the M first input ends, and respectively carrying out setting operation on the M memristors according to the M operating voltages.

12. The operating method of claim 11, wherein the set operation comprises:

obtaining an array R '[ M ] of M target resistance values of the M memristors, and inputting the array R' [ M ] to a pulse signal generator;

receiving the M operating voltages generated by the pulse signal generator according to an array R' [ M ];

inputting the M operating voltages to the M first input terminals to set resistance values of the M memristors, respectively.

13. The method of operation of claim 12, wherein obtaining an array R "[ M ] of M target resistances for the M memristors comprises:

representing a resistance value of each of the M memristors as 2^ n resistance steps, where n is a positive integer;

sampling a nonlinear signal curve to obtain M +1 gear values;

carrying out forward difference on the M +1 gear values, calculating M relative values, respectively corresponding to the resistance values of the M memristors, and recording as an array R [ M ];

finding the maximum value Rmax in the array R [ M ];

calculating a mapping proportion k ^ 2^ n/Rmax so that the maximum value Rmax is mapped to a 2^ n gear in the 2^ n resistance gears;

multiplying each numerical value in the array R [ M ] by the mapping proportion k to obtain a mapped array R' [ M ];

and performing nearest neighbor rounding on each numerical value in the array R ' [ M ] to obtain an array R ' [ M ] after the nearest neighbor rounding, so that the g-th numerical value in the array R ' [ M ] is mapped to the 2^ n resistance gears of the g-th memristor in the M memristors, wherein g is 1,2, … and M.

14. A method of operating a digital to analogue conversion circuit as claimed in any one of claims 1 to 8, comprising:

receiving the first control signal and the second control signal, wherein the second control signal is an off potential to cause the memristor string module to exit a set mode, the first control signal is an on potential to cause an electrical connection to be established between any pair of adjacent memristors among the M memristors, and M reference divided voltages are generated on the M memristors;

and receiving the digital conversion signal, and inputting the digital conversion signal into the multi-path selection module, wherein the multi-path selection module selects a corresponding reference divided voltage from the M reference divided voltages according to the digital conversion signal, and outputs the selected reference divided voltage as the analog voltage signal from the second output terminal.