CN114665881B - Resistance type DAC circuit structure and digital-to-analog converter - Google Patents
Resistance type DAC circuit structure and digital-to-analog converter Download PDFInfo
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- CN114665881B CN114665881B CN202210571913.3A CN202210571913A CN114665881B CN 114665881 B CN114665881 B CN 114665881B CN 202210571913 A CN202210571913 A CN 202210571913A CN 114665881 B CN114665881 B CN 114665881B
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Abstract
The invention provides a resistance type DAC circuit structure and a digital-to-analog converter, comprising: integer multiple weight resistance module and fraction multiple weight resistance module, wherein: selecting at least one of an integral multiple weight resistance module or a fractional multiple weight resistance module based on the ratio of the weighted analog signal output by the resistance type DAC circuit structure to the unit resistance so as to output a corresponding weighted analog signal; the input digital signal is input into the selected weight resistance module, the output signals of the selected weight resistance module are synthesized through switch control so as to meet the requirement of the resolution ratio of the circuit, and the smallest weight value is not determined by integral multiple unit resistance any more by setting the fractional weight resistance module, so that the design is convenient, and the circuit is effectively ensured to obtain the optimal differential nonlinearity and integral nonlinearity; compared with the DAC with the Kelvin framework, the number of the unit resistors and the number of the switches do not change exponentially with the digit of the DAC any more, the number of the unit resistors and the number of the switches are saved to the maximum extent, the physical size is reduced, and the cost is saved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a resistance type DAC circuit structure and a digital-to-analog converter.
Background
Dac (digital to Analog converter) is a device that converts digital signals into Analog signals, and is widely used in digital circuits. Resistive DACs have limitations related to achieving high resolution and maintaining their linearity. According to the Kelvin structure, if a DAC with N bits is set, the number of the DAC is required to be 2 N An equivalent series resistance and 2 N A switch. It is clear that a kelvin configuration DAC has a large number of resistors, and it is impractical to adjust each resistor in the DAC to obtain the optimum Differential Nonlinearity (DNL) and Integral Nonlinearity (INL), partly because the number of resistors is too large, partly because the resistors are too small to be calibrated, and partly because it is also costly to set the DAC to the kelvin configuration. Due to the physical size reality, resistive DACs typically can achieve very limited resolution, typically 8 to 10 bits.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a resistor-type DAC circuit structure and a digital-to-analog converter, which are used to solve the problem that the resistor-type DAC in the prior art has exponentially increased resistors and switches with increased number of bits, thereby increasing physical size and incurring large cost, which makes it difficult to obtain optimal Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for the circuit.
To achieve the above and other related objects, the present invention provides a resistive DAC circuit structure, including at least: integer multiple weight resistance module and fraction multiple weight resistance module, wherein:
selecting at least one of the integer-weight resistor module or the fractional-weight resistor module based on a ratio of a weighted analog signal output by the resistor type DAC circuit structure to a unit resistor to output a corresponding weighted analog signal; and inputting the input digital signal into the selected weight resistance module, and synthesizing the output signal of the selected weight resistance module through switch control so as to meet the resolution requirement of the circuit.
Optionally, the integer-weight resistor module includes: m +1 integer-weight resistor networks and M +1 switches, wherein each integer-weight resistor network is respectively connected with one switch in parallel, and M is a natural number more than or equal to 0.
Optionally, the (i + 1) th integer-weight resistor network in the integer-weight resistor module comprises 2 connected in series i And the number of the unit resistors in each integer-weight resistor network increases from low to high by taking 2 as an equal coefficient, wherein i is a natural number which is greater than or equal to 0 and less than or equal to M.
Optionally, the fractional weight resistance module includes: 1/2 times of weight resistance network, 1/4 times of weight resistance network and K sub-fractional times of weight resistance network, wherein, in K sub-fractional times of weight resistance network, the jth sub-fractional times of weight resistance network is used for realizing the ratio of 1/2 to the unit resistance j+2 Multiple weighted analog signal output, K is a natural number greater than or equal to 1, j is greater than or equal to 1 and less than or equal to 1A natural number equal to K.
Optionally, the 1/2 times weighted resistance network comprises: 1/2 times weight resistance unit and 1 switch, wherein, the 1/2 times weight resistance unit is connected with the switch in parallel.
Optionally, the 1/2 times weight resistance unit comprises 2 unit resistances connected in parallel.
Optionally, the 1/4 times weighted resistor network includes: 1/4 times weight resistance unit and 1 unit resistance, wherein, the 1/4 times weight resistance unit is connected with the unit resistance in parallel.
Optionally, the 1/4 times weight resistance unit includes: 3 unit resistors and 1 switch, wherein the switch is connected in series with the 3 unit resistors.
Optionally, the jth sub-fractional-weight resistor network of the K sub-fractional-weight resistor networks includes 1 1/2 j+2 The weight-multiplying resistor sub-network is connected with 2 unit resistors, wherein 2 unit resistors are connected in parallel and are connected with the 1/2 j+2 The weighting resistor sub-networks are connected in parallel; and realizing the output of the fraction-times-weighted analog signal with 1/2 as an equal ratio coefficient based on the increment of the number of unit resistors in each sub-fraction-times-weighted resistor network.
Optionally, said 1/2 j+2 The weighted resistor sub-network includes: 1/2 j+2 A weight factor and 2 unit resistances, wherein 2 unit resistances are connected in parallel and are connected with the 1/2 j+2 A weighted resistance factor in series, wherein the 1/2 j+2 The weight factor includes: 1 switch and 2 j 1 unit resistance, of which 2 j -1 unit resistor in series with the switch.
The invention provides a digital-to-analog converter, which at least comprises the resistance type DAC circuit structure.
As described above, the resistive DAC circuit structure and the digital-to-analog converter according to the present invention have the following advantages:
1) the invention ensures that the minimum weight value is not determined by Integral multiple unit resistance any more by setting the fractional multiple resistance module, is convenient to design, and effectively ensures that the circuit can easily obtain the optimal Differential Nonlinearity (DNL) and Integral Nonlinearity (INL).
2) Compared with the DAC with the Kelvin framework, the resistance type DAC circuit structure has the advantages that the number of the unit resistors and the number of the switches do not change exponentially with the digit of the DAC any more, the number of the unit resistors and the number of the switches are saved to the maximum extent, the physical size is reduced, and the cost is saved.
Drawings
Fig. 1 is a schematic diagram illustrating an integer-weight resistor module according to the present invention.
Fig. 2 is a schematic diagram of the fractional weight resistance module according to the present invention.
Description of the element reference numerals
1-integer times weight resistance module; 11-integer times weight resistance network; 2-fractional weight-multiplying resistance module; 21-1/2 times weight resistance network; 211-1/2 times weight resistance unit; 22-1/4 times weight resistance network; 221-1/4 times weight resistance unit; 23-a fractional multiple weight resistor network; 231-1/2 j+2 A weighting resistor subnetwork; 232-1/2 j+2 A weighted resistance factor.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 and fig. 2, the present embodiment provides a resistive DAC circuit structure, which includes: integer multiple weight resistance module 1 and fraction multiple weight resistance module 2, wherein:
selecting at least one of the integral multiple weight resistor module 1 or the fractional multiple weight resistor module 2 based on the ratio of the weighted analog signal output by the resistor type DAC circuit structure to the unit resistor Ru so as to output a corresponding weighted analog signal; and inputting the input digital signal into the selected weight resistance module, and synthesizing the output signal of the selected weight resistance module through switch control so as to meet the resolution requirement of the circuit.
Specifically, as shown in fig. 1, the integer-weight resistor module 1 includes: m +1 integer-weight resistor networks 11 and M +1 switches, wherein each integer-weight resistor network 11 is respectively connected with one switch in parallel, and M is a natural number more than or equal to 0. More specifically, the (i + 1) th integer-weight resistor network 11 in the integer-weight resistor module 1 comprises 2 connected in series i The number of the unit resistors in each of the multiple-weight resistor networks 11 increases from low to high by an equal ratio coefficient of 2, where i is a natural number greater than or equal to 0 and less than or equal to M, as shown in fig. 1, the maximum value of i is M, and the value of M should be set according to the actual requirements of the circuit. It should be noted that, if the ratio of the output weighted analog signal to the unit resistance Ru is 3, a 1-time weighting resistor network and a 2-time weighting resistor network may be selected, where 1 unit resistance Ru (i.e. 2 unit resistances Ru) is in the 1-time weighting resistor network 0 Single unit resistor Ru), 2 unit resistors Ru (i.e., 2) in a 2-times weight resistor network 1 Unit resistors Ru), and output signals of the 1-time weight resistor network and the 2-time weight resistor network are added to realize synthesis; alternatively, a 1-times weight resistor network and a 4-times weight resistor network can be selected, wherein the 4-times weight resistor network has 4 unit resistors Ru (i.e., 2 2 The unit resistors Ru) are combined by subtracting the output signals of the 4-time weight resistor network and the 1-time weight resistor network, and by analogy, the value of M is selected according to the ratio of the weighted analog signal to the unit resistors Ru, and the output signals of the selected integer multiple weight resistor networks 11 are combined by adding or subtracting according to actual needs. It should be further noted that the precision value of the unit resistance Ru can be 10%, 5%, 0.5%, 0.01%, etc.,the unit resistor Ru can be set as long as the precision value that the process can reach is a value, because the weighted analog signal obtained from the output of the resistor DAC circuit structure is the relative value of the unit resistor Ru, the absolute precision of the unit resistor Ru can be avoided, in the practical application scene, the relative precision of the unit resistor Ru is selected and designed according to the practical requirements of the circuit or the system, the general size is large, the resistor matching is better, the relative precision is higher, but a larger chip area is consumed, as long as the matching requirement of the corresponding DAC can be met, the unit resistor Ru and the corresponding precision of any size are applicable, and the embodiment is not limited.
Specifically, as shown in fig. 2, the fractional weight resistance module 2 includes: the fractional weight resistance module 2 includes: 1/2 times the weight of the resistor network 21, 1/4 times the weight of the resistor network 22 and K sub-fractional times the weight of the resistor network 23, wherein, in K sub-fractional times the weight of the resistor network 23, the jth sub-fractional times the weight of the resistor network used to achieve and unit resistance ratio of 1/2 j+2 And multiplying the weighted analog signal output, wherein K is a natural number which is more than or equal to 1, and j is a natural number which is more than or equal to 1 and less than or equal to K.
More specifically, the 1/2 times weighted resistor network 21 includes: 1/2 times weight resistance unit 211 and 1 switch, wherein the 1/2 times weight resistance unit 211 is connected in parallel with the switch. Further, the 1/2 times weight resistor unit 211 includes 2 unit resistors Ru connected in parallel. It should be noted that, although four groups of 2 × unit resistors Ru can be used for parallel connection according to the parallel relation of the resistors to realize weighted analog signal output with a ratio of 1/2 with the unit resistor Ru, compared with the present embodiment, the number of the unit resistors Ru is 8, and there are four parallel branches, which increases the circuit area and complexity.
More specifically, the 1/4 weighted resistor network 22 includes: 1/4 times the weight of the resistor unit 221 and 1 unit resistor Ru, wherein the 1/4 times the weight of the resistor unit 221 and the unit resistor Ru are connected in parallel. Further, the 1/4 times weighting resistance unit 221 includes: 3 unit resistors Ru and 1 switch, wherein the switch is connected in series with the 3 unit resistors Ru. It should be noted that, when the switch of the 1/4-time weighted resistor network 22 is closed, the ratio of the output weighted analog signal to the unit resistor Ru is 3/4, as shown in fig. 1, the 2 nd integer-time weighted resistor network 11 (where, the 2 nd integer-time weighted resistor network 11 includes 1 unit resistor Ru) and the 1/4-time weighted resistor network 22 (where, the switch of the 1/4-time weighted resistor unit 221 in the 1/4-time weighted resistor network 22 is closed) are selected, and the output signals of the 2 nd integer-time weighted resistor network 11 and the 1/4-time weighted resistor network 22 are subtracted to obtain the ratio of the weighted analog signal to the unit resistor Ru is 1/4; according to the parallel connection relationship of the resistors, four groups of 1 × unit resistors Ru can be used for parallel connection, but compared with the present embodiment, there are four parallel branches, which increases the circuit area and complexity.
More specifically, the jth sub-fractional-weight resistor network 23 of the K sub-fractional-weight resistor networks includes 1 1/2 j+2 Weight multiplying resistor sub-network 231 (where j equals K as shown in fig. 2) is connected in parallel with 2 unit resistors, 2 of which are connected in parallel with 1/2 j+2 Weight resistor sub-network 231 is connected in parallel; fractional-multiple-weighted analog signal output with 1/2 as an equal ratio coefficient is realized based on the increment of the number of unit resistors in each sub-fractional-multiple-weighted resistor network 23, wherein, as shown in fig. 2, the maximum value of j is K, and the value of K is set according to the actual requirement of the circuit. Further, the 1/2 j+2 Weighted resistor sub-network 231 includes: 1/2 j+2 A weight-multiplying resistance factor 232 and 2 unit resistances Ru, wherein the 2 unit resistances Ru are connected in parallel and are connected with the 1/2 j+2 The weighting resistance factors 232 are connected in series; the 1/2 j+2 The weight resistance factor 232 includes: 1 switch and 2 j 1 unit resistance Ru, 2 j 1 unit resistor Ru connected in series and connected with the switch, wherein, as shown in FIG. 2, the maximum value of j is K, and the value of K is set according to the actual requirement of the circuit.
The present embodiment further provides a digital-to-analog converter, where the digital-to-analog converter at least includes the resistor DAC circuit structure.
Specifically, as an example, the module attributes of the digital-to-analog converter performing the integer multiple or fractional multiple operation (where the module is an abbreviation of a weight resistance module) are shown in the table:
| module | i | j | When the switch is closed, the mold Block resistance value | When the switch is off, the mould Block resistance value | Modular resistor on switch closure Difference from disconnection | Unit resistance in module Number of |
| 8 times module | 3 | 0 | 0 | 8Ru | 8Ru | 8 |
| 4 times module | 2 | 0 | 0 | 4Ru | 4Ru | 4 |
| 2 times module | 1 | 0 | 0 | 2Ru | 2Ru | 2 |
| 1 time module | 0 | 0 | 0 | 1Ru | 1Ru | 1 |
| 1/2 times module | 0 | / | 0 | 1/2Ru | 1/2Ru | 2 |
| 1/4 times module | 0 | / | 3/4Ru | 1Ru | 1/4Ru | 4 |
| 1/8 times module | 0 | 1 | 3/8Ru | 1/2Ru | 1/8Ru | 5 |
| 1/16 times module | 0 | 2 | 7/16Ru | 1/2Ru | 1/16Ru | 7 |
| 1/32 times module | 0 | 3 | 15/32Ru | 1/2Ru | 1/ |
11 |
| 1/64 times module | 0 | 4 | 31/64Ru | 1/2Ru | 1/64Ru | 19 |
For a digital-to-analog converter realizing 8bit resolution, the selectable resistive DAC circuit structure includes: 4 times module, 2 times module, 1 times module, 1/2 times module, 1/4 times module, 1/8 times module, 1/16 times module and 1/32 times module, wherein 4 times module is 2 times module 2 Doubling module, 1/32 doubling module 1/2 5 The number of the total required unit resistors Ru is 36, and the number of the switches is 8; while a kelvin-structured digital-to-analog converter requires 256 (i.e., 2) 8 ) Compared with the DAC circuit with Kelvin structure, the digital-to-analog converter of the embodiment only uses a larger number of unit resistors Ru and 256 switchesThe circuit area is greatly reduced due to less unit resistors Ru and switches, the cost can be saved to the maximum extent, and meanwhile, the fraction-multiple module enables the minimum weight value to be no longer determined by integral multiple of the unit resistors Ru, so that the design is convenient; meanwhile, the weight value obtained by the fractional multiple module enables fine tuning of the circuit, and effectively ensures that the circuit can easily obtain the optimal Differential Nonlinearity (DNL) and Integral Nonlinearity (INL).
In summary, the resistive DAC circuit structure and the digital-to-analog converter according to the present invention include: integer multiple weight resistance module and fraction multiple weight resistance module, wherein: selecting at least one of the integer-weight resistor module or the fractional-weight resistor module based on a ratio of a weighted analog signal output by the resistor type DAC circuit structure to a unit resistor to output a corresponding weighted analog signal; the input digital signals are input into the selected weight resistance module, the output signals of the selected weight resistance module are synthesized through switch control, so that the resolution requirement of the circuit is met, the smallest weight value is not determined by Integral multiple unit resistance any more by setting the fractional weight resistance module, the design is convenient, and the circuit is effectively ensured to be easy to obtain the optimal Differential Nonlinearity (DNL) and Integral Nonlinearity (INL); compared with the DAC with the Kelvin framework, the number of the unit resistors and the number of the switches do not change exponentially with the digit of the DAC any more, the number of the unit resistors and the number of the switches are saved to the maximum extent, the physical size is reduced, and the cost is saved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A resistive DAC circuit structure, comprising: integer multiple weight resistance module and fraction multiple weight resistance module, wherein:
selecting at least one of the integer-weight resistor module or the fractional-weight resistor module based on a ratio of a weighted analog signal output by the resistor type DAC circuit structure to a unit resistor to output a corresponding weighted analog signal; inputting the input digital signal into the selected weight resistance module, and synthesizing the output signal of the selected weight resistance module through switch control so as to meet the resolution requirement of the circuit;
wherein, the integer multiple weight resistance module includes: m +1 integer-weight resistor networks and M +1 switches, wherein each integer-weight resistor network is respectively connected with one switch in parallel, and M is a natural number more than or equal to 0;
wherein the fractional weight resistance module comprises: 1/2 times weight resistance network, 1/4 times weight resistance network and K sub-fraction times weight resistance network, wherein, in the K sub-fraction times weight resistance network, the jth sub-fraction times weight resistance network is used for realizing that the ratio of the jth sub-fraction times weight resistance network to the unit resistance is 1/2 j+2 Multiple weighted analog signal output, wherein K is a natural number greater than or equal to 1, j is a natural number greater than or equal to 1 and less than or equal to K, and the jth sub-fractional weight-multiplying resistor network in the K sub-fractional weight-multiplying resistor networks comprises 1 1/2 j+2 A weight-multiplying resistor sub-network connected with 2 unit resistors, wherein 2 unit resistors are connected in parallel with the 1/2 j+2 The weighting resistor sub-networks are connected in parallel; and realizing the output of the fraction-times-weighted analog signal with 1/2 as an equal ratio coefficient based on the increment of the number of unit resistors in each sub-fraction-times-weighted resistor network.
2. The resistive DAC circuit structure of claim 1, wherein: the (i + 1) th integer weight resistance network in the integer weight resistance module comprises 2 in series connection i The number of the unit resistors in each integer-weight resistor network increases from low to high by an equal ratio coefficient of 2, wherein i is greater than or equal to 0 and less than or equal toA natural number of M.
3. The resistive DAC circuit structure of claim 1, wherein: the 1/2 times weight resistance network comprises: 1/2 times weight resistance unit and 1 switch, wherein, the 1/2 times weight resistance unit is connected with the switch in parallel.
4. The resistive DAC circuit structure of claim 3, wherein: the 1/2 times weight resistance unit comprises 2 unit resistances connected in parallel.
5. The resistive DAC circuit structure of claim 1, wherein: the 1/4 times weight resistance network comprises: 1/4 times weight resistance unit and 1 unit resistance, wherein, the 1/4 times weight resistance unit is connected with the unit resistance in parallel.
6. The resistive DAC circuit structure of claim 5, wherein: the 1/4 times weight resistance unit comprises: 3 unit resistors and 1 switch, wherein the switch is connected in series with the 3 unit resistors.
7. The resistive DAC circuit structure of claim 1, wherein: the 1/2 j+2 The weight multiplier resistor sub-network includes: 1/2 j+2 A weight factor and 2 unit resistances, wherein 2 unit resistances are connected in parallel and are connected with the 1/2 j+2 A weighted resistance factor in series, wherein the 1/2 j+2 The weight factor includes: 1 switch and 2 j 1 unit resistance, of which 2 j -1 unit resistor in series with the switch.
8. A digital-to-analog converter, characterized in that it comprises at least: a resistive DAC circuit structure according to any one of claims 1 to 7.
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| CN1166726A (en) * | 1997-01-17 | 1997-12-03 | 张葭 | New-type parallel A/D converter circuit |
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| CN101425805B (en) * | 2007-10-31 | 2010-11-10 | 展讯通信（上海）有限公司 | High resolution small area A/D conversion circuit |
| CN102420610A (en) * | 2010-09-27 | 2012-04-18 | 飞思卡尔半导体公司 | Method for testing digital-to-analog converter and analog-to-digital converter |
| US8860597B2 (en) * | 2011-07-06 | 2014-10-14 | Qualcomm Incorporated | Digital to-analog converter circuitry with weighted resistance elements |
| WO2018126427A1 (en) * | 2017-01-06 | 2018-07-12 | Texas Instruments Incorporated | Area efficient digital to analog and analog to digital converters |
| US10938401B1 (en) * | 2019-11-25 | 2021-03-02 | Nxp B.V. | Analog-to-digital converter, resistive digital-to-analog converter circuit, and method of operating an analog-to-digital converter |
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| CN1166726A (en) * | 1997-01-17 | 1997-12-03 | 张葭 | New-type parallel A/D converter circuit |
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