CN117037877A - Memory computing chip based on NOR Flash and control method thereof - Google Patents
Memory computing chip based on NOR Flash and control method thereof Download PDFInfo
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- G11C16/00—Erasable programmable read-only memories
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G11C16/00—Erasable programmable read-only memories
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Abstract
The invention discloses a memory computing chip based on NOR Flash and a control method thereof, wherein the chip comprises: the device comprises an input interface module, a NOR Flash Cap unit array module, a controller and an output interface module; the input interface module is used for receiving target data; the NOR Flash Cap unit array module comprises a plurality of NOR Flash units with adjustable threshold voltage and a plurality of equal-proportion capacitors; in a storage mode, the NOR Flash unit is used for storing target data; in a calculation mode, the NOR Flash unit and the equal-proportion capacitor are used for calculating according to target data; the calculation mode adopts a charge sharing principle to calculate; the controller is used for controlling the in-memory computing chip to switch between a storage mode and a computing mode; the output interface module is used for outputting data. The invention can improve the data migration efficiency, thereby improving the calculation performance and being widely applied to the field of flash memory chips.
Description
Technical Field
The invention relates to the field of Flash memory chips, in particular to an in-memory computing chip based on NOR Flash and a control method thereof.
Background
In a classical von neumann computing architecture, the memory and the processor are separate, with data transfer between them over a data bus. When executing the command, the processor reads the data from the memory, after processing, the updated data is written back to the memory, and the frequent data migration causes huge power consumption and time cost.
At present, the processing speed of a processor is continuously improved, but the access speed of a memory is limited, so that the computing performance is greatly influenced. In particular, with the rise of applications such as big data and artificial intelligence, the processing of massive data makes von neumann computing architecture bottlenecks more and more prominent. Therefore, although the prior art proposes a memory integrated circuit for performing memory computation based on current, the memory computation based on current may result in a limitation of computation speed, and the existing memory computation still has a problem of low computation performance.
Disclosure of Invention
In view of this, the present invention provides an in-memory computing chip based on NOR Flash and a control method thereof, so as to improve data migration efficiency and thus improve computing performance.
One aspect of the present invention provides an in-memory computing chip based on NOR Flash, comprising: the device comprises an input interface module, a NOR Flash Cap unit array module, a controller and an output interface module;
the input interface module is used for receiving target data;
the NOR Flash Cap unit array module comprises a plurality of NOR Flash units with adjustable threshold voltage and a plurality of equal-proportion capacitors;
in a storage mode, the NOR Flash unit is used for storing the target data;
In a calculation mode, the NOR Flash unit and the equal-proportion capacitor are used for calculating according to the target data; the calculation mode adopts a charge sharing principle to calculate;
the controller is used for controlling the in-memory computing chip to switch between the storage mode and the computing mode;
the output interface module is used for outputting data.
Optionally, the NOR Flash Cap unit array module is of a two-dimensional structure, and a plurality of NOR Flash units form a two-dimensional array structure in the NOR Flash Cap unit array module; each NOR Flash unit comprises a grid electrode, a drain electrode and a source electrode;
in the NOR Flash Cap unit array module, the grid electrodes of all NOR Flash units in each row are connected to the same word line, and a plurality of rows of NOR Flash units are correspondingly connected with a plurality of word lines; the drains of all NOR Flash units in each column are connected with the same bit line, the sources of all NOR Flash units in each column are connected with the same source line, the sources of all NOR Flash units in each column are also connected with the upper polar plate of one equal-proportion capacitor, and the lower polar plate of each equal-proportion capacitor is connected with the ground.
Optionally, the in-memory computing chip further comprises a plurality of equipartition switches and a grounding switch;
one end of each equipartition switch is connected with a corresponding public end, and the connection end of the source electrode of each NOR Flash unit and the upper polar plate of one equal-proportion capacitor is used as the public end;
the other ends of all the equipartition switches are commonly connected to one end of the grounding switch, and the other end of the grounding switch is connected with the ground;
the controller is used for generating an enabling signal and controlling an enabling switch of the storage mode and an enabling switch of the calculation mode according to the enabling signal so as to control the in-memory calculation chip to switch between the storage mode and the calculation mode.
Optionally, the in-memory computing chip further includes a rank decoder module and a programming circuit module; the output interface module comprises an analog processing module and an arithmetic post-processing module;
one end of the input interface module is connected with the first end of the row-column decoder module, the second end of the row-column decoder module is connected with the first end of the NOR Flash Cap cell array module, and the third end of the row-column decoder module is connected with the programming circuit module; one end of the analog processing module is connected with the second end of the NOR Flash Cap unit array module, and the other end of the analog processing module is connected with one end of the arithmetic post-processing module; the other end of the arithmetic post-processing module is connected with one end of the output interface module;
In the storage mode, the word line is used for receiving a row selection signal of the NOR Flash unit, the bit line is used as a voltage input end, and the source line is used as an analog current output end; the input interface module, the row-column decoder module and the programming circuit module jointly complete the erasing and reading operation of the NOR Flash Cap cell array module; the analog processing module is used for converting an analog voltage signal or a current signal output by the NOR Flash Cap unit array module into a digital signal; the arithmetic post-processing module is used for carrying out arithmetic operation according to the digital signal.
Optionally, the input interface module is an analog input signal module, and the output interface module includes an analog-to-digital conversion module, a digital processing circuit and an arithmetic post-processing module;
the first end of the controller is connected with the first end of the analog input signal module, and the second end of the controller is respectively connected with the first end of the analog-to-digital conversion module, the first end of the digital processing circuit and the first end of the arithmetic post-processing module; the second end of the analog input signal module is connected with the first end of the NOR Flash Cap unit array module, and the first end of the NOR Flash Cap unit array module is the drain electrode of the NOR Flash unit; the second end of the analog-to-digital conversion module is connected with the second end of the NOR Flash Cap cell array module, and the third end of the analog-to-digital conversion module is connected with the second end of the digital processing circuit; the third end of the digital processing circuit is connected with the second end of the arithmetic post-processing module;
The analog input signal module is used for receiving the target data; the analog-to-digital conversion module is used for converting an analog voltage signal or a current signal output by the NOR Flash Cap unit array module into a digital signal; the digital processing circuit is used for preprocessing the digital signal; the arithmetic post-processing module is used for carrying out arithmetic operation according to the preprocessed digital signals;
in the computing mode, the word line is used for receiving a column selection signal of the NOR Flash unit; the voltage signal on the bit line is used as an input excitation signal of multiply-accumulate operation, and the source line is in a disconnection state; the number of the equal-proportion capacitors is the same as the bit width of the digital weight in the multiplication and accumulation operation, and the equal-proportion capacitors are used for charging in the multiplication operation process based on charge average; when the NOR Flash Cap cell array module does not input an excitation signal, the grounding switch and all the equipartition switches are in a closed state so as to empty the charges of all the equal-ratio column capacitors.
Optionally, in the calculation mode, the equipartition switch is used for equipartition of charges generated during a multiply-accumulate operation based on charge equipartition on all the equal-ratio column capacitances;
In the calculation mode, the controller is further used for controlling the input voltage of the interface input module and each equipartition switch to adjust the bit width of the digital input signal in the multiply-accumulate operation; the controller is also used for controlling the opening and closing states of the equipartition switches in the multiplication and accumulation operation process so as to carry out convolution operations with different sizes.
Optionally, the arithmetic post-processing module includes at least one of a pooling circuit, a Sigmoid function circuit, a Relu function circuit, a Tanh function circuit, or a BNRelu circuit.
The invention also provides a control method of the memory computing chip based on the NOR Flash, which is applied to the controller in the memory computing chip based on the NOR Flash, and the method comprises the following steps:
determining a working mode of an in-memory computing chip, wherein the working mode comprises a storage mode and a computing mode;
when the working mode is the storage mode, performing data programming on a NOR Flash unit in a NOR Flash Cap unit array module and detecting whether the data programming is correct or not;
when the working mode is the calculation mode, controlling an input interface module, a row-column decoder module and a programming circuit module in the in-memory calculation chip to jointly finish the erasing and reading operation of the NOR Flash Cap cell array module;
And/or the number of the groups of groups,
when the working mode is the calculation mode, controlling the NOR Flash Cap unit array module to carry out multiply-accumulate operation; controlling the input voltage of the interface input module and each equipartition switch in the NOR Flash Cap unit array module to adjust the bit width of the digital input signal in the multiply-accumulate operation; and controlling the opening and closing states of the equipartition switches in the multiplication and accumulation operation process so as to carry out convolution operations with different sizes.
The invention also provides a storage device which comprises the memory computing chip based on the NOR Flash, wherein the memory computing chip is used for storing data.
The invention also provides an electronic device which is characterized by comprising a processor, an SRAM, a communication interface, a bus and an in-memory computing chip based on NOR Flash;
the communication interface is used for exchanging data with external equipment;
the processor, the SRAM, the communication interface and the in-memory computing chip are respectively connected with the bus.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention provides an in-memory computing chip based on NOR Flash, which comprises an input interface module, a NOR Flash Cap unit array module, a controller and an output interface module, wherein the NOR Flash Cap unit array module comprises a plurality of NOR Flash units with adjustable threshold voltage and a plurality of equal proportion capacitors, and in a storage mode, the NOR Flash units are used for storing target data; in the calculation mode, the NOR Flash unit and the equal-proportion capacitor are used for calculating according to target data (the target data can be analog voltage signals); the calculation mode adopts the charge sharing principle to calculate, and the calculation speed is faster and more efficient compared with the current-based calculation mode of the existing in-memory calculation unit based on the charge sharing principle.
In addition, the in-memory computing chip can perform computation and data storage, so that the integration of memory computation is realized, frequent data transmission between the memory and the processor is not needed, the power consumption and the time cost are reduced, the processing performance is improved, the work of the processor is shared, and the performance of the whole computing system structure is further improved; because the data is not required to be frequently transmitted, the invention does not need to limit the bandwidth; when no calculation task exists, the in-memory calculation chip can be used as a memory for storing data, multiplexing of electric elements is realized, the utilization efficiency of the elements is improved, and the hardware cost of an integrated circuit is saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory computing chip based on NOR Flash according to an embodiment of the present invention;
Fig. 2 is a diagram illustrating a structure of a NOR Flash Cap unit array module according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of switching between a storage mode and a computation mode according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a single multiplication computation point of a NOR Flash Cap cell array module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a memory chip in a memory mode according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure of an in-memory computing chip in a computing mode according to an embodiment of the present invention;
FIG. 7 is a circuit schematic diagram of a convolution operation of a NOR Flash Cap cell array module according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a circuit with adjustable digital weight bit width of a NOR Flash Cap cell array module according to an embodiment of the present invention;
FIG. 9 is a schematic circuit diagram of a convolution operation size switchable circuit of a NOR Flash Cap cell array module according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of an arithmetic post-processing module according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a configurable digital processing module according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of an electronic device using an in-memory computing chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart.
The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to be limiting of the invention.
Referring to fig. 1, an embodiment of the present invention provides an in-memory computing chip based on NOR Flash, including: the device comprises an input interface module, a NOR Flash Cap unit array module, a controller and an output interface module;
the input interface module is used for receiving target data;
the NOR Flash Cap unit array module comprises a plurality of NOR Flash units with adjustable threshold voltage and a plurality of equal-proportion capacitors;
in a storage mode, the NOR Flash unit is used for storing the target data;
in a calculation mode, the NOR Flash unit and the equal-proportion capacitor are used for calculating according to the target data; the calculation mode adopts a charge sharing principle to calculate;
the controller is used for controlling the in-memory computing chip to switch between the storage mode and the computing mode;
the output interface module is used for outputting data.
Specifically, the input interface module is connected to an external element, for example, to an external microprocessor, and is used for receiving data to be calculated (i.e. target data), and in an alternative embodiment, the data to be calculated is used as an excitation signal, which may be an analog voltage signal, and the threshold voltage of the NOR Flash units is adjustable, which is equivalent to storing one bit of a multi-bit digital weight data in each NOR Flash unit, and the output voltage of each NOR Flash unit is equal to the product of the excitation signal and the digital weight data, where the weight data is a digital signal with adjustable bit width.
Further, the NOR Flash Cap unit array module is of a two-dimensional structure, and a plurality of NOR Flash units form a two-dimensional array structure in the NOR Flash Cap unit array module; each NOR Flash unit comprises a grid electrode, a drain electrode and a source electrode;
in the NOR Flash Cap unit array module, the grid electrodes of all NOR Flash units in each row are connected to the same word line, and a plurality of rows of NOR Flash units are correspondingly connected with a plurality of word lines; the drains of all NOR Flash units in each column are connected with the same bit line, the sources of all NOR Flash units in each column are connected with the same source line, the sources of all NOR Flash units in each column are also connected with the upper polar plate of one equal-proportion capacitor, and the lower polar plate of each equal-proportion capacitor is connected with the ground.
In an alternative embodiment, referring to fig. 2, the NOR Flash Cap cell array module may include an NOR Flash cell array, which is a two-dimensional structure. The NOR Flash unit is a part of the NOR Flash Cap unit array module, which removes the equal proportion capacitance, and can be used for storing a NOR Flash tube of 0 or 1.
Referring to fig. 3, each NOR Flash cell may be simplified to a three terminal structure including a gate drain and a source. The plurality of NOR Flash units are connected with a Source Line (SL) in an array mode through a Word Line (WL) and a Bit Line (BL).
The NOR Flash Cap unit array module comprises a plurality of NOR Flash units, the plurality of NOR Flash units are arranged in an array, the grid electrodes of all NOR Flash units in each row are connected to the same word line WL, and a plurality of rows of NOR Flash units are correspondingly connected with a plurality of word lines, namely WL 1-WLN; the source electrodes and the drain electrodes of all the NOR Flash units in each column are distributed in a mirror image mode, the drain electrodes of the NOR Flash units in each column are connected with a bit line BL, the source electrodes of the NOR Flash units in each column are connected with a source line SL, and the NOR Flash units in a plurality of columns correspond to a plurality of bit lines BL 1-BLN and a plurality of source lines SL 1-SLN.
Further, the in-memory computing chip further comprises a plurality of equipartition switches and a grounding switch;
one end of each equipartition switch is connected with a corresponding public end, and the connection end of the source electrode of each NOR Flash unit and the upper polar plate of one equal-proportion capacitor is used as the public end;
the other ends of all the equipartition switches are commonly connected to one end of the grounding switch, and the other end of the grounding switch is connected with the ground;
the controller is used for generating an enabling signal and controlling an enabling switch of the storage mode and an enabling switch of the calculation mode according to the enabling signal so as to control the in-memory calculation chip to switch between the storage mode and the calculation mode.
Specifically, a plurality of equipartition switches and a ground switch can be regarded as the switch module, and a plurality of equal proportion electric capacity can be regarded as equal proportion column electric capacity module. Referring to fig. 4, switching between the in-memory computing chip storage mode and the computing mode can be implemented by a controller, and an enable signal of the controller controls an enable switch of the computing mode and an enable switch of the storage mode, controlling both modes.
Specifically, the enabling process of the computing mode includes: after the erasing of the storage mode is completed, the controller can immediately send out a control signal (a high-level signal with a certain pulse width) to enable a readout path of the storage mode to be disconnected, namely, a signal of the controller controls a MOS switch at the SA end to be disconnected, meanwhile, the controller can control a grounding switch and all equipartition switches connected with the NOR Flash unit to be simultaneously closed, and then the in-memory computing chip enters a computing mode.
Optionally, both the dividing switch and the grounding switch can be realized by NMOS tubes or transmission gates.
Next, the storage mode and the calculation mode will be described respectively.
First, each circuit module or element of the in-memory computing chip in the memory mode will be described.
Further, the in-memory computing chip further comprises a row-column decoder module and a programming circuit module; the output interface module comprises an analog processing module and an arithmetic post-processing module;
one end of the input interface module is connected with the first end of the row-column decoder module, the second end of the row-column decoder module is connected with the first end of the NOR Flash Cap cell array module, and the third end of the row-column decoder module is connected with the programming circuit module; one end of the analog processing module is connected with the second end of the NOR Flash Cap unit array module, and the other end of the analog processing module is connected with one end of the arithmetic post-processing module; the other end of the arithmetic post-processing module is connected with one end of the output interface module;
in the storage mode, the word line is used for receiving a row selection signal of the NOR Flash unit, the bit line is used as a voltage input end, and the source line is used as an analog current output end; the input interface module, the row-column decoder module and the programming circuit module jointly complete the erasing and reading operation of the NOR Flash Cap cell array module; the analog processing module is used for converting an analog voltage signal or a current signal output by the NOR Flash Cap unit array module into a digital signal; the arithmetic post-processing module is used for carrying out arithmetic operation according to the digital signal.
Referring to fig. 5, an embodiment of the present invention provides a schematic structural diagram of an in-memory computing chip in a memory mode.
Specifically, the row-column decoder module is used for carrying out row-column decoding on the NOR Flash cell array in the NOR Flash Cap cell array module; the programming circuit module is used for regulating and controlling the threshold voltage of the NOR Flash units, and specifically is connected with at least one of a source electrode, a grid electrode or a substrate of each NOR Flash unit.
The row-column decoder module is used for gating a required NOR Flash unit in a storage mode so as to apply an analog input signal or programming/erasing voltage to the NOR Flash unit.
As a further alternative embodiment, the programming circuit module may include: the voltage generation circuit is used for generating programming voltage or erasing voltage, and the voltage control circuit is used for loading the programming voltage to the source electrode of the selected NOR Flash unit or loading the erasing voltage to the grid electrode or the substrate of the selected NOR Flash unit so as to regulate and control the threshold voltage of the NOR Flash unit.
Specifically, the programming circuit module may apply a high voltage to the source of the NOR Flash cell according to threshold voltage requirement data of the NOR Flash cell using a hot electron injection effect to accelerate channel electrons to a high speed, thereby increasing the threshold voltage of the NOR Flash cell. And the programming circuit module can also utilize tunneling effect, apply high voltage to the grid electrode or the substrate of the NOR Flash unit according to the threshold voltage requirement data of the NOR Flash unit, and attract electrons from the NOR Flash unit so as to reduce the threshold voltage of the NOR Flash unit.
Still further, the in-memory computing chip of the present invention may further include: the input register module is connected between the input interface module and the NOR Flash Cap unit array module and used for registering data to be output by the input interface module, and the output register module is connected between the arithmetic post-processing module and the output end of the in-memory computing chip and used for registering data to be output by the arithmetic post-processing module.
In a storage mode, the word line is used for receiving a NOR Flash unit row selection signal; the bit line is used as a voltage input end; the source line serves as an analog current output.
Because each NOR Flash unit in the NOR Flash Cap unit array module is connected with an independent word line and a bit line, the NOR Flash unit array can be independently addressed, namely, the minimum read-write can be independently read-written, and the minimum erasing unit is a block (namely, a plurality of pages form a block, alternatively, a block can be simultaneously erased). Alternatively, the erasing process of the in-memory computing chip of the present invention may be the same as that of the related art.
Next, each circuit module or element of the in-memory computing chip in the computing mode will be described.
Further, the input interface module is an analog input signal module, and the output interface module comprises an analog-to-digital conversion module, a digital processing circuit and an arithmetic post-processing module;
the first end of the controller is connected with the first end of the analog input signal module, and the second end of the controller is respectively connected with the first end of the analog-to-digital conversion module, the first end of the digital processing circuit and the first end of the arithmetic post-processing module; the second end of the analog input signal module is connected with the first end of the NOR Flash Cap unit array module, and the first end of the NOR Flash Cap unit array module is the drain electrode of the NOR Flash unit; the second end of the analog-to-digital conversion module is connected with the second end of the NOR Flash Cap cell array module, and the third end of the analog-to-digital conversion module is connected with the second end of the digital processing circuit; the third end of the digital processing circuit is connected with the second end of the arithmetic post-processing module;
the analog input signal module is used for receiving the target data; the analog-to-digital conversion module is used for converting an analog voltage signal or a current signal output by the NOR Flash Cap unit array module into a digital signal; the digital processing circuit is used for preprocessing the digital signal; the arithmetic post-processing module is used for carrying out arithmetic operation according to the preprocessed digital signals;
In the computing mode, the word line is used for receiving a column selection signal of the NOR Flash unit; the voltage signal on the bit line is used as an input excitation signal of multiply-accumulate operation, and the source line is in a disconnection state; the number of the equal-proportion capacitors is the same as the bit width of the digital weight in the multiplication and accumulation operation, and the equal-proportion capacitors are used for charging in the multiplication operation process based on charge average; when the NOR Flash Cap cell array module does not input an excitation signal, the grounding switch and all the equipartition switches are in a closed state so as to empty the charges of all the equal-ratio column capacitors.
Furthermore, in the calculation mode, the average switch is used for equally dividing the charge generated during the multiply-accumulate operation based on charge average division on all the equal-ratio column capacitances; in the calculation mode, the controller is further used for controlling the input voltage of the interface input module and each equipartition switch to adjust the bit width of the digital input signal in the multiply-accumulate operation; the controller is also used for controlling the opening and closing states of the equipartition switches in the multiplication and accumulation operation process so as to carry out convolution operations with different sizes.
Referring to fig. 6, an embodiment of the present invention provides a schematic structural diagram of an in-memory computing chip in a computing mode.
Specifically, in the calculation mode, when the digital weight is N bits in a single multiplication, the capacitance on the calculation path corresponding to the NOR Flash unit from low to high is 2 j C、2 j-1 C...2 2 C、2 1 C、2 0 C, wherein C is the minimum unit capacitance that the memory circuit can achieve. Taking the 3bit digital weight of fig. 4 as an example, the capacitance on the calculation paths corresponding to the 3 NOR Flash units from high to low weights is 4C, 2C and C, respectively.
In the computing mode, target data input from the interface input module is an analog voltage signal, wherein the target data is used as an input excitation signal and is added to the drain electrode of the NOR Flash unit by BL, and multiplication operation is carried out on multi-bit digital weights, wherein the NOR Flash unit can be a three-terminal device and comprises a grid electrode, a source electrode and a drain electrode. In the calculation mode, the gate is connected to WL, the source is connected to SL, and the drain is connected to the input stimulus signal, i.e., the analog input voltage signal.
The operation steps comprise:
step 1: the controller enables the memory computing chip based on the NOR Flash to enter a mode enabling mode;
step 2: the equal-ratio column capacitor is charged according to the input analog voltage signal, when the storage value of the NOR Flash unit is 1, the threshold value of the NOR Flash unit is high, no charge is accumulated on the corresponding capacitor, and Q=0; when the storage value of the NOR Flash unit is 0, the threshold value of the NOR Flash unit is low, charges can be accumulated on the corresponding capacitor, the charge quantity is the product of the capacitor and an input excitation signal, and Q=C×vin;
Step 3: the equal-proportion capacitors of the single calculation points are connected, and the calculation result of the single multiplication operation is obtained according to the principle of equally dividing the parallel capacitors; specifically, a single computation point refers to one of 9 (3 by 3) multiplication computations in the convolution kernel computation.
Step 4: the convolution kernel calculation of corresponding size involves a plurality of multiplications, namely, equal-proportion capacitance connection of a plurality of calculation points is realized, charges of the plurality of calculation points are equally divided, and the final equally divided voltage result is the summation of the calculation results of the plurality of calculation points and multiplied by a fixed coefficient, and the coefficient is the reciprocal of the number of the calculation points.
The input excitation signal and the multi-bit digital weight are multiplied, and the principle formula of single calculation point multiplication calculation is as follows:
the input excitation signal and the multi-bit digital weight are multiplied, and the principle formula of S point multiplication accumulation summation is as follows:
the variables of the two expressions described above are described as follows:
vout: multiplying the analog voltage of the result; vin represents the voltage applied to the drain of the Nor Flash unit, i.e. the multiplicative multiplier 1 (analog signal);
c: the minimum unit capacitance value in the equal-proportion capacitance array (array composed of equal-proportion capacitances);
n: in the equal-proportion capacitors, the number of the equal-proportion capacitors used by a single multiplication calculation point is calculated;
j: calculating the capacitance serial number in the medium-proportion capacitance in a single multiplication point;
w [ j ]: calculating the digital weight of the point by single multiplication;
vouts: output result voltages (analog) of the S multiply-accumulate computations;
vn: the nth multiplication calculates the multiplier (analog signal, voltage applied to drain) of the point;
in the calculation mode, the bit width of the digital weight can be adjusted according to actual calculation requirements, as shown in fig. 7, each NOR Flash unit with written values represents 1 bit of the digital weight, N bit digital weights are represented by N NOR Flash unit combinations, and fig. 7 is a schematic diagram of 3bit digital weights.
Further, in the calculation mode, referring to fig. 8, by controlling the switch module connected with the equal-ratio capacitor array in the NOR Flash Cap unit array module, a single multiplication calculation operation of different bits is realized, that is, the number of equal-ratio capacitors participating in charge sharing is controlled.
In the calculation mode, referring to fig. 9, the operation of the convolution kernel calculation, the scale of the multiply-accumulate operation, for example, the convolution kernel of 3×3,5×5,7×7.
In an alternative embodiment, the controller is connected to each module of the in-memory computing chip, and is used for controlling the state and operation of the in-memory computing chip, such as controlling the working mode of the NOR Flash Cap unit array module, controlling the row-column decoder module to perform row-column decoding, controlling the programming circuit to perform data programming, selecting the processing executed by the analog processing module, controlling the switch module to perform multiplication operation based on the NOR Flash Cap unit, controlling the size of the convolution kernel, controlling the operation executed by the configurable digital processing module, and so on.
The multiply-accumulate operation can be performed based on the charge sharing principle, convolution calculation based on the multiply-accumulate operation can be directly controlled by a combination switch to realize the switching of the convolution kernel size, and the speed and the power consumption are better than those of the prior art based on current calculation.
Next, an arithmetic post-processing module in the calculation mode will be described.
Still further, the arithmetic post-processing module includes at least one of a pooling circuit, a Sigmoid function circuit, a Relu function circuit, a Tanh function circuit, or a BNRelu circuit.
Referring to fig. 10, the arithmetic post-processing module may be used as a configurable digital processing module, which may include various processing circuits commonly used in neural network algorithms, such as a pooling circuit, a Sigmoid function circuit in an activation circuit, a Relu function circuit, a Tanh function circuit, a BNRelu circuit, etc., and various arithmetic circuits are packaged as one digital arithmetic unit, and a plurality of digital arithmetic units may be included in the configurable digital processing module. The invention can realize further arithmetic operation of the operation result output by the memory cell array, improves the applicability of the memory-calculation integrated chip and expands the application range.
The digital processing units of the configurable digital processing modules are connected in series, and different numbers of digital operation units can be used according to the calculation requirements, referring to fig. 11, each configurable digital processing module can include: a demultiplexer, a digital operation unit and a multiplexer.
The input end of the demultiplexer is connected with a configurable digital processing module or an analog-to-digital conversion module, the first output end of the demultiplexer is connected with a digital operation unit, the output end of the digital operation unit and the second output end of the demultiplexer are connected with the next configurable digital processing module or an output register module through a multiplexer, or the multiplexer is used as the output end, and in addition, the control ends of the demultiplexer and the multiplexer are connected with a controller.
As another alternative embodiment, the connection relationship of the plurality of configurable digital processing modules is as follows:
the input end of the demultiplexer in the first configurable digital processing module is connected with the output end of the analog-to-digital conversion module, the first output end of the first configurable digital processing module is connected with the input end of the digital operation unit in the first configurable digital processing module, the second output end of the first configurable digital processing module and the output end of the digital operation unit are connected with the input end of the second configurable digital processing module through a multiplexer, and the demultiplexer and the control end of the multiplexer are connected with a controller.
The input end of the demultiplexer in the second configurable digital processing module is connected with the output end of the first configurable digital processing module, the first output end of the second configurable digital processing module is connected with the input end of the digital operation unit in the second configurable digital processing module unit, the second output end of the second configurable digital processing module and the output end of the digital operation unit are connected with the input end of the third configurable digital processing module through a multiplexer, and the control ends of the demultiplexer and the multiplexer are connected with the controller. And the like, until the Nth configurable digital processing module, the input end of a demultiplexer in the Nth configurable digital processing module is connected with the output end of the N-1 th configurable digital processing module, one output end of the demultiplexer is connected with the input end of a digital operation unit in the Nth configurable digital processing module unit, the other output end of the demultiplexer and the output end of the digital operation unit are connected with the input end of an output register through a multiplexer or serve as output ends, and the control ends of the demultiplexer and the multiplexer are connected with a controller.
The embodiment of the invention also provides a control method of the memory computing chip based on the NOR Flash, which is applied to the controller in the memory computing chip based on the NOR Flash, and comprises the following steps:
determining a working mode of an in-memory computing chip, wherein the working mode comprises a storage mode and a computing mode;
when the working mode is the storage mode, performing data programming on a NOR Flash unit in a NOR Flash Cap unit array module and detecting whether the data programming is correct or not;
when the working mode is the calculation mode, controlling an input interface module, a row-column decoder module and a programming circuit module in the in-memory calculation chip to jointly finish the erasing and reading operation of the NOR Flash Cap cell array module;
and/or the number of the groups of groups,
when the working mode is the calculation mode, controlling the NOR Flash Cap unit array module to carry out multiply-accumulate operation; controlling the input voltage of the interface input module and each equipartition switch in the NOR Flash Cap unit array module to adjust the bit width of the digital input signal in the multiply-accumulate operation; and controlling the opening and closing states of the equipartition switches in the multiplication and accumulation operation process so as to carry out convolution operations with different sizes.
The embodiment of the invention also provides a storage device which comprises the memory computing chip based on the NOR Flash, wherein the memory computing chip is used for storing data.
Referring to fig. 12, an embodiment of the present invention further provides an electronic device, including a processor, an SRAM, a communication interface, a bus (i.e., the high-speed communication bus in fig. 12), and a NOR Flash-based in-memory computing chip (i.e., the NOR Flash Cap-in-memory computing chip in fig. 12) as described above;
the communication interface is used for exchanging data with external equipment;
the processor, the SRAM, the communication interface and the in-memory computing chip are respectively connected with the bus.
In particular, the processor may be a microprocessor, which may act as a master device, may be implemented based on different instruction sets, and an alternative embodiment is an riscv-based microprocessor. The in-memory computing chip based on the NOR Flash can be used as a slave device, and the structure of the in-memory computing chip based on the NOR Flash is as described above and is not described herein.
The electronic device of the invention can communicate (receive data or output data) with external devices through the communication interface, and the communication interface and the in-memory computing chip can be in communication connection through a bus.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present invention are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
Furthermore, while the invention is described in the context of functional modules, it should be appreciated that, unless otherwise indicated, one or more of the described functions and/or features may be integrated in a single physical device and/or software module or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be apparent to those skilled in the art from consideration of their attributes, functions and internal relationships. Accordingly, one of ordinary skill in the art can implement the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative and are not intended to be limiting upon the scope of the invention, which is to be defined in the appended claims and their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing an electronic device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the embodiments described above, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are included in the scope of the present invention as defined in the appended claims.
Claims (10)
1. An in-memory computing chip based on NOR Flash, comprising: the device comprises an input interface module, a NOR Flash Cap unit array module, a controller and an output interface module;
the input interface module is used for receiving target data;
the NOR Flash Cap unit array module comprises a plurality of NOR Flash units with adjustable threshold voltage and a plurality of equal-proportion capacitors;
in a storage mode, the NOR Flash unit is used for storing the target data;
in a calculation mode, the NOR Flash unit and the equal-proportion capacitor are used for calculating according to the target data; the calculation mode adopts a charge sharing principle to calculate;
The controller is used for controlling the in-memory computing chip to switch between the storage mode and the computing mode;
the output interface module is used for outputting data.
2. The NOR Flash based in-memory computing chip of claim 1, wherein said NOR Flash Cap cell array module is a two-dimensional structure, and a plurality of said NOR Flash cells form a two-dimensional array structure in said NOR Flash Cap cell array module; each NOR Flash unit comprises a grid electrode, a drain electrode and a source electrode;
in the NOR Flash Cap unit array module, the grid electrodes of all NOR Flash units in each row are connected to the same word line, and a plurality of rows of NOR Flash units are correspondingly connected with a plurality of word lines; the drains of all NOR Flash units in each column are connected with the same bit line, the sources of all NOR Flash units in each column are connected with the same source line, the sources of all NOR Flash units in each column are also connected with the upper polar plate of one equal-proportion capacitor, and the lower polar plate of each equal-proportion capacitor is connected with the ground.
3. The memory computing chip based on NOR Flash as claimed in claim 2, wherein said memory computing chip further comprises a plurality of equipartition switches and a grounding switch;
One end of each equipartition switch is connected with a corresponding public end, and the connection end of the source electrode of each NOR Flash unit and the upper polar plate of one equal-proportion capacitor is used as the public end;
the other ends of all the equipartition switches are commonly connected to one end of the grounding switch, and the other end of the grounding switch is connected with the ground;
the controller is used for generating an enabling signal and controlling an enabling switch of the storage mode and an enabling switch of the calculation mode according to the enabling signal so as to control the in-memory calculation chip to switch between the storage mode and the calculation mode.
4. The NOR Flash based in-memory computing chip of claim 2, wherein said in-memory computing chip further comprises a rank decoder module and a programming circuit module; the output interface module comprises an analog processing module and an arithmetic post-processing module;
one end of the input interface module is connected with the first end of the row-column decoder module, the second end of the row-column decoder module is connected with the first end of the NOR Flash Cap cell array module, and the third end of the row-column decoder module is connected with the programming circuit module; one end of the analog processing module is connected with the second end of the NOR Flash Cap unit array module, and the other end of the analog processing module is connected with one end of the arithmetic post-processing module; the other end of the arithmetic post-processing module is connected with one end of the output interface module;
In the storage mode, the word line is used for receiving a row selection signal of the NOR Flash unit, the bit line is used as a voltage input end, and the source line is used as an analog current output end; the input interface module, the row-column decoder module and the programming circuit module jointly complete the erasing and reading operation of the NOR Flash Cap cell array module; the analog processing module is used for converting an analog voltage signal or a current signal output by the NOR Flash Cap unit array module into a digital signal; the arithmetic post-processing module is used for carrying out arithmetic operation according to the digital signal.
5. The NOR Flash based memory computing chip of claim 3 wherein said input interface module is an analog input signal module and said output interface module comprises an analog to digital conversion module, a digital processing circuit and an arithmetic post-processing module;
the first end of the controller is connected with the first end of the analog input signal module, and the second end of the controller is respectively connected with the first end of the analog-to-digital conversion module, the first end of the digital processing circuit and the first end of the arithmetic post-processing module; the second end of the analog input signal module is connected with the first end of the NOR Flash Cap unit array module, and the first end of the NOR Flash Cap unit array module is the drain electrode of the NOR Flash unit; the second end of the analog-to-digital conversion module is connected with the second end of the NOR Flash Cap cell array module, and the third end of the analog-to-digital conversion module is connected with the second end of the digital processing circuit; the third end of the digital processing circuit is connected with the second end of the arithmetic post-processing module;
The analog input signal module is used for receiving the target data; the analog-to-digital conversion module is used for converting an analog voltage signal or a current signal output by the NOR Flash Cap unit array module into a digital signal; the digital processing circuit is used for preprocessing the digital signal; the arithmetic post-processing module is used for carrying out arithmetic operation according to the preprocessed digital signals;
in the computing mode, the word line is used for receiving a column selection signal of the NOR Flash unit; the voltage signal on the bit line is used as an input excitation signal of multiply-accumulate operation, and the source line is in a disconnection state; the number of the equal-proportion capacitors is the same as the bit width of the digital weight in the multiplication and accumulation operation, and the equal-proportion capacitors are used for charging in the multiplication operation process based on charge average; when the NOR Flash Cap cell array module does not input an excitation signal, the grounding switch and all the equipartition switches are in a closed state so as to empty the charges of all the equal-ratio column capacitors.
6. The NOR Flash based in-memory computing chip of claim 5 wherein in said computing mode said divide-and-divide switch is configured to divide charge generated during a charge-division based multiply-and-accumulate operation equally across all of said equal-ratio column capacitors;
In the calculation mode, the controller is further used for controlling the input voltage of the interface input module and each equipartition switch to adjust the bit width of the digital input signal in the multiply-accumulate operation; the controller is also used for controlling the opening and closing states of the equipartition switches in the multiplication and accumulation operation process so as to carry out convolution operations with different sizes.
7. The NOR Flash based in-memory computing chip of claim 5, wherein said arithmetic post-processing module comprises at least one of a pooling circuit, a Sigmoid function circuit, a Relu function circuit, a Tanh function circuit, or a BNRelu circuit.
8. A control method of an in-memory computing chip based on NOR Flash, which is applied to the controller in an in-memory computing chip based on NOR Flash as claimed in any one of claims 1 to 7, the method comprising:
determining a working mode of an in-memory computing chip, wherein the working mode comprises a storage mode and a computing mode;
when the working mode is the storage mode, performing data programming on a NOR Flash unit in a NOR Flash Cap unit array module and detecting whether the data programming is correct or not;
when the working mode is the calculation mode, controlling an input interface module, a row-column decoder module and a programming circuit module in the in-memory calculation chip to jointly finish the erasing and reading operation of the NOR Flash Cap cell array module;
And/or the number of the groups of groups,
when the working mode is the calculation mode, controlling the NOR Flash Cap unit array module to carry out multiply-accumulate operation; controlling the input voltage of the interface input module and each equipartition switch in the NOR Flash Cap unit array module to adjust the bit width of the digital input signal in the multiply-accumulate operation; and controlling the opening and closing states of the equipartition switches in the multiplication and accumulation operation process so as to carry out convolution operations with different sizes.
9. A memory device comprising a NOR Flash based in-memory computing chip according to any of claims 1 to 7, said in-memory computing chip being adapted to store data.
10. An electronic device comprising a processor, an SRAM, a communication interface, a bus, and an in-memory NOR Flash-based computing chip according to any one of claims 1 to 7;
the communication interface is used for exchanging data with external equipment;
the processor, the SRAM, the communication interface and the in-memory computing chip are respectively connected with the bus.
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