CN113793800B - Impurity removing process and manufacturing process of semiconductor monocrystalline silicon wafer - Google Patents
Impurity removing process and manufacturing process of semiconductor monocrystalline silicon wafer Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B08—CLEANING
- B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
- B08B7/00—Cleaning by methods not provided for in a single other subclass or a single group in this subclass
- B08B7/0014—Cleaning by methods not provided for in a single other subclass or a single group in this subclass by incorporation in a layer which is removed with the contaminants
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02041—Cleaning
- H01L21/02096—Cleaning only mechanical cleaning
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Abstract
The invention discloses a process for removing impurities from a semiconductor monocrystalline silicon wafer and a process for manufacturing the semiconductor monocrystalline silicon wafer, wherein the process for removing impurities comprises the steps of carrying out heat treatment on the silicon wafer, forming a layer of gettering layer containing oxygen precipitate micro defects within the range of not more than 20 mu m in thickness of the surface layer of the silicon wafer, capturing metal impurities on the surface layer and in the body of the silicon wafer by the gettering layer, and polishing and removing the metal impurities. The silicon wafer processed by the impurity removal process of the semiconductor monocrystalline silicon wafer can effectively reduce the metal pollution level of the silicon wafer and can keep the stability of the surface metal pollution level for a long time.
Description
Technical Field
The invention belongs to the technical field of semiconductor monocrystalline silicon, and particularly relates to a impurity removal process and a manufacturing process of a semiconductor monocrystalline silicon wafer with low metal pollution level.
Background
Monocrystalline silicon wafers are the main substrate material of modern very large scale integrated circuits, and the crystal bars obtained by pulling by the CZ method are manufactured by the technological processes of slicing, chamfering, grinding, corrosion, polishing, cleaning, detecting and the like to obtain integrated circuit grade semiconductor wafers. With the shrinking of semiconductor line widths and the increasingly stringent requirements of IC devices for dark currents, lower and better metal impurity concentrations within the silicon wafer are required. In the manufacturing process of the silicon wafer, besides the purity of the polycrystalline silicon raw material used for preparing the crystal bar, factors such as tools, equipment, liquid medicine, environmental conditions, personnel operation and the like involved in each working procedure of the silicon wafer molding and processing process can influence the surface metal and bulk metal pollution level of the silicon wafer. For example, in the alkali corrosion process, alkali liquor contains more metal impurities, and under the high-temperature corrosion process condition, the alkali liquor possibly permeates and diffuses into the silicon wafer body, so that the content of bulk metal exceeds the standard. In order to obtain a silicon wafer with a certain metal pollution level, in the process of processing the silicon wafer, each procedure cleans the surface of the silicon wafer, removes residual materials and metal pollution left by the previous processing technology, and controls the surface metal pollution to be at a certain level. The metal pollution level of the silicon wafer can be ensured to meet the requirement through procedures such as cleaning before packaging and leaving factory, but in the actual production process, as metals such as copper, nickel and the like are more active, the metals migrate to the surface of the silicon wafer in the standing process, the silicon wafer which is qualified in the original metal pollution level test stands for a period of time, and the surface metals are found to be increased and even exceed the specification requirement.
For example, chinese patent application CN112059736a, before final cleaning, performs low-temperature annealing to diffuse metal in the silicon wafer to the surface, and then removes the metal diffused to the surface through the final cleaning process, so as to reduce the surface metal pollution level, but if the silicon wafer treated by this process is left to stand still, migration and diffusion of metal in the body may still occur, so that the surface metal pollution level cannot be kept stable. CN109872941a oxidizes the surface of the silicon wafer to form an oxide film, heats the bottom of the silicon wafer at low temperature and irradiates with microwave, so that the metal inside the silicon wafer diffuses into the oxide film on the surface, and finally the oxide film on the surface of the silicon wafer and the metal adsorbed therein are etched away by the acidic etching solution, thereby reducing the metal pollution level of the silicon wafer, but this method requires additional acid etching cleaning process.
Therefore, a new impurity removal process for monocrystalline silicon wafers is still needed to obtain high quality silicon wafers.
Disclosure of Invention
The invention aims to provide a process for removing impurities from a semiconductor monocrystalline silicon wafer, which can greatly reduce the surface metal and bulk metal pollution level of the silicon wafer and obtain a silicon wafer with higher quality.
Another object of the present invention is to provide a process for producing a semiconductor single crystal silicon wafer comprising such a process for removing impurities.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
a process for removing impurities from a semiconductor monocrystalline silicon wafer comprises the following steps:
1) Performing heat treatment on the silicon wafer, and forming a layer of oxygen-containing precipitate micro-defect gettering layer within the range that the thickness of the surface layer of the silicon wafer is not more than 20 mu m;
2) Polishing the silicon wafer after heat treatment, and removing the gettering layer.
In a specific embodiment, the heat treatment process in step 1) is:
a) Heating the silicon wafer to 1200-1350 ℃ in a rapid annealing furnace at a heating rate of 50-200 ℃/s, preserving heat for not more than 3 seconds, cooling to 800-950 ℃ at a cooling rate of 50-200 ℃/s, and naturally cooling;
b) And c), delivering the silicon wafer treated in the step a) into a heat treatment furnace with the initial temperature of 600-800 ℃ to perform oxygen precipitation nucleation and growth heat treatment.
In a specific embodiment, the atmosphere of the rapid annealing furnace in the step a) is selected from at least any one of argon, helium, nitrogen or ammonia, or at least any one of argon, helium, nitrogen or ammonia is filled with hydrogen with the volume content of which is not more than 5%, preferably pure ammonia; the atmosphere of the heat treatment furnace in the step b) is selected from any one of argon, helium or nitrogen, preferably argon.
In a preferred embodiment, the rapid annealing furnace in step a) has a heating rate of 100-200 ℃/s, a holding temperature of 1250-1300 ℃, a holding time of 100 ms-1 s, and a cooling rate of 100-200 ℃/s.
In a preferred embodiment, the oxygen precipitation nucleation and growth heat treatment process in step b) is carried out by holding the temperature in a heat treatment furnace at 600-800 ℃ for 4 hours, holding the temperature at 900-1100 ℃ for 16 hours, or heating to 900-1100 ℃ at a heating rate of not more than 2 ℃/min and holding the temperature for 4-16 hours for annealing; preferably, the temperature is raised to 900-1100 ℃ at a heating rate of not higher than 2 ℃/min and the annealing is kept at the temperature for 4-16 hours.
In a specific embodiment, the oxygen precipitation nucleation and growth heat treatment process in step b) is to heat up to 1000-1050 ℃ in a heat treatment furnace at a heating rate of 0.5-1 ℃/min and keep annealing at that temperature for 4-16 hours.
In a specific embodiment, in the step 1), a gettering layer containing oxygen precipitate micro defects is formed within the range of 5-10 μm in thickness of the surface layer of the silicon wafer.
In a specific embodiment, the silicon wafer in the step 2) is polished after heat treatment, and the oxygen precipitation density in the surface layer of the polished silicon wafer is not less than 1E9/cm 3 。
In another aspect, a process for manufacturing a semiconductor single crystal silicon wafer includes the aforementioned process for impurity removal of a semiconductor single crystal silicon wafer.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, after alkali corrosion in silicon wafer production/before polishing, the silicon wafer is subjected to heat treatment, a gettering layer is formed on the surface layer of the silicon wafer, so that metal pollution in the silicon wafer is absorbed in the gettering layer, and the gettering layer is removed through a subsequent polishing procedure, so that the bulk metal pollution level of the silicon wafer is greatly reduced, and meanwhile, the stability of the surface metal pollution level can be ensured due to the low content of the whole metal impurities of the silicon wafer.
The invention adopts a rapid annealing combined heat treatment process method, and forms oxygen precipitation with sufficient density in a certain thickness area of the surface layer of the silicon wafer by controlling the process parameters such as heating rate, annealing atmosphere, heat preservation time and the like, and the oxygen precipitation is taken as a trapping center of metal impurities, so that the metal impurities of the whole silicon wafer are absorbed into the certain thickness area of the surface layer of the silicon wafer, the surface layer is removed later in a polishing process, and the polished silicon wafer is subjected to pre-cleaning and final cleaning, thereby ensuring that the bulk metal and surface metal pollution in the gettering layer of the silicon wafer are removed, and the quality of the silicon wafer is greatly improved.
Drawings
Fig. 1 is a schematic diagram of a conventional silicon wafer processing process flow.
FIG. 2 is a schematic view of a process flow for manufacturing a monocrystalline silicon piece according to the present invention.
FIG. 3 is a schematic representation of the dynamic distribution of vacancy concentration and interstitial silicon atom concentration on and within a wafer during a rapid thermal processing phase.
FIG. 4 is a graphical representation of vacancy concentration and interstitial silicon atom concentration profiles on and within a wafer under ideal conditions for a sufficiently long soak time.
FIG. 5 is a graphical representation of the vacancy point defect concentration profile of a single crystal wafer after heat treatment in accordance with the present invention.
FIG. 6 is a schematic diagram showing the distribution of gettering layers of oxygen-containing precipitate micro-defects on the surface layer of a silicon wafer after heat treatment of a single crystal silicon wafer according to the present invention.
FIG. 7 is a schematic diagram showing the distribution of oxygen precipitate micro-defects in a silicon wafer after being treated by a rapid annealing internal gettering process.
FIG. 8 is a graph showing the Cu concentration of the surface metal of the silicon wafer of comparative example 4 according to the present invention.
FIG. 9 is a graph showing the trend of Cu concentration of the surface metal of a silicon wafer according to the embodiment of the invention.
Detailed Description
The following examples will further illustrate the method provided by the present invention for a better understanding of the technical solution of the present invention, but the present invention is not limited to the examples listed but should also include any other known modifications within the scope of the claims of the present invention.
As shown in FIG. 1, the production process of the silicon wafer in the prior art comprises the working procedures of grinding, alkali corrosion, polishing, cleaning and the like of the rear end besides the single crystal drawing, rounding, cutting-slicing and chamfering of the front end, and specifically comprises the steps of grinding, alkali corrosion, edge polishing, cleaning after double-sided polishing, cleaning after polishing, final polishing, pre-cleaning, detection, final cleaning and packaging.
As shown in fig. 2, the cleaning process before the etching process, polishing and after the polishing process of the present invention is the same as the conventional process, and the apparatus and specific process used in these processes can be referred to the prior art, which is also well known to those skilled in the art. The invention adds the heat treatment step before polishing, and the polishing thickness is different according to the position of the heat treatment formed ground-sucking layer, or the invention adds the impurity removing process based on the prior art.
Specifically, the impurity removal process of the semiconductor monocrystalline silicon wafer mainly comprises the following steps:
(1) After cleaning the corrosion piece, carrying out heat treatment on the silicon wafer, and forming a layer of oxygen-containing precipitate micro-defect gettering layer within the range that the thickness of the surface layer of the silicon wafer is not more than 20 mu m;
(2) And polishing the silicon wafer after the heat treatment to remove the gettering layer.
The manufacturing process of the invention carries out heat treatment on the silicon wafer after alkali corrosion, and the heat treatment process comprises the following steps:
a) Heating the silicon wafer to 1200-1350 ℃ in a rapid annealing furnace at a heating rate of 50-200 ℃/s, preserving the heat of the silicon wafer at 1200-1350 ℃ for not more than 3 seconds, cooling to 800-950 ℃ at a cooling rate of 50-200 ℃/s, and naturally cooling.
b) The silicon wafer is sent into a heat treatment furnace with the initial temperature of 600-800 ℃ to carry out oxygen precipitation nucleation and growth heat treatment, wherein the oxygen precipitation nucleation and growth heat treatment process is 600-800 ℃/4 hours +900 ℃ -1100 ℃/16 hours or is heated to 900-1100 ℃ at the heating rate of not higher than 2 ℃/min and is annealed in a heat preservation way for 4-16 hours at the temperature, and the heating rate of not higher than 2 ℃/min is preferably heated to 900-1100 ℃ and is annealed in a heat preservation way for 4-16 hours at the temperature.
The heat treatment step a) of the present invention may be carried out using any commercial RTP annealing furnace, and the heat treatment furnace in step b) may be a conventional commercial vertical or horizontal tubular annealing furnace.
When RTP is adopted for rapid temperature rise and reduction, the defect concentration of the hollow site of the silicon wafer changes as follows:
in the rapid heating stage, under the action of high temperature, the concentration of vacancies and interstitial silicon atom concentration distribution on the surface and inside of the silicon wafer are shown in figure 3, the concentration of vacancies on the surface and inside of the silicon wafer is greatly higher than that of interstitial silicon atom, the internal point defects of the silicon wafer are mainly Frank defects, the concentration of vacancies and interstitial silicon atom concentration are equal, the silicon wafer is in a dynamic balance state, point defect pairs are generated continuously, and the vacancies and interstitial silicon point defects are annihilated continuously. Because the concentration of surface vacancies is greater than the concentration in the interior of the wafer and the concentration of surface interstitial silicon atoms is less than the concentration in the interior of the wafer, vacancies have a tendency to diffuse from the surface to the interior and interstitial silicon atoms have a tendency to diffuse from the interior to the surface.
The equilibrium vacancy concentration and equilibrium interstitial silicon atom concentration levels in figure 3 are related to the temperature, the higher the temperature the greater the concentration, and when the temperature is raised to 1200-1350 c, the vacancies diffuse from the wafer surface to the interior due to the concentration differential, and if the holding time is long enough the point defect concentration profile is ideal as shown in figure 4.
Based on the dynamic distribution characteristic, the invention unexpectedly discovers that when the heat preservation time is short enough (less than 3 seconds) and the temperature rising and falling speed is high enough (more than 50 ℃/s), the diffusion process of the vacancy point defects on the surface layer is not completed yet, and when the temperature after heat preservation is rapidly reduced to below 950 ℃, the concentration distribution of the vacancy point defects is kept as shown in figure 5, and the vacancy point defects can be enriched near the surface layer of the silicon wafer.
When the process has long temperature keeping time and insufficient temperature raising and lowering speed, the vacancy point defect density distribution, namely the oxygen precipitate micro defect density distribution, is shown in figure 7, which is the internal gettering process known in the semiconductor industry, and can fully absorb impurity metal pollution, but because the gettering center is positioned in the silicon wafer body, under certain process conditions, impurities absorbed by the silicon wafer body, such as iron, can be released again, so that the device preparation yield is influenced.
Meanwhile, when the atmosphere is ammonia gas during rapid temperature rise and drop, the ammonia gas can be partially decomposed at high temperature to generate free nitrogen atoms, the free nitrogen atoms can react with the silicon wafer, incomplete nitridation occurs on the surface of the silicon wafer to generate silicon nitride, a large number of vacancies are formed at the interface of the silicon nitride and the silicon, and the vacancies diffuse into the silicon wafer. The vacancy concentration profile shown in fig. 5 can be further enhanced in a nitrogen or ammonia-containing atmosphere. In this way, under the combined action of the factors of rapid temperature rise and drop, high heat preservation temperature, nitrogen-containing atmosphere, short heat preservation time and the like, the vacancy point defect concentration distribution as shown in fig. 5 is finally formed. And the inventor researches that the concentration of the surface vacancies and the concentration distribution in the depth direction can be adjusted by adjusting the temperature rise and fall speed, the temperature keeping temperature, the temperature keeping time, the annealing atmosphere and other factors.
The atmosphere of the rapid annealing furnace in the step a) is argon, helium, nitrogen, ammonia or mixed gas thereof, and hydrogen with the volume content of not more than 5% can be introduced into the annealing furnace gas, so that the outward diffusion of surface oxygen can be promoted in high-temperature heat treatment to remove an oxide layer, and pure ammonia is preferred.
After the rapid temperature increase in step a) of the present invention to 1200-1350 c, the higher this temperature, the greater the surface vacancy point defect concentration, but the higher the wafer temperature, the closer to the silicon melting point, potentially leading to wafer warpage, preferably 1250-1300 c.
In the step a), the rapid temperature rise and fall rate is 50-200 ℃/s, and theoretically, the larger the temperature rise and fall rate of the silicon wafer is, the more favorable the generation and the reservation of superficial empty site defects are, but the temperature rise and fall rate is limited by the capacity of the existing equipment on one hand, and in addition, the defects such as the sliding of the silicon wafer and the like can be caused by the excessively high temperature rise and fall rate, preferably 100-150 ℃/s.
The high-temperature heat preservation time in the step a) is not more than 3 seconds, the longer the heat preservation time is, the longer the vacancy diffusion time is, the greater the depth of high vacancy concentration in the surface layer of the silicon wafer is, the more oxygen precipitation micro defects are generated, the more impurity metal gettering is facilitated, but the thicker the surface layer of the silicon wafer needs to be removed is; the shorter the hold time, the smaller the depth of high vacancy concentration in the wafer surface layer, and the smaller the thickness of the wafer surface layer to be removed, but the less the gettering effect, the preferred hold time is 100 milliseconds to 1 second.
In the heat treatment step b), the silicon wafer enters a heat treatment furnace with the initial temperature of 600-800 ℃, and the preferable oxygen precipitation nucleation and growth heat treatment process is heated to 900-1100 ℃ at the heating rate of not higher than 2 ℃/min and is subjected to heat preservation annealing for 4-16 hours at the temperature. The silicon wafer may promote the formation of nucleation centers for oxygen precipitation by forming a complex of the vacancy defects formed in step a) and interstitial oxygen in the wafer. Under high temperature treatment, oxygen atoms and vacancies in the silicon wafer gradually gather and nucleate, and oxygen precipitates gradually grow up to become metal impurity gettering traps. In the traditional rapid annealing internal gettering process, the oxygen precipitation nucleation process and the growth process are carried out step by step, and typical processes are as follows: the oxygen precipitation nucleation process is that the temperature is kept at 800 ℃ for 4 hours; the oxygen precipitation growth process is 900-1100 ℃ and the temperature is kept for 16 hours. The invention adopts a one-step high-temperature heat treatment process, and the nucleation and oxygen precipitation growth process are synchronously carried out under low-speed temperature rise, so that the process time can be greatly reduced, and the thermal budget can be reduced. In step b), as the oxygen precipitates are formed, metal-contaminated impurities in the silicon wafer migrate at high temperature and are adsorbed and immobilized by the surface oxygen precipitates. The temperature of the thermal annealing in the heat treatment step b) is preferably 1000 to 1050 ℃.
In the heat treatment step b) of the invention, the temperature rising rate is not more than 2 ℃/min, preferably 0.5-1 ℃/min, at the temperature rising rate, the oxygen diffusion rate is faster than the diffusion rate at the fixed heat preservation temperature, the oxygen precipitation growth rate is improved, and meanwhile, the oxygen precipitation size is larger than the critical oxygen precipitation size at the corresponding temperature due to the slower temperature rising rate, the phenomenon of oxygen precipitation melting caused by the temperature rising can not occur, so that the heat treatment time is reduced while the higher oxygen precipitation density is obtained.
In the invention, the silicon wafer is subjected to heat treatment, and the thickness of the impurity-absorbing oxygen precipitate formed in the surface layer of the silicon wafer is not more than 20 microns, preferably 5-10 microns, by adjusting the technological parameters such as the temperature raising and lowering speed, the temperature maintaining temperature, the temperature maintaining time, the annealing atmosphere and the like in the heat treatment steps a) and b), because the single-sided removal amount of the surface layer in the general polishing procedure is 5-10 microns in the silicon wafer production process. The concentration and distribution of oxygen precipitates formed after the final heat treatment are shown in FIG. 6, and the distribution form of FIG. 5 is consistent.
After heat treatment, the silicon wafer is polished, and the surface layer with the oxygen precipitation density of more than 1E9 in the silicon wafer is removed in the polishing procedure, wherein the thickness of the removed surface layer is not more than 20 microns, preferably 5-10 microns, and the silicon wafer with high quality is finally obtained through the subsequent processes of cleaning and the like, so that the metal pollution level of the silicon wafer can be effectively reduced, and the stability of the metal pollution level of the surface can be maintained for a long time.
The manufacturing process of the present invention is further illustrated by the following more specific examples, without any limitation.
The heat treatment furnace is 3202 type of thermco company, and the rapid annealing furnace is vantage vulcan RTP type of application material company;
the sampling tool for measuring the metal content of the silicon wafer surface is PVA TePLa company VPD, and the model is WSPS;
the surface metal measuring equipment is Agilent ICP-MS, and the model is 8900;
the manufacturer of the double-sided polishing machine is the labmaster company, and the model is AC2000;
the etched wafer manufacturer is medium-grade with a thickness of about 800 microns.
And (3) taking a 300mm silicon corrosion piece with the thickness of about 800 microns produced by a Czochralski method, cleaning by adopting an RCA cleaning method, performing heat treatment, polishing and cleaning after polishing on the cleaned corrosion piece according to the following examples, and testing the oxygen precipitation density, distribution and surface metal pollution of the silicon piece.
The cleaning flow after the etching sheet is cleaned and polished is shown in the following table:
etching piece RCA washs flow chart
Post-polishing cleaning process flow
Polishing was performed according to the rough polishing-medium polishing-fine polishing process in patent CN111230605 a.
Oxygen precipitation density and distribution test method: and (3) cleaving the silicon wafer along the crystal face, corroding for 5-8 minutes by using Wright corrosive liquid, rinsing and drying by using pure water, observing by using a metallographic microscope, measuring the thickness of the surface layer of the oxygen-containing precipitate, and obtaining the oxygen precipitate density by visually measuring the number of oxygen precipitates in a visual field.
Example 1
Heat treatment step a) placing the silicon wafer in a rapid annealing furnace at a heating rate of 150 ℃/s, heating to 1250 ℃, and holding for 3s, followed byCooling to 900 ℃ at a cooling rate of 150 ℃/s, and taking out the silicon wafer from the rapid annealing furnace for natural cooling for standby, wherein ammonia is in the furnace chamber; step b) the silicon wafer is placed into a heat treatment furnace, the temperature is increased to 900 ℃ from 600 ℃ at a speed of 1 ℃/min, and the temperature is kept for 16 hours, and the atmosphere is 5% oxygen and 95% nitrogen. Testing the oxygen-containing precipitate of the heat-treated silicon wafer had a surface layer thickness of about 9 μm and a density of about 1E9/cm 2 The polishing removed surface layer had a thickness of about 10 microns.
Example 2
The heat treatment step a) is to place the silicon wafer in a rapid annealing furnace to be heated to 1350 ℃ at a heating rate of 200 ℃/s, keep the temperature for 2s, and take out the silicon wafer from the rapid annealing furnace to be naturally cooled for standby after the temperature is reduced to 800 ℃ at a cooling rate of 200 ℃/s, wherein argon is in the furnace chamber; step b) the silicon wafer is placed in a heat treatment furnace, the temperature is increased from 700 ℃ to 1000 ℃ at the speed of 0.5 ℃/min, and the temperature is kept for 4 hours, and the atmosphere is 5% oxygen and 95% nitrogen. Testing the oxygen-containing precipitate of the heat-treated silicon wafer had a surface layer thickness of about 5 μm and a density of about 9E9/cm 2 The polishing removed surface layer was about 6 microns thick.
Example 3
The heat treatment step a) is to place the silicon wafer in a rapid annealing furnace to be heated to 1300 ℃ at a heating rate of 100 ℃/s and to keep the temperature for 1s, and then take out the silicon wafer from the rapid annealing furnace to be naturally cooled for standby after the temperature is reduced to 950 ℃ at a cooling rate of 100 ℃/s, wherein the nitrogen is in the furnace chamber; step b) the silicon wafer is placed into a heat treatment furnace, the temperature is increased from 800 ℃ to 1100 ℃ at a speed of 2 ℃/min, and the temperature is kept for 10 hours, and the atmosphere is 5% oxygen and 95% nitrogen. Testing the oxygen-containing precipitate of the heat-treated silicon wafer had a surface layer thickness of about 18 μm and a density of about 5E9/cm 2 The polished removed surface layer had a thickness of about 20 microns.
Example 4
The heat treatment step a) is to place the silicon wafer in a rapid annealing furnace to be heated to 1200 ℃ at a heating rate of 50 ℃/s and a heat preservation time of 100ms, and then take out the silicon wafer from the rapid annealing furnace to be naturally cooled for standby after the temperature is reduced to 850 ℃ at a cooling rate of 50 ℃/s, wherein the nitrogen is in the furnace chamber; and b) placing the silicon wafer into a heat treatment furnace, preserving heat at 800 ℃ for 4 hours, and preserving heat at 1000 ℃ for 16 hours, wherein the atmosphere is 5% oxygen and 95% nitrogen. Test heat treatmentThe thickness of the surface layer of the oxygen-containing sediment of the silicon wafer is about 19 micrometers, and the density is about 2E10/cm 2 The polished removed surface layer had a thickness of about 20 microns.
Comparative example 1
The heat treatment step a) is to place the silicon wafer in a rapid annealing furnace to be heated to 1250 ℃ at a heating rate of 150 ℃/s and to keep the temperature for 10s, and then take out the silicon wafer from the rapid annealing furnace to be naturally cooled for standby after the temperature is reduced to 900 ℃ at a cooling rate of 150 ℃/s, wherein ammonia gas is in the furnace chamber; step b) the silicon wafer is placed into a heat treatment furnace, the temperature is increased to 900 ℃ from 600 ℃ at a speed of 1 ℃/min, and the temperature is kept for 16 hours, and the atmosphere is 5% oxygen and 95% nitrogen. The distribution of oxygen precipitation of the silicon wafer after heat treatment is tested, no oxygen precipitation is found in the thickness of about 10 microns on the surface layer, the oxygen precipitation is mainly distributed in the silicon wafer body with the thickness of more than 10 microns, and the density is about 7E9/cm 2 。
Comparative example 2
The heat treatment step a) is to place the silicon wafer in a rapid annealing furnace to be heated to 1250 ℃ at a heating rate of 150 ℃/s and a heat preservation time of 3s, and then take out the silicon wafer from the rapid annealing furnace to be naturally cooled for standby after the temperature is reduced to 900 ℃ at a cooling rate of 20 ℃/s, wherein the nitrogen is in the furnace chamber; step b) the silicon wafer is placed into a heat treatment furnace, the temperature is increased to 900 ℃ from 600 ℃ at a speed of 1 ℃/min, and the temperature is kept for 16 hours, and the atmosphere is 5% oxygen and 95% nitrogen. The distribution of oxygen precipitation of the silicon wafer after heat treatment is tested, no oxygen precipitation is found in the thickness of about 60 microns on the surface layer, the oxygen precipitation is mainly distributed in the silicon wafer body with the thickness of more than 60 microns, and the density is about 1E9/cm 2 。
Comparative example 3
The heat treatment step a) is to place the silicon wafer in a rapid annealing furnace to be heated to 1250 ℃ at a heating rate of 20 ℃/s and a heat preservation time of 3s, and then take out the silicon wafer from the rapid annealing furnace to be naturally cooled for standby after the temperature is reduced to 900 ℃ at a cooling rate of 150 ℃/s, wherein the nitrogen is in the furnace chamber; step b) the silicon wafer is placed into a heat treatment furnace, the temperature is increased to 900 ℃ from 600 ℃ at a speed of 1 ℃/min, and the temperature is kept for 16 hours, and the atmosphere is 5% oxygen and 95% nitrogen. The distribution of oxygen precipitation of the silicon wafer after heat treatment is tested, no oxygen precipitation is found in the thickness of about 10 microns on the surface layer, the oxygen precipitation is mainly distributed in the silicon wafer body with the thickness of more than 5 microns, and the density is about 5E9/cm 2 。
Comparative example 4
The etched sheet was directly polished and cleaned without the heat treatment of the present invention.
After the polished silicon wafer is cleaned, firstly, 3 pieces of silicon wafers are respectively tested for surface metal content, and the average measured values are shown in the following table:
a schematic of the distribution of oxygen precipitates in comparative examples 1,2, and 3 is shown in FIG. 7. As can be seen from fig. 7, the oxygen precipitation profile formed in this comparative example is consistent with the oxygen precipitation profile of the rapid annealing process that is currently used in the industry to form the oxygen precipitation internal gettering process, and also has a better impurity removal effect, and comparative examples 1,2 and 3 are another impurity removal process that is currently used more widely.
The 4 silicon wafers of each of example and comparative example 4 were packed in 5 cleaned FOSBs in a class 1 clean room, placed in the clean room, and 1 silicon wafer was taken out every 24 hours to test the metal content, and the average measurement values thereof are shown in fig. 9 and 8.
From the above data, it can be seen that the manufacturing method of the present invention can not only effectively reduce the surface metal contamination level of the silicon wafer, but also maintain the metal contamination level substantially stable over the time of the standing, which is significantly different from that of the comparative example.
While the present invention has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the invention. Those skilled in the art will appreciate that certain modifications and adaptations of the invention are possible and can be made under the teaching of the present specification. Such modifications and adaptations are intended to be within the scope of the present invention as defined in the appended claims.
Claims (12)
1. A process for removing impurities from a semiconductor monocrystalline silicon wafer comprises the following steps:
1) Performing heat treatment on the silicon wafer, and forming a layer of oxygen-containing precipitate micro-defect gettering layer within the range that the thickness of the surface layer of the silicon wafer is not more than 20 mu m;
2) Polishing the silicon wafer after heat treatment, and removing the gettering layer;
the heat treatment process in the step 1) comprises the following steps:
a) Heating the silicon wafer to 1200-1350 ℃ in a rapid annealing furnace at a heating rate of 50-200 ℃/s, preserving heat for not more than 3 seconds, cooling to 800-950 ℃ at a cooling rate of 50-200 ℃/s, and naturally cooling;
b) And c), delivering the silicon wafer treated in the step a) into a heat treatment furnace with the initial temperature of 600-800 ℃ to perform oxygen precipitation nucleation and growth heat treatment.
2. The process according to claim 1, wherein the atmosphere of the rapid annealing furnace in step a) is selected from at least any one of argon, helium, nitrogen and ammonia, or hydrogen is introduced into the at least any one of argon, helium, nitrogen and ammonia in an amount of not more than 5% by volume.
3. The process according to claim 2, wherein the atmosphere of the rapid annealing furnace in step a) is selected from pure ammonia.
4. The process according to claim 1, wherein the atmosphere of the heat treatment furnace in step b) is selected from any one of argon, helium or nitrogen.
5. The process according to claim 4, wherein the atmosphere in the heat treatment furnace in the step b) is argon.
6. The process according to claim 1 or 2, wherein the rapid annealing furnace in step a) has a heating rate of 100-200 ℃/s, a holding temperature of 1250-1300 ℃, a holding time of 100 ms-1 s, and a cooling rate of 100-200 ℃/s.
7. The process according to claim 1 or 4, wherein the oxygen precipitation nucleation and growth heat treatment process in step b) is carried out in a heat treatment furnace at 600-800 ℃ for 4 hours and at 900-1100 ℃ for 16 hours.
8. The process according to claim 1 or 4, wherein the oxygen precipitation nucleation and growth heat treatment process in step b) is performed by heating to 900-1100 ℃ at a heating rate of not more than 2 ℃/min and annealing at the temperature for 4-16 hours.
9. The process according to claim 8, wherein the oxygen precipitation nucleation and growth heat treatment process in step b) is performed by heating to 1000-1050 ℃ in a heat treatment furnace at a heating rate of 0.5-1 ℃/min and annealing at the temperature for 4-16 hours.
10. The process according to claim 1, wherein in step 1), a gettering layer containing micro defects of oxygen precipitate is formed within a thickness range of 5-10 μm on the surface layer of the silicon wafer.
11. The process according to claim 1, wherein the silicon wafer is polished after heat treatment, and the oxygen deposition density in the surface layer of the polished silicon wafer is not lower than 1E9/cm 3 。
12. A process for producing a semiconductor single crystal silicon wafer, characterized by comprising the process for removing impurities of a semiconductor single crystal silicon wafer according to any one of claims 1 to 11.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4851358A (en) * | 1988-02-11 | 1989-07-25 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing |
| CN1329751A (en) * | 1998-12-09 | 2002-01-02 | Memc电子材料有限公司 | An epitaxial silicon wafer with intrinsic gettering and method for preparation thereof |
| CN1769549A (en) * | 2004-11-05 | 2006-05-10 | 北京有色金属研究总院 | Monocrystalline silicon buffing sheet heat treatment process |
| CN107039253A (en) * | 2015-12-15 | 2017-08-11 | 英飞凌科技股份有限公司 | Method for handling Silicon Wafer |
| CN110799678A (en) * | 2016-12-28 | 2020-02-14 | 太阳能爱迪生半导体有限公司 | Method for treating silicon wafers with internal gettering and gate oxide integrity yield |
| CN112289895A (en) * | 2020-12-28 | 2021-01-29 | 常州时创能源股份有限公司 | N-type efficient solar cell and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120049330A1 (en) * | 2009-05-15 | 2012-03-01 | Sumco Corporation | Silicon wafer and method for producing the same |
-
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- 2021-08-18 CN CN202110947117.0A patent/CN113793800B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4851358A (en) * | 1988-02-11 | 1989-07-25 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing |
| CN1329751A (en) * | 1998-12-09 | 2002-01-02 | Memc电子材料有限公司 | An epitaxial silicon wafer with intrinsic gettering and method for preparation thereof |
| CN1769549A (en) * | 2004-11-05 | 2006-05-10 | 北京有色金属研究总院 | Monocrystalline silicon buffing sheet heat treatment process |
| CN107039253A (en) * | 2015-12-15 | 2017-08-11 | 英飞凌科技股份有限公司 | Method for handling Silicon Wafer |
| CN110799678A (en) * | 2016-12-28 | 2020-02-14 | 太阳能爱迪生半导体有限公司 | Method for treating silicon wafers with internal gettering and gate oxide integrity yield |
| CN112289895A (en) * | 2020-12-28 | 2021-01-29 | 常州时创能源股份有限公司 | N-type efficient solar cell and preparation method thereof |
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