CN113792523A - Simulation debugging method and device, computing equipment and computer storage medium - Google Patents
Simulation debugging method and device, computing equipment and computer storage medium Download PDFInfo
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Abstract
The embodiment of the application provides a simulation debugging method, a simulation debugging device, computing equipment and a computer storage medium. Determining a code to be debugged; dividing the code to be debugged into a plurality of code segments according to a set number, and determining a simulation time list and simulation time corresponding to each code segment; determining a code segment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code segment to be simulated; determining a dead cycle code segment from the code segments to be simulated according to a preset detection mechanism; and acquiring the positioning information of the endless loop code segment, and inquiring and debugging the endless loop code segment based on the positioning information. In the embodiment, the efficiency of debugging simulation dead cycle can be improved.
Description
Technical Field
The embodiment of the application relates to the technical field of chip verification, in particular to a simulation debugging method, a simulation debugging device, computing equipment and a computer storage medium.
Background
With the development of the chip verification technology, the verification methodology in the chip verification technology can be efficiently applied to the object-oriented method and the like to build the verification platform, but the simulation technology in the chip verification technology still cannot be efficiently applied to the object-oriented method and the like to build the verification platform.
In a verification environment using a simulation technology, a problem of simulation dead loop (also called simulation hang-up) is usually encountered, and for the problem of simulation dead loop, a single step debugging mode is usually adopted at present (wherein, the single step debugging refers to a debugging means which is usually adopted in program development and used for finding a bug of a program, a procedure of program simulation is tracked step by step, and a cause of an error is found according to a value of a variable.) to solve the problem of simulation dead loop.
However, when the single-step debugging method is used for solving the problem of the dead loop simulation, a great deal of time is required, so that the efficiency of debugging the dead loop simulation is low.
Disclosure of Invention
The embodiment of the application provides a simulation debugging method, a simulation debugging device, a computing device and a computer storage medium, and can improve the efficiency of debugging simulation dead cycles.
In a first aspect, an embodiment of the present application provides a simulation debugging method, including:
determining a code to be debugged;
dividing the code to be debugged into a plurality of code segments according to a set number, and determining a simulation time list and simulation time corresponding to each code segment, wherein the simulation time list comprises a plurality of simulation times and code segment information to be simulated in each simulation time, and the simulation time is used for indicating the execution time of the corresponding code segment;
determining a code segment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code segment to be simulated;
determining a dead cycle code segment from the code segments to be simulated according to a preset detection mechanism;
and acquiring the positioning information of the endless loop code segment, and inquiring and debugging the endless loop code segment based on the positioning information.
Optionally, after the determining a code segment to be simulated according to the current simulation time and the simulation time list and performing simulation verification on the code segment to be simulated, the method further includes:
and printing the code segment which is subjected to the simulation verification in the result log file.
Optionally, the determining, according to a preset detection mechanism, a loop death code segment from the code segments to be simulated includes:
and if the same code segment is detected to be repeatedly printed in the result log file, determining the code segment as a dead cycle code segment.
Optionally, the determining, according to a preset detection mechanism, a loop death code segment from the code segments to be simulated includes:
and if the simulation verification times of a code segment detected in the result log file exceed the preset times, determining the code segment as a dead loop code segment.
Optionally, the determining, according to a preset detection mechanism, a loop death code segment from the code segments to be simulated includes:
and if the simulation time is detected to be continuously increased and the simulation waveform is not increased, determining the code segment currently subjected to simulation verification as the dead loop code segment.
Optionally, the determining a code fragment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code fragment to be simulated includes:
and forming a simulation scheduling queue by the determined code segments to be simulated, and performing simulation verification on the simulation scheduling queue.
Optionally, the determining the code to be debugged includes:
and compiling and simulating the source code file through a VCS command to acquire a code to be debugged.
Optionally, before the obtaining the positioning information of the endless loop code segment, the method includes:
and taking the code range information and the simulation time corresponding to the endless loop code segment as the positioning information of the code segment, and redirecting to the result log file.
In a second aspect, an embodiment of the present application provides an emulation debugging apparatus, including:
the determining module is used for determining a code to be debugged;
the processing module is used for dividing the code to be debugged into a plurality of code segments according to a set number, and determining a simulation time list and simulation time corresponding to each code segment, wherein the simulation time list comprises a plurality of simulation times and the code segments to be simulated in each simulation time, and the simulation times are used for indicating the execution time of the corresponding code segments;
the simulation module is used for determining a code segment to be simulated according to the current simulation time and the simulation time list and carrying out simulation verification on the code segment to be simulated;
the detection module is used for determining a dead cycle code segment from the code segments to be simulated according to a preset detection mechanism;
and the debugging module is used for acquiring the positioning information of the endless loop code segment, and inquiring and debugging the endless loop code segment based on the positioning information.
In a third aspect, an embodiment of the present application provides a computing device, including a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are called and executed by the processing component to implement the emulation debugging method of the first aspect.
In a fourth aspect, an embodiment of the present application provides a computer storage medium, which stores a computer program, and when the computer program is executed by a computer, the simulation debugging method of the first aspect is implemented.
In the embodiment of the application, a code to be debugged is determined; dividing the code to be debugged into a plurality of code segments according to a set number, and determining a simulation time list and simulation time corresponding to each code segment; determining a code segment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code segment to be simulated; determining a dead cycle code segment from the code segments to be simulated according to a preset detection mechanism; the method comprises the steps of obtaining positioning information of the endless loop code segments, inquiring and debugging the endless loop code segments based on the positioning information, determining the endless loop code segments from the code segments to be simulated through a preset detection mechanism, and improving the efficiency of debugging simulation endless loops.
These and other aspects of the present application will be more readily apparent from the following description of the embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a simulation debugging method according to an embodiment of the present application;
fig. 2 is a schematic diagram of a simulation time list provided in an embodiment of the present application;
fig. 3 is a flowchart of another simulation debugging method provided in the embodiment of the present application;
FIG. 4 is a schematic diagram of a simulation waveform provided in an embodiment of the present application;
fig. 5 is a schematic structural diagram of an emulation debugging apparatus according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In some of the flows described in the specification and claims of this application and in the above-described figures, a number of operations are included that occur in a particular order, but it should be clearly understood that these operations may be performed out of order or in parallel as they occur herein, the number of operations, e.g., 101, 102, etc., merely being used to distinguish between various operations, and the number itself does not represent any order of performance. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.
Before introducing a simulation debugging method provided by the present application, a brief introduction is made to related concepts and research backgrounds related to the present application:
(1) related concepts
Single step debugging: the method is a debugging means generally adopted in program development to find program bugs, and the debugging means tracks the program execution flow step by step, and finds the error reasons according to the values of variables.
And (3) endless circulation: in programming, a program that cannot be terminated by its own control is called a "dead loop".
Wherein the dead cycle comprises the following situations:
1. two or more always blocks make a delay-free mutual call (without delay). For example, taking the example that the process block includes the process block a and the process block B, the process block a is assigned 1 at time 0, when any one of the process block a and the process block B changes, the process block B is assigned the inverse value of the process block B to the process block a, and when any one of the process block a and the process block B changes, the process block a is assigned to the process block B.
2. Multiple instantiations of one or more modules in a chip feed back to each other through module ports.
3. Assignments may be interdependent between multiple constants, assignments may be interdependent between constants and gate circuits, or assignments may be interdependent between process blocks and constants.
4. The input and output ports of one or more gates in the chip are interdependent. For example, the gate circuit includes a gate circuit C and a gate circuit D, and the output value of the output port of the gate circuit C is input to the input port of the gate circuit D, and the output value of the gate circuit D is input to the input port of the gate circuit C.
(2) Background of the study
The inventor finds that: in the current simulation verification simulation, when a simulation loop death problem (also called simulation hang-up) is encountered, an industry person usually finds a code segment in which the loop death occurs by adopting a single step debugging mode, so as to solve the simulation loop death problem. However, when the single-step debugging method is used for solving the problem of the dead loop simulation, a great deal of time is required, so that the efficiency of debugging the dead loop simulation is low.
In order to solve the problem of low efficiency of debugging simulation dead cycle, the application provides a simulation debugging method, and the dead cycle code segments are determined from the code segments to be simulated through a preset detection mechanism, so that the efficiency of debugging simulation dead cycle can be improved.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a flowchart of a simulation debugging method provided in an embodiment of the present application, and as shown in fig. 1, the method includes:
101. and determining the code to be debugged.
In the embodiment of the application, a code to be debugged, which needs to be simulated, is determined from a source code file, and the code to be debugged may be the source code file or a certain code region in the source code file.
102. Dividing the code to be debugged into a plurality of code segments according to the set number, and determining a simulation time list and simulation time corresponding to each code segment.
In this step, the simulation time list includes a plurality of simulation times and information of the code fragments to be simulated at each simulation time, and the simulation times are used for indicating the execution time of the corresponding code fragments.
It should be noted that before step 102 is executed, a simulation time list of the code to be debugged needs to be established in advance, for example, as shown in fig. 2, the simulation time list includes a plurality of simulation times and information of code fragments to be simulated at each simulation time.
In the embodiment of the application, in order to improve the detection efficiency of the endless loop code segments, the code to be debugged can be divided into a plurality of code segments according to the set number. For example, the set number includes 1000. The code to be debugged may be divided into 1000 code fragments. In the present application, for example, a code to be debugged is divided into three code segments a, b, and c, and from the simulation time list in fig. 2, it can be determined that the simulation time of the code segment a is 00:00: at time 01, the simulation time of code segment b is 00:00: at time 02, the simulation time of code segment a is 00:00: and (03).
103. And determining a code segment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code segment to be simulated.
In this step, the default one-time simulation debugging process is from 00:00: and (5) starting simulation at the time 00, continuously acquiring the next code segment according to the simulation time list to perform simulation verification along with the increase of the simulation time, and if the dead-cycle code occurs, causing the simulator to repeatedly simulate the same code segment.
In the embodiment of the present application, for example, a single-simulation debugging process is performed from 00:00: starting simulation at the time 00, and with the increase of simulation time, when the simulation time is 00:00: and 01, determining the code segment to be simulated as a code segment a according to the simulation time list, performing simulation verification on the code segment a, and so on, if the code to be debugged has no endless loop code segment, sequentially executing each code segment according to the simulation time list until the whole code to be debugged is completely executed. If a code fragment is dead-cycled, the simulation time will continue to increase, but the simulator will repeatedly execute the code fragment. For example, with code segment a as the dead loop code segment, when the simulation time is 00:00: 01, carrying out simulation verification on the code segment a, wherein the simulation time is continuously increased to become 00:00: 02, according to the simulation time list, the code segment b should be subjected to simulation verification at this moment, and when a dead loop occurs due to the code segment a, the result is that at 00:00: 02, the code segment a is still verified by emulation. Therefore, the present application aims to find and debug the dead cycle code segments, so that the simulator can sequentially execute each code segment according to the simulation time list until the whole code to be debugged is completely executed.
104. And determining the endless loop code segment from the code segments to be simulated according to a preset detection mechanism.
In this step, the detection mechanism can be set according to the requirement, and the detection mechanism can include various types.
In the embodiment of the present application, for example, the preset detection mechanism includes detecting whether the same code segment is being executed repeatedly by the emulator, or whether the same code segment is being output by the result log file, and the like. Specifically, on the premise that a code segment which is subjected to simulation verification is printed in a result log file, if the same code segment is repeatedly printed in the result log file, the code segment is determined as a dead cycle code segment; or if the simulation verification times of a code segment are detected to exceed the preset times, determining the code segment as a dead loop code segment.
In addition, other detection mechanisms may be set, and the above detection mechanism is only one example. This is not a limitation of the present application.
105. And acquiring the positioning information of the endless loop code segment, and inquiring and debugging the endless loop code segment based on the positioning information.
In this step, the positioning information of the dead loop code segment may include the simulation time of the dead loop code segment and the code range information corresponding to the dead loop code segment. The simulation time is the time for determining the endless loop code segment from the code segment to be simulated according to a preset detection mechanism, and the code range information is the information such as the number of bytes and bytes contained in the endless loop code segment.
In the embodiment of the application, when a loop code segment is determined, simulation time of the loop code segment and code range information corresponding to the code segment need to be acquired, and the simulation time and the code range information are used as positioning information of the loop code segment and are redirected to a detection result log file, so that the code segment is inquired and debugged subsequently according to the positioning information of the loop code segment in the detection result log file, and the problem of loop death in simulation debugging is solved.
Further, the code snippet may be quickly queried in the code region based on location information of the code snippet. The method for querying the location code may refer to the current code location technology, which is not described in this application.
In the embodiment of the application, the problem of simulation endless loop can be solved by debugging the code segments, the endless loop code segments can be quickly detected by a preset detection mechanism, and compared with a single step debugging mode, the efficiency of detecting the endless loop code segments and the efficiency of solving the simulation endless loop are improved by the simulation debugging mode.
Fig. 3 is a flowchart of a simulation debugging method provided in an embodiment of the present application, and as shown in fig. 3, the method includes:
201. and determining the code to be debugged.
In the embodiment of the present application, as a possible implementation manner, after a source code file is compiled and simulated by a VCS command, a code to be debugged, which needs to be simulated, is determined from the source code file, where the code to be debugged may be the source code file or a certain code region in the source code file.
Among them, the VCS command may include: sv + v2k + VCS + loopreport + [ threshold ], where the VCS command indicates that a VCS simulator is used to compile and simulate a test sv source code file, and the simulation options are "v 2 k" (simulation option in VCS simulator) and "vcslocurrentreport" (simulation option in VCS simulator) for enabling the simulator to execute a dead loop debugging function, that is, determining a dead loop code segment from the code segments to be simulated according to a preset detection mechanism.
202. Dividing the code to be debugged into a plurality of code segments according to the set number, and determining a simulation time list and simulation time corresponding to each code segment.
In the embodiment of the present application, the execution process of the step may refer to the step 102, which is not described again in the embodiment of the present application.
203. And determining a code segment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code segment to be simulated.
In the embodiment of the present application, the execution process of this step may refer to step 103, which is not described again in the embodiment of the present application.
It should be noted that, as a possible implementation scheme, in the execution process of step 203, the code segments to be determined to be simulated may be combined into a simulation scheduling queue, and simulation verification is performed on the simulation scheduling queue.
204. And printing the code segment which is subjected to the simulation verification in the result log file.
In the embodiment of the application, the code segment which is subjected to the simulation verification is printed in the result log file, so that the execution result of the simulation verification is conveniently recorded.
205. And determining the endless loop code segment from the code segments to be simulated according to a preset detection mechanism.
In this step, the detection mechanism can be set according to the requirement, and the detection mechanism can include various types.
In this embodiment of the present application, as a possible implementation scheme, step 205 may include: and if the same code segment is detected to be repeatedly printed in the result log file, determining the code segment as a dead cycle code segment.
In this implementation, each time a simulation verification is performed on a code segment in the simulation queue, the code segment is printed in a result log file, and a simulation of the next code segment is performed according to a list of timestamp simulation times. And if the next code segment is subjected to simulation verification and the last code segment is still printed in a result log, determining the last code segment as a dead loop code segment.
As another possible implementation, step 205 may include: and if the simulation verification times of a code segment detected in the result log file exceed the preset times, determining the code segment as a dead loop code segment.
In this implementation, similar to the above implementation, each time a simulation verification is performed on a code fragment in the simulation queue, the code fragment is printed in a result log file, and a next code fragment is simulated according to a list of time stamp simulation times. And if the next code segment is subjected to simulation verification, the last code segment is still printed in a result log, and the number of times of printing the last code segment exceeds the preset number of times, determining the last code segment as a dead cycle code segment.
As another possible implementation, step 205 may include: and if the simulation time is detected to be continuously increased and the simulation waveform is not increased, determining the code segment currently subjected to simulation verification as the dead loop code segment.
The two implementation schemes are different from the two implementation schemes, and both the two implementation schemes detect whether the code segment to be simulated is the endless loop code segment by checking the result log file.
It should be noted that, each time a new code segment is executed, corresponding waveform information is added to the waveform file, and if the simulator repeatedly executes a certain code segment, the waveform file does not add new waveform information any more, and based on that, if it is detected that the simulation time is continuously increased but the simulation waveform is not increased, the code segment currently undergoing simulation verification is determined to be a dead-cycle code segment.
For example, as shown in fig. 4, when simulation time 1 in fig. 4 indicates that a simulator performs simulation verification, and when a dead-loop code segment is a code segment b, as the simulation time increases to 00:00:03, simulation verification should be performed on the code segment c according to the simulation time list, and when a dead loop occurs in the code segment b, the simulator may continuously perform simulation verification on the code segment b, so that the simulation time continuously increases, but the simulation waveform does not increase any more.
206. And taking the code range information and the simulation time corresponding to the endless loop code segment as the positioning information of the code segment, and redirecting to the result log file.
In this step, the simulation time is the time for determining the endless loop code segment from the code segments to be simulated according to a preset detection mechanism. The code range information is information such as bytes and the number of bytes included in the endless loop code segment.
In the embodiment of the application, the endless loop code segment determined from the code segment to be simulated needs to print the positioning information of the endless loop code segment in the result log file, so that the endless loop code segment can be conveniently inquired and debugged subsequently.
207. And acquiring the positioning information of the endless loop code segment, and inquiring and debugging the endless loop code segment based on the positioning information.
In the embodiment of the present application, the step 105 of the above embodiment may be referred to as an execution process of the step, which is not described in detail herein.
Fig. 5 is a schematic structural diagram of an emulation debugging apparatus according to an embodiment of the present application, and as shown in fig. 5, the apparatus includes:
a determining module 31, configured to determine a code to be debugged;
the processing module 32 is configured to divide the code to be debugged into a plurality of code segments according to a set number, and determine a simulation time list and simulation time corresponding to each code segment, where the simulation time list includes a plurality of simulation times and code segments to be simulated in each simulation time, and the simulation time is used to indicate execution time of the corresponding code segment;
the simulation module 33 is configured to determine a code segment to be simulated according to the current simulation time and the simulation time list, and perform simulation verification on the code segment to be simulated;
the detection module 34 is configured to determine a loop code segment from the code segments to be simulated according to a preset detection mechanism;
and the debugging module 35 is configured to acquire positioning information of the endless loop code segment, and query and debug the endless loop code segment based on the positioning information.
In this embodiment of the present application, optionally, the apparatus further includes: a print module 36.
And a printing module 36 for printing the code segment which has completed the simulation verification in the result log file.
In this embodiment of the application, optionally, the device detecting module 34 is specifically configured to determine the code segment as a dead loop code segment if it is detected that the same code segment is repeatedly printed in the result log file.
In this embodiment of the application, optionally, the device detecting module 34 is specifically configured to determine a code segment as a dead loop code segment if the simulation verification frequency of the code segment detected in the result log file exceeds a preset frequency.
In this embodiment of the application, optionally, the device detection module 34 is specifically configured to determine, if it is detected that the simulation time is continuously increased but the simulation waveform is not increased, the code segment currently undergoing simulation verification as the dead loop code segment.
In this embodiment of the application, optionally, the device simulation module 33 is specifically configured to combine the determined code segments to be simulated into a simulation scheduling queue, and perform simulation verification on the simulation scheduling queue.
In this embodiment of the application, optionally, the device determination module 31 is specifically configured to compile and simulate a source code file through a VCS command, and obtain a code to be debugged.
In this embodiment of the application, optionally, the device printing module 36 is specifically configured to take the code range information and the simulation time corresponding to the endless loop code segment as the positioning information of the code segment, and redirect the code range information and the simulation time to the result log file.
The simulation debugging apparatus shown in fig. 5 may execute the simulation debugging method shown in the embodiment shown in fig. 3, and the implementation principle and the technical effect are not repeated. The specific manner in which each module and unit of the emulation debugging apparatus in the above embodiments perform operations has been described in detail in the embodiments related to the method, and will not be elaborated herein.
In one possible design, the simulation debugging apparatus of the embodiment shown in fig. 5 may be implemented as a computing device, and in practical applications, as shown in fig. 6, the computing device may include a storage component 401 and a processing component 402;
one or more computer instructions are stored in the storage component 401, wherein the one or more computer instructions are called and executed by the processing component 402 to implement the emulation debugging method according to the embodiment of fig. 1 or fig. 2.
Among other things, the processing component 402 may include one or more processors to execute computer instructions to perform all or some of the steps of the methods described above. Of course, the processing elements may also be implemented as one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components configured to perform the emulation debugging method described in the embodiments of fig. 1 or 2.
The storage component 401 is configured to store various types of data to support operations at the terminal. The memory components may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a computer, the simulation debugging method of the embodiment shown in fig. 1 or fig. 2 may be implemented.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (11)
1. A simulation debugging method is characterized by comprising the following steps:
determining a code to be debugged;
dividing the code to be debugged into a plurality of code segments according to a set number, and determining a simulation time list and simulation time corresponding to each code segment, wherein the simulation time list comprises a plurality of simulation times and code segment information to be simulated in each simulation time, and the simulation time is used for indicating the execution time of the corresponding code segment;
determining a code segment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code segment to be simulated;
determining a dead cycle code segment from the code segments to be simulated according to a preset detection mechanism;
and acquiring the positioning information of the endless loop code segment, and inquiring and debugging the endless loop code segment based on the positioning information.
2. The method of claim 1, wherein after determining the code segment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code segment to be simulated, the method further comprises:
and printing the code segment which is subjected to the simulation verification in the result log file.
3. The method of claim 2, wherein the determining the dead loop code segment from the code segments to be simulated according to a predetermined detection mechanism comprises:
and if the same code segment is detected to be repeatedly printed in the result log file, determining the code segment as a dead cycle code segment.
4. The method of claim 2, wherein the determining the dead loop code segment from the code segments to be simulated according to a predetermined detection mechanism comprises:
and if the simulation verification times of a code segment detected in the result log file exceed the preset times, determining the code segment as a dead loop code segment.
5. The method of claim 1, wherein the determining the dead loop code segment from the code segments to be simulated according to a predetermined detection mechanism comprises:
and if the simulation time is detected to be continuously increased and the simulation waveform is not increased, determining the code segment currently subjected to simulation verification as the dead loop code segment.
6. The method of claim 1, wherein the determining the code fragment to be simulated according to the current simulation time and the simulation time list, and performing simulation verification on the code fragment to be simulated comprises:
and forming a simulation scheduling queue by the determined code segments to be simulated, and performing simulation verification on the simulation scheduling queue.
7. The method of claim 1, wherein determining code to be debugged comprises:
and compiling and simulating the source code file through a VCS command to acquire a code to be debugged.
8. The method of claim 1, prior to said obtaining the location information of the endless loop code segment, comprising:
and taking the code range information and the simulation time corresponding to the endless loop code segment as the positioning information of the code segment, and redirecting to the result log file.
9. An emulation debugging apparatus, comprising:
the determining module is used for determining a code to be debugged;
the processing module is used for dividing the code to be debugged into a plurality of code segments according to a set number, and determining a simulation time list and simulation time corresponding to each code segment, wherein the simulation time list comprises a plurality of simulation times and the code segments to be simulated in each simulation time, and the simulation times are used for indicating the execution time of the corresponding code segments;
the simulation module is used for determining a code segment to be simulated according to the current simulation time and the simulation time list and carrying out simulation verification on the code segment to be simulated;
the detection module is used for determining a dead cycle code segment from the code segments to be simulated according to a preset detection mechanism;
and the debugging module is used for acquiring the positioning information of the endless loop code segment, and inquiring and debugging the endless loop code segment based on the positioning information.
10. A computing device comprising a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions to invoke emulation by the processing component to implement the emulated debugging method of any of claims 1-8.
11. A computer storage medium, characterized in that a computer program is stored, which, when simulated by a computer, implements the simulation debugging method according to any one of claims 1 to 8.
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