CN113782528A - Semiconductor device, integrated circuit product and manufacturing method - Google Patents

Semiconductor device, integrated circuit product and manufacturing method Download PDF

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CN113782528A
CN113782528A CN202111330860.8A CN202111330860A CN113782528A CN 113782528 A CN113782528 A CN 113782528A CN 202111330860 A CN202111330860 A CN 202111330860A CN 113782528 A CN113782528 A CN 113782528A
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region
doped region
type
substrate
source
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CN113782528B (en
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赵东艳
成睿琦
赵扬
陈燕宁
董广智
王立城
付振
王树龙
罗宗兰
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State Grid Corp of China SGCC
Xidian University
State Grid Information and Telecommunication Co Ltd
Beijing Smartchip Microelectronics Technology Co Ltd
Changzhou Power Supply Co of State Grid Jiangsu Electric Power Co Ltd
Beijing Core Kejian Technology Co Ltd
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State Grid Corp of China SGCC
Xidian University
State Grid Information and Telecommunication Co Ltd
Beijing Smartchip Microelectronics Technology Co Ltd
Changzhou Power Supply Co of State Grid Jiangsu Electric Power Co Ltd
Beijing Core Kejian Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Power Engineering (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor device, an integrated circuit product and a manufacturing method, and belongs to the technical field of semiconductor devices. The semiconductor device includes: a substrate; the first doping region is formed on the substrate and is a doping region of a source region and a drain region of the first MOS; the second doped region is formed in the substrate, the distance between the second doped region and the source region is smaller than the distance between the second doped region and the drain region, and the conductivity types of the second doped region and the source region are opposite; an interconnect layer having conductivity in contact with the second doped region and the source region. The invention can provide the anti-electromagnetic interference capability for the semiconductor device.

Description

Semiconductor device, integrated circuit product and manufacturing method
Technical Field
The present invention relates to the field of semiconductor device technology, and in particular to a semiconductor device, a method of manufacturing a semiconductor device, an inverter, a layout structure, an electronic device, an integrated circuit product, and a computer-readable storage medium.
Background
With the continuous reduction of feature sizes of integrated circuits and corresponding various semiconductor devices, electromagnetic damage effects are easily generated in the reduced devices, and the devices are often damaged actually after the electromagnetic damage effects occur.
Currently, some research is being conducted in the industry regarding the damage effect of PN junctions (p-n junctions) and Bipolar Junction Transistors (BJTs). Research on damage of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, abbreviated as MOS) device is a research on Electrostatic discharge (ESD), but research on electromagnetic damage of a MOS device has not been satisfactorily progressed, particularly on electromagnetic damage of a CMOS (Complementary Metal-Oxide-Semiconductor) device, such as a CMOS inverter. In practical use environments, semiconductor devices are easily exposed to electromagnetic interference, and under the electromagnetic interference, some semiconductor devices may be damaged and failed, and further, the integrated circuit or other equipment may be systematically failed. Therefore, the research on the electromagnetic damage effect is important for the electromagnetic protection of integrated circuits and devices, and the electromagnetic interference protection capability of semiconductor devices needs to be provided.
Disclosure of Invention
The invention aims to provide a semiconductor device, an integrated circuit product and a manufacturing method, which can avoid electromagnetic damage caused by electromagnetic interference on the semiconductor device and further break through the bottleneck of electromagnetic interference resistance of the semiconductor device and the product under the same process level.
In order to achieve the above object, an embodiment of the present invention provides a semiconductor device including:
a substrate;
the first doping region is formed on the substrate and is a doping region of a source region and a drain region of the first MOS;
the second doped region is formed in the substrate, the distance between the second doped region and the source region is smaller than the distance between the second doped region and the drain region, and the conductivity types of the second doped region and the source region are opposite;
an interconnect layer having conductivity in contact with the second doped region and the source region.
Specifically, the semiconductor device further includes:
and the third doped region is formed on the substrate, and the distance between the third doped region and the source region is greater than that between the second doped region and the source region.
Specifically, a boundary of the second doped region is adjacent to a boundary of the first doped region, and the boundary of the first doped region is adjacent to the source region.
Specifically, the third doped region is spaced from a boundary of the first doped region, and the boundary of the first doped region is a boundary adjacent to the drain region.
Specifically, the contact of the interconnection layer with the second doped region and the source region is an ohmic contact;
the interconnect layer includes a source voltage contact end of the third doped region.
Specifically, the interconnect layer includes a conductor segment;
the conductor segment is in contact with the second doped region and the source region, and the conductor segment is used for forming an equivalent circuit connection;
the equivalent circuit connection is the connection of the source region, through the conductor segment, with the second doped region, the body, and the source voltage contact.
Specifically, the base is a substrate, and the semiconductor device further includes:
the well region is formed on the substrate;
the fourth doped region is formed in the well region and is a doped region of a source region and a drain region of the second MOS;
the second MOS is PMOS, and the first MOS is NMOS.
Specifically, the substrate is a well region of the substrate, and the semiconductor device further includes:
the fourth doped region is formed on the substrate and is a doped region of a source region and a drain region of the second MOS;
the second MOS is PMOS, and the first MOS is NMOS.
The embodiment of the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
forming a first doped region of a substrate, wherein the first doped region is a doped region of a source region and a drain region of a first MOS;
forming a second doped region of the substrate, wherein the distance between the second doped region and the source region is smaller than the distance between the second doped region and the drain region, and the conductivity type of the second doped region is opposite to that of the source region;
forming a conductive interconnect layer in contact with the second doped region and the source region.
Specifically, after the forming the first doped region of the base body and before the forming the conductive interconnection layer, the manufacturing method further includes:
and forming a third doped region of the substrate, wherein the distance between the third doped region and the source region is greater than the distance between the second doped region and the source region.
Specifically, the second doping region of the substrate is formed, wherein,
the boundary of the second doped region is adjacent to the boundary of the first doped region, which is the boundary adjacent to the source region.
Specifically, the third doped region of the substrate is formed, wherein,
the third doped region is spaced apart from a boundary of the first doped region, which is a boundary adjacent to the drain region.
Specifically, the forming of the conductive interconnection layer includes:
forming ohmic contacts of the second doped region and the source region;
forming a source voltage contact terminal of the third doped region.
Specifically, the forming of the ohmic contact between the second doped region and the source region includes:
forming a conductor segment in contact with the second doped region and the source region, the conductor segment for forming an equivalent circuit connection;
the equivalent circuit connection is the connection of the source region, through the conductor segment, with the second doped region, the body, and the source voltage contact.
Specifically, the substrate is a substrate, and before the forming of the conductive interconnection layer, the manufacturing method further includes:
forming a well region of the substrate;
forming a fourth doped region in the well region, the fourth doped region being a doped region of a source region and a drain region of the second MOS,
the second MOS is PMOS, and the first MOS is NMOS.
Specifically, the substrate is a well region of a substrate, and before the forming of the conductive interconnection layer, the manufacturing method further includes:
forming a fourth doped region in the substrate, the fourth doped region being a doped region of a source region and a drain region of a second MOS,
the second MOS is PMOS, and the first MOS is NMOS.
An embodiment of the present invention provides an inverter, including:
a P-type substrate;
the first N-type doped region is formed in the P-type substrate and is used for forming a doped region of a source region and a doped region of a drain region of the NMOS;
the first P-type doped region is formed on the P-type substrate;
the distance between the first P-type doped region and the source region is smaller than the distance between the first P-type doped region and the drain region;
an interconnect layer having conductivity in contact with the first P-type doped region and the source region.
Specifically, the inverter further includes:
and the second P-type doped region is formed on the P-type substrate, and the distance between the second P-type doped region and the source region is greater than the distance between the first P-type doped region and the source region.
Specifically, the contact of the interconnection layer with the first P-type doped region and the source region is an ohmic contact;
and the interconnection layer is provided with a source voltage contact end of the second P-type doped region.
Specifically, the interconnect layer includes:
a conductor segment in contact with the first P-type doped region and the source region, the conductor segment for forming an equivalent circuit connection;
the equivalent circuit is connected to the source region and is connected to the first P-type doped region, the P-type substrate and the source voltage contact terminal through the conductor segment.
Specifically, the inverter further includes:
the N-type well region is formed on the P-type substrate;
the third P-type doped region is formed in the N-type well region and is used for forming doped regions of a source region and a drain region of the PMOS;
the second N-type doped region is formed in the N-type well region;
the interconnection layer is in contact with the second N-type doped region and the source electrode of the PMOS;
and the interconnection layer is provided with a drain voltage contact end of the second N-type doped region.
Specifically, the inverter further includes:
the polysilicon common gate is formed on the P-type substrate and the N-type well region and is used for forming the grid electrodes of the NMOS and the PMOS and the input end of the inverter;
the interconnection layer is in contact with the third P-type doped region and the first N-type doped region and is used for forming connection of the drain electrode of the NMOS and the drain electrode of the PMOS and an output end of the inverter.
An embodiment of the present invention provides a layout structure, where the layout structure includes:
a P-type substrate;
the first N-type active region is formed on the P-type substrate and used for forming a source region and a drain region of an NMOS;
the first P-type active region is formed on the P-type substrate;
the distance between the first P type active region and the source region is smaller than the distance between the first P type active region and the drain region;
an interconnect layer having conductivity in contact with the first P-type active region and the active region.
In another aspect, an embodiment of the present invention provides an electronic device, including:
at least one processor;
a memory coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the at least one processor implements the aforementioned method by executing the instructions stored by the memory.
In yet another aspect, embodiments of the present invention provide an integrated circuit product including the aforementioned semiconductor device, or
The integrated circuit product comprises the inverter described above, or
The integrated circuit product comprises the layout structure.
In yet another aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the computer to perform the foregoing method.
In the invention, the doped region (such as the second doped region) with opposite conductive types is formed near the source region of the MOS of the semiconductor device, and the source region and the doped region formed nearby are in conductive contact, when electromagnetic interference occurs, the electromagnetic interference pulse is injected into the source region of the MOS, and almost simultaneously the electromagnetic interference pulse is also injected into the doped region formed nearby, so that the potential of a substrate (such as a substrate or a well region) nearby the source region is changed along with the potential of the source region injected with the electromagnetic interference pulse, the bias voltage of a depletion layer of the source region and the substrate is obviously reduced, and the electromagnetic damage effect caused by the injection of a large number of carriers into the substrate is avoided. In addition, the invention does not need additional process steps and process conditions, and breaks through the bottleneck of anti-electromagnetic interference of semiconductor devices and products under the same process level.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a schematic cross-sectional diagram of an exemplary inverter according to an embodiment of the present invention;
FIG. 2 is a cross-sectional schematic diagram of an exemplary inverter according to an embodiment of the present invention;
FIG. 3 is a cross-sectional schematic diagram of an exemplary inverter according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of important steps of an exemplary method of manufacture of an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a conventional inverter;
FIG. 6 is a cross-sectional schematic diagram of an exemplary inverter according to an embodiment of the present invention;
FIG. 7 is a schematic diagram showing a current comparison between an inverter according to an embodiment of the present invention and a conventional inverter under electromagnetic interference;
FIG. 8 is a graph showing a comparison of peak temperatures of an inverter according to an embodiment of the present invention and a conventional inverter under electromagnetic interference;
fig. 9 is a schematic diagram of the arrangement positions of the substrate and the well region in an exemplary layout structure according to the embodiment of the invention;
fig. 10 is a schematic diagram of an arrangement position of an active region in an exemplary layout structure according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a position of a polysilicon common gate arrangement in an exemplary layout structure according to an embodiment of the present invention;
fig. 12 is a schematic diagram of an arrangement position of a P-type injection mask region in an exemplary layout structure according to an embodiment of the present invention;
fig. 13 is a schematic diagram of an arrangement position of an N-type injection mask region in an exemplary layout structure according to an embodiment of the present invention;
FIG. 14 is a schematic diagram illustrating a layout structure of contact holes according to an exemplary layout structure of the present invention;
fig. 15 is a schematic diagram of an arrangement position of a metal layer in an exemplary layout structure according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
In order to analyze the interference of the device in the electromagnetic environment, a sensitive position (such as a source region) in the device under the action of strong electromagnetic pulse can be found, and the internal mechanism of the device is analyzed to reinforce the device.
The substrate of the semiconductor device is doped, a plurality of parasitic transistors are easily formed by the substrate and each doped region, substrate current is generated in the process of recombination of electrons and holes in the semiconductor device, the substrate current passes through the substrate resistor, and at the moment, voltage drop is detected at two ends of the substrate resistor. When the body current (for example, the source region is affected by electromagnetic interference) or the body resistance is large, the voltage drop across the body resistance is large, so that the emitter junction of the parasitic transistor is in a forward biased state, the parasitic transistor is turned on, the current flows through the collector of the parasitic transistor, and when the current gain of the parasitic transistor is large, continuous positive feedback between the parasitic transistors easily occurs, so that a large-current flow path is generated from the MOS drain voltage end to the source voltage end, heat accumulation is formed inside the integrated circuit or in the device, and finally the circuit or the device is damaged or burnt. Embodiments of the present invention will provide a solution to the above problems.
Example 1
An embodiment of the present invention provides a semiconductor device, which may include:
a substrate; the first doping region is formed on the substrate and is a doping region of a source region and a drain region of the first MOS; the second doped region is formed in the substrate, the distance between the second doped region and the source region is smaller than the distance between the second doped region and the drain region, and the conductivity types of the second doped region and the source region are opposite; an interconnect layer having conductivity in contact with the second doped region and the source region.
In some implementations, the base is doped, for example, the base includes a P-type or N-type Substrate (sub) or a Well region (Well) formed in the Substrate. The first doped region (doped region) is heavily doped with respect to the substrate, and a conductivity type of the first doped region may be opposite to a conductivity type of the substrate; it should be noted that doping is to add a dopant to an object to be doped, and the doping process may include a Diffusion (Diffusion) process and/or an Ion implantation (Ion implantation) process; the dopant includes boron (B), indium (In) and other P-type dopants, In which case the holes are the majority carriers of the object to be doped, and the conductivity type is correspondingly P-type; the dopant also includes N-type dopants such As arsenic (As), phosphorus (P), etc., when electrons are the majority carriers of the object to be doped, the conductivity type is correspondingly N-type; the doped region is a region containing dopant ions of a specific concentration/concentration profile; the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for limiting the quantity or order; the source region is a region on the substrate corresponding to the source of the MOS, the drain region is a region on the substrate corresponding to the drain of the MOS, the (doped region of the) source region is also a doped region corresponding to the source, and the (doped region of the) drain region is also a doped region corresponding to the drain.
In a first example, the substrate may be a P-type substrate (P-sub), the first doped region may be two N + type doped regions (abbreviated as N + region; "+" represents heavily doped, with a high doping concentration, and "-" represents lightly doped, with a low doping concentration, for example only, the doping concentrations may be selected to be different based on the product of the specific application, such as P-/N-, P +/N +, P + +/N + +, etc., and in some cases, the substrate may be lightly doped), and the two N + regions may be doped regions of the source region and the drain region of the first MOS, respectively. In a second example, the body may be a P-well region (P-well) of an N-type substrate (N-sub), and the first doped region may be two N + doped regions, which may be a doped region of a source region and a doped region of a drain region of the first MOS, respectively. In a third example, the substrate may be an N-well (N-well) of a P-type substrate, and the first doped region may be two P + type doped regions (abbreviated as P + regions), which may be doped regions of a source region and a drain region of the first MOS, respectively. It is understood that the above examples are not limited to implementations, and may be implemented in combination with the above examples according to different processes and product requirements, for example, in a Twin-well (Twin-well) process, a Triple-well (Triple-well) process, an array device product, and the like.
The third doped region is formed on the substrate, and the distance between the third doped region and the source region of the first MOS is larger than the distance between the second doped region and the source region of the first MOS. In the first example, the second doped region may be a P + region, the P + region may be closely attached to an N + region corresponding to the source region, i.e., a boundary between the P + region and the N + region may be adjacent, and furthermore, the P-type substrate may be formed with an N-type well region before the first doped region is formed, the P + region and the N-type well region have a spacing distance; the third doped region may also be a P + region. In some cases, the third doped region, the first doped region and the second doped region are aligned in the positioning direction, the second doped region is a right P + region (with respect to the first doped region, or with respect to a center line of a rectangular region if the first doped region is the rectangular region), the third doped region is a left P + region, and may be respectively a left P + region, two N + regions (the N + region near a left boundary of the first doped region may be a doped region of the drain region, the N + region near a right boundary thereof may be a doped region of the source region, the left boundary and the right boundary may be two boundary lines of the aforementioned rectangular region with respect to the center line, in which case, the boundary adjacent to the source region may be the right boundary, the boundary adjacent to the drain region may be the left boundary), and the right P + region, the left P + region is spaced apart from the N + region corresponding to the drain region of the first MOS transistor, the right P + region is adjacent to the N + region corresponding to the source region of the first MOS. It is noted that the second doped region and the third doped region may be completed in the doping process step without additional process conditions or additional process steps. In the foregoing second example and third example, the second doped region may be a P + region and an N + region, respectively, and the third doped region may be a P + region and an N + region, respectively. Wherein, abutting or abutting is the relative distance between specified boundaries (e.g., boundary lines) of the regions that just touch, or nearly touch, or are positioned at or below a specified distance. The spacing or separation distance is the relative distance located between the designated boundaries of the regions that is greater than or equal to the designated distance. Other examples may be referred to herein and are not described in detail.
The material of the interconnection layer may include metal such as aluminum (Al), copper (Cu), or alloy, or other conductive material containing metal elements, and the interconnection layer may be formed on the substrate by a deposition method. The interconnection layer may be in direct Contact with the second doped region and the source region, and the formed Contact may be an Ohmic Contact (Ohmic Contact). In particular, the interconnect layer may further comprise a conductor segment, which may be adapted to the product and may be in contact with other conductor portions in the interconnect layer, for example, the conductor segment may be connected to the source voltage via other conductor portions in the interconnect layer, and the other conductor portions and the conductor segment may be integrated or formed separately, which may be adapted to different requirements. The conductor section may be formed above the second doped region and the source region of the first MOS, and may in particular be in direct contact with the second doped region and the source region of the first MOS, which conductor section may serve to form an equivalent circuit connection.
On the basis of the foregoing first example, the third doped region is a substrate terminal region (abbreviated as sub-terminal), the interconnection layer may further include a source voltage contact terminal of the substrate terminal region, and at this time, the equivalent circuit is connected to an N + region corresponding to the source region of the first MOS, and the P-type substrate may provide a substrate resistance in the equivalent circuit connection through a conductor segment, that is, when the semiconductor device is subjected to electromagnetic interference, an electromagnetic pulse is injected into the source region, and is also almost simultaneously injected into the right P + region, the depletion layer bias voltage is significantly reduced, electrons injected into the substrate are significantly suppressed, the substrate resistance of the semiconductor device no longer provides a voltage drop for the parasitic transistor, and the substrate resistance in the equivalent circuit connection is separated from an equivalent amplification circuit of the parasitic transistor.
In the exemplary semiconductor device of fig. 1, there is a P-type substrate P-sub and an N-type well region N-well, a doped region and a gate of a PMOS (P-type MOS) may be formed in the dotted line frame Y1, a gate G is formed on a P-sub of a P-type substrate, two N + regions formed by doping are formed in the P-type substrate near the gate G, which are a drain region corresponding to the drain D of an NMOS (N-type MOS, which may be a first MOS) and a source region corresponding to the source S of the NMOS, respectively, a P + region (i.e., a right P + region) and another P + region (i.e., a left P + region) serving as a substrate contact region sub tap are further doped next to the source region, the left P + region has a distance from the drain region, and a source voltage contact terminal in the interconnection layer is connected to a source voltage VSS(ii) a A conductor segment M is formed on the source region and the closely attached P + region, the conductor segment M can be a metal wire or a metal sheet, etc. (the shape of the conductor segment is not limited), at this time, an equivalent circuit connection is formed, the connection is formed by the source region and the closely attached P + region, the P-type substrate P-sub and the source voltage contact end through the conductor segment M, and the substrate resistance R of the P-type substrate P-sub can be seenSSeparate from the amplification circuit of the parasitic transistor in the semiconductor device. Wherein, the shaded area OX. may be an oxide in the present embodiment; in some cases, the substrate of the embodiment of the present invention may be a portion of a substrate of a semiconductor device, such as an isolated process semiconductor device with multiple substrates. The cross-sectional structure diagram of the embodiment of the present invention may have structures, connections, contacts, and the like not shown, for example, the conductor segment M is further connected to the source voltage, or connected to the source voltage through other conductor portions in the interconnection layer.
Based on the foregoing second example, the third doped region is a junction region (well tap) of the P-well region, and the interconnection layer may further include a source voltage contact terminal of the P-well region, where the equivalent circuit is connected to an N + region corresponding to the source region of the first MOS, and the P-well region may provide a well region resistance in the equivalent circuit connection through the conductor segment and the connection formed by the right P + region, the P-well region, and the source voltage contact terminal.
In the exemplary semiconductor device of fig. 2, there are N-sub substrate and P-well, PMOS doped region and gate may be formed in the dashed box Y2 (for example, N-well may be formed during twin-well process), gate G is formed on P-well, and two N + regions formed by doping are formed in P-well near gate GA drain region corresponding to the drain D of the NMOS (N-type MOS, which may be the first MOS) and a source region corresponding to the source S of the NMOS, wherein a P + region (right P + region) and another P + region (left P + region) are formed by doping and close to the source region, the left P + region is spaced from the drain region, and a source voltage contact terminal in the interconnection layer is connected with a source voltage VSS(ii) a A conductor section M is formed on the source region and the closely attached P + region, the conductor section M can be a metal wire or a metal sheet, and the like, at the moment, an equivalent circuit connection is formed, the connection is formed by connecting the source region with the closely attached P + region, the P-well region P-well and the source voltage contact end through the conductor section M, and the well region resistance R of the P-well region P-well can be seenWSeparate from the amplification circuit of the parasitic transistor in the semiconductor device.
For some semiconductor device products, based on the foregoing third example, the third doped region is a connector region of the N-well region, and the interconnect layer may further include a drain voltage contact terminal of the N-well region, where the equivalent circuit connection is a P + region corresponding to the source region of the first MOS, and the N-well region may provide a well region resistance in the equivalent circuit connection through the conductor segment and the connection formed by the right N + region, the N-well region, and the drain voltage contact terminal.
In the exemplary semiconductor device of fig. 3, there are a P-type substrate P-sub and an N-type well region N-well, a doped region and a gate of an NMOS, etc. may be formed in a dashed-line box Y3, a gate G is formed on the N-type well region N-well, two P + regions formed by doping are formed in the N-well region N-well near the gate G, a drain region corresponding to a drain D of the PMOS and a source region corresponding to a source S of the PMOS, respectively, an N + region (i.e., a right N + region) and another N + region (i.e., a left N + region) serving as a well junction region tap are further formed by doping next to the source region, the left N + region is spaced apart from the drain region, and a drain voltage contact terminal in the interconnection layer is connected to a drain voltage V in the interconnection layerDD(ii) a A conductor section M is formed on the source region and the N + region which is tightly attached to the source region, the conductor section M can be a metal wire or a metal sheet, and at the moment, an equivalent circuit connection is formed, wherein the connection is formed by connecting the source region with the N + region, the N-well region N-well and the drain voltage contact end which are tightly attached to each other through the conductor section M, and the well region resistor R of the P-well region P-well can be seenWAnd the semiconductor deviceThe amplification circuits of the parasitic transistors are separated.
It is also noted that in the above examples, the conductor segments in the interconnect layer do not require additional process conditions and process steps, and the conductor segments are formed in process steps that can form the interconnect layer under the same process conditions.
In most cases, as in the previous example, the semiconductor device may include a plurality of MOSs formed on the substrate and the well region, respectively. In the first example, the P-type substrate has a well region formed therein, the well region has a fourth doped region formed therein, the fourth doped region is a doped region of a source region and a drain region of the second MOS, in which case the second MOS may be PMOS, the first MOS may be NMOS, in which case the N-type well region has a corresponding well region junction region (N + region), and the interconnection layer has a drain voltage contact terminal (to the drain voltage V) thereinDD). In the second example, the N-type substrate has a fourth doped region formed therein, the fourth doped region is a doped region of a source region and a drain region of a second MOS, in which case the second MOS may be a PMOS, the first MOS may be an NMOS, in which case the N-type substrate has a corresponding substrate contact region (N + region), and the interconnect layer has a drain voltage contact (a drain voltage V) thereinDD). In the third example, the P-type substrate has a fourth doped region formed therein, the fourth doped region is a doped region of a source region and a drain region of the second MOS, in which case the second MOS can be an NMOS, the first MOS can be a PMOS, in which case the P-type substrate has a corresponding substrate contact region (P + region), and the interconnection layer has a source voltage contact (connected to the source voltage V) thereinSS) And in some cases the second MOS may be formed in the manner of the first example described above, with corresponding equivalent circuit connections. It will be appreciated that both PMOS and NMOS have gates, which may be formed over doped regions of the well region and substrate corresponding to source and drain regions of the respective MOS, and in some cases, both gates may be common gates.
The embodiment of the invention forms equivalent circuit connection through the structure of the semiconductor device, separates the connection of the substrate resistor and the amplifying circuit of the parasitic transistor, eliminates the adverse effect of the amplifying circuit formed by the substrate resistor and the parasitic transistor on the semiconductor device, improves the bias voltage of a PN junction depletion layer between a source region and a substrate under the influence of electromagnetic interference pulse, avoids the damage caused by injecting a large number of current carriers into the substrate, does not need additional process steps and process conditions, and breaks through the bottleneck of electromagnetic interference resistance of the semiconductor device and products under the same process level.
Example 2
The embodiment of the present invention belongs to the same inventive concept as embodiment 1, and the embodiment of the present invention provides a method for manufacturing a semiconductor device, which may include:
forming a first doped region of a substrate, wherein the first doped region is a doped region of a source region and a drain region of a first MOS;
forming a second doped region of the substrate, wherein the distance between the second doped region and the source region is smaller than the distance between the second doped region and the drain region, and the conductivity type of the second doped region is opposite to that of the source region;
forming a conductive interconnect layer in contact with the second doped region and the source region.
In some implementations, the matrix, doped regions, and interconnect layer can be implemented with reference to example 1. Illustratively, the body may be a P-type substrate, an N-type well region is formed in the P-type substrate, the first doped region may be an N-type region, the first MOS may be an NMOS, the second doped region may be a P-type region, and the interconnect layer may be in direct contact with the second doped region and the source region. The doped region of the embodiments of the present invention is a region containing dopant ions with a specific concentration/concentration profile formed after a specific process step.
Some doped regions may be formed simultaneously or sequentially with respect to the sequence of steps for forming the doped regions. Illustratively, after the forming the first doped region of the base body and before the forming the conductive interconnect layer, the method of manufacturing further comprises: and forming a third doped region of the substrate, wherein the distance between the third doped region and the source region is greater than the distance between the second doped region and the source region. Wherein the third doped region may be a P-type region and may be used for a substrate connector region of a P-type substrate.
Further, a second doped region of the substrate is formed, wherein a boundary of the second doped region may beTo adjoin, in particular, a boundary of the first doped region adjacent to the source region. Forming a third doped region of the body, wherein the third doped region is spaced apart from a boundary of the first doped region (and adjacent to the drain region). Forming a conductive interconnect layer comprising: forming ohmic contacts of the second doped region and the source region; forming a source voltage contact (to source voltage V) of said third doped regionSS). Forming an ohmic contact to the second doped region and the source region, comprising: forming a conductor segment in contact with the second doped region and the source region, the conductor segment for forming an equivalent circuit connection; the equivalent circuit connection is the connection of the source region, through the conductor segment, with the second doped region, the body, and the source voltage contact.
And forming a fourth doped region in the N-type well region, wherein the fourth doped region is a doped region of a source region and a drain region of a second MOS, the fourth doped region can be a P-type region, the second MOS is a PMOS, and the first MOS is an NMOS. As mentioned above, in some cases, the substrate may also be a P-well of an N-type substrate, in which a fourth doped region is formed, the fourth doped region being a doped region of a source region and a drain region of a second MOS, the fourth doped region may be a P-type region, the second MOS is a PMOS, the first MOS is an NMOS, the N-well has a corresponding well junction region (N + region), and the interconnection layer has a drain voltage contact (a drain voltage V + region) in the interconnection layerDD）。
Based on the foregoing embodiments, in one exemplary method of manufacturing, as shown in fig. 4, a self-aligned process may be employed. The manufacturing method may include:
s1) forming an N-type well region in the P-type substrate through N-type ion implantation;
s2) after the N-type well region is formed, a plurality of active regions are obtained through the positioning of the field oxide layer;
s3), growing a gate oxide layer, and depositing to form a polysilicon gate bridged on the field oxide layer after the growth of the gate oxide layer is finished;
s4) forming an N-type doped region and a P-type doped region through an active region designated by a mask and ion implantation, wherein the N-type doped region comprises a first doped region in a P-type substrate and a well region joint region in an N-type well region, and the P-type doped region comprises a fourth doped region in the N-type well region, a second doped region and a third doped region in the P-type substrate;
s5) forming an interconnect layer including a source voltage contact terminal, a drain voltage contact terminal, and a conductor segment over the P-type substrate and the N-type well region.
Specifically, step S4), may include:
masking a designated active region, wherein the designated active region comprises an active region to be subjected to P-type ion implantation;
carrying out N-type ion implantation to form an N-type doped region;
masking a designated active region, wherein the designated active region comprises an active region which is subjected to N-type ion implantation;
and carrying out P-type ion implantation to form a P-type doped region.
It will be appreciated that the foregoing manufacturing method may further include other steps of etching, cleaning, baking, etc.
Example 3
The embodiment of the present invention belongs to the same inventive concept as embodiments 1 to 2, and provides an inverter, which is a CMOS inverter, and is also one of the semiconductor devices of the foregoing embodiment 1, and the CMOS inverter is an important basic unit in an integrated circuit. The inverter may include:
a P-type substrate;
the first N-type doped region is formed in the P-type substrate and is used for forming a doped region of a source region and a doped region of a drain region of the NMOS;
the first P-type doped region is formed on the P-type substrate;
the distance between the first P-type doped region and the source region is smaller than the distance between the first P-type doped region and the drain region;
an interconnect layer having conductivity in contact with the first P-type doped region and the source region.
In some implementations, the first N-type doped region can be an N + region, the first P-type doped region can be a P + region, and the interconnect layer can be in direct contact with the first P-type doped region and the source region.
Specifically, the inverter further includes:
and the second P-type doped region is formed on the P-type substrate, and the distance between the second P-type doped region and the source region is greater than the distance between the first P-type doped region and the source region. The second P-type doped region may be a P + region and may be a substrate junction region of a P-type substrate.
Specifically, the contact of the interconnection layer with the first P-type doped region and the source region is an ohmic contact; and the interconnection layer is provided with a source voltage contact end of the second P-type doped region.
Specifically, the interconnect layer includes:
a conductor segment in contact with the second doped region and the source region, the conductor segment for forming an equivalent circuit connection;
the equivalent circuit is connected to the source region and is connected to the first P-type doped region, the P-type substrate and the source voltage contact terminal through the conductor segment.
Specifically, the inverter further includes: the N-type well region is formed on the P-type substrate;
the third P-type doped region is formed in the N-type well region and is used for forming doped regions of a source region and a drain region of the PMOS; the second N-type doped region is formed in the N-type well region; the interconnection layer is in active contact with the second N-type doped region and the active region of the PMOS; and the interconnection layer is provided with a drain voltage contact end of the second N-type doped region. The third P-type doped region may be a P + region and the second N-type doped region may be a well junction region of the N-well region.
Specifically, the inverter further includes:
the polysilicon common gate is formed on the P-type substrate and the N-type well region and is used for forming the grid electrodes of the NMOS and the PMOS and the input end of the inverter;
the interconnection layer is in contact with the third P-type doped region and the first N-type doped region and is used for forming connection of the drain electrode of the NMOS and the drain electrode of the PMOS and an output end of the inverter.
For a conventional CMOS inverter, as shown in FIG. 5, the process of electron and hole recombinationWill generate a substrate current through the resistance R of the substrateSAt this time, at RSA voltage drop is detected across. When substrate current is either RSWhen larger, RSThe voltage drop across the transistor will be large, causing the (parasitic transistor, lateral BJT) Q to be large1Is in a forward biased state, and thus Q1On with its collector current flowing through (parasitic transistor, vertical BJT) Q2So that Q is2And is also turned on. When parasitic transistor Q1And Q2The positive feedback between the two parasitic transistors will continue when the result of the multiplication of the cascode current gain exceeds 1, and thus, at the drain voltage terminal VDDTo the source voltage terminal VSSThe current path of large current is generated to form latch-up effect, the static power consumption of the inverter during normal operation is very low, but the latch-up effect can rapidly increase the power consumption of the integrated circuit or the device, and meanwhile, heat accumulation is formed in the circuit or the device, and finally the circuit or the device is damaged or burnt.
The reduction of the resistance R is known from the basic formation conditions of the latch-up effect of the inverter described aboveSAnd RWReducing the current amplification factor beta of the parasitic triodeNPN、βPNPThe anti-latch capability can be effectively improved. Therefore, in the conventional inverter reinforcing scheme, the base width of the lateral parasitic triode is increased, namely the distance between the NMOS source region and drain region and the boundary of the trap is increased, so that the current gain of the parasitic transistor is reduced, the latch-up trigger voltage is improved, or pin holes for connecting an N trap to VDD and connecting a P type substrate to ground are distributed to reduce the equivalent resistance R of the substrate and the trap as much as possibleSAnd RWThe main focus is to reduce the impact of parasitic parameters related to triggering latch-up. In the embodiments of the present invention, parasitic parameters (such as substrate resistance R) can be reduced without adding additional process stepsSAnd well region resistance RW) The influence of the electromagnetic pulse can be avoided, and electrons injected into the substrate when the electromagnetic pulse is interfered, so that the aim of inhibiting the latch-up effect is fulfilled.
In a disclosed CMOS inverter of an embodiment of the present invention, as shown in fig. 6, the CMOS inverter includes:
the device comprises a P-type substrate P-sub, an N-type well region N-well formed in the P-type substrate P-sub;
the polysilicon common gate G is formed on a P-type substrate P-sub and an N-type well region N-well and is used for forming the grid electrodes of the NMOS and the PMOS and the input end of the inverter;
two N-type doped regions are formed in the P-type substrate P-sub relative to the position of the polysilicon common gate G on the P-type substrate P-sub and are used as doped regions of a source region and a drain region of an NMOS (N-channel metal oxide semiconductor), and the N-type doped region closer to an N-well region of the N-type well can be used as the doped region of the source region;
an N-type doped region formed in the N-well region N-well and used as a well tap of the well region joint region;
one of the two P-type doped regions in the P-type substrate P-sub is tightly attached to the N-type doped region corresponding to the source region of the NMOS, the other one is farther away from the source region and is spaced from the drain region of the NMOS, and the other one is used as a substrate joint region sub tap of the P-type substrate P-sub;
an interconnection layer including a source voltage contact terminal (above the substrate contact region sub tap, connected to a source voltage V)SS) A drain voltage contact terminal (above well tap region, connected with drain voltage V)DD) And a conductive segment M;
the conductive segment M forms ohmic contact with the N-type doped region and the P-type doped region (i.e., an example of doped regions with opposite conductivity types) which are closely attached to each other;
two P-type doped regions in the N-type well region N-well are used as doped regions of a source region and a drain region of the PMOS at the positions of the N-type well region N-well opposite to the polysilicon common gate G, and the doped regions of the source region are connected with a drain voltage V through an interconnection layerDDAnd the doped region of the drain region is connected with the doped region of the drain region of the NMOS through the interconnection layer and is used for the output end of the inverter. The aforementioned doped region may be a heavily doped region.
In the embodiment of the invention, the source region of the NMOS is adjusted to a position farther from the substrate connector region than the drain region thereof, and a P + region is formed next to the source region, and the source region and the P + region form ohmic contact through a conductor segment (for example, a metal wire) in the interconnection layer. At the position ofIn the structure, an equivalent circuit connection is formed, wherein the source region of the NMOS reaches a P + region through ohmic contact and then reaches the substrate and a substrate voltage contact terminal. Thus, the shunt resistor R between the base and the emitter of the lateral parasitic NPN transistorSWill not be present in the amplification circuit of the parasitic transistor, eliminating its effect on latch-up.
On the basis of the inverter shown in fig. 6, as shown in fig. 7, it can be seen that under the condition of electromagnetic interference where the operating voltage is 1.5V, the sinusoidal pulse width of the source input of the NMOS is 10ns, the frequency is 1GHz, and the amplitude is 1.5V, the source current of the NMOS of the inverter structure (i.e., the reinforced structure shown by the solid line in fig. 7) of the embodiment of the present invention is reduced by more than ten times compared with the conventional structure under the electromagnetic interference, and the electrons injected into the substrate are greatly reduced. As shown in fig. 8, the peak temperature in the inverter according to the embodiment of the present invention (the arrow in fig. 8 points to the solid line of the voltage axis, and changes periodically within 10ns, and after 10ns, it is 0V) is maintained below 310K within 10ns of the action of the electromagnetic pulse (the arrow in fig. 8 points to the solid line of the temperature axis), while the peak temperature in the inverter according to the conventional structure (the dashed line in fig. 8, and the temperature axis is used as a reference) increases with the increase of the injection time, and reaches up to 336K. After the electromagnetic pulse action is finished, the inverter with the conventional structure generates a large current density on a loop from a power supply from a source region of a PMOS to a source region of an NMOS to the ground due to latch-up effect, the peak temperature in the inverter with the conventional structure is continuously increased, and the inverter with the conventional structure is burnt out as time advances. After the action of the electromagnetic pulse of the inverter of the embodiment of the invention is finished, the peak temperature in the device is gradually reduced to the normal working temperature, and the inverter recovers to work normally.
In the embodiment of the invention, the NMOS source region and the close-attached P + region form ohmic contact through the interconnection metal wire in the interconnection layer, when strong electromagnetic pulse is injected into the NMOS source region, the close-attached P + region can also be injected, so that the substrate potential near the NMOS source region is changed along with the potential of the NMOS source region, the depletion layer bias voltage of a PN junction formed by the NMOS source region and the substrate is reduced, electrons injected into the substrate are reduced, the occurrence of latch-up effect is inhibited, and the anti-electromagnetic interference bottleneck of the CMOS inverter with the same process level is broken through.
Example 4
The embodiment of the present invention belongs to the same inventive concept as embodiments 1 to 3, and provides a layout structure, which may be a layout structure of an inverter or a corresponding semiconductor device in embodiment 3, and the layout structure includes: a P-type substrate; the first N-type active region is formed on the P-type substrate (and is positioned outside an N-type well region in the P-type substrate) and is used for forming a source region and a drain region of an NMOS; the first P-type active region is formed on the P-type substrate; the distance between the first P type active region and the source region is smaller than the distance between the first P type active region and the drain region; specifically, the boundary of the P-type injection mask region at the first P-type active region is adjacent to the boundary of the N-type injection mask region at the first N-type active region; an interconnect layer having conductivity and in contact with the first P-type active region and the active region, the contact being an ohmic contact. The P-type injection mask area is formed by injecting N-type ions into an area outside the P-type injection mask area in the N-type ion injection process step; the N-type implantation mask region is formed by implanting P-type ions into the region except the N-type implantation mask region in the P-type ion implantation process step. The size of the area of the mask area is larger than that of the corresponding active area, and the process suitable for implementation can have some reference sizes. As a choice of the area size of the doped region at the corresponding position in embodiment 1, the size of the area of the mask region may be adapted to the process, and the doped region may be regarded as an area with a concentration distribution when the doped region is not ion-implanted (may be a specific concentration such as a doping concentration of the substrate) in the mask region and outside the corresponding active region and the active region is a heavily doped concentration.
In an exemplary layout structure disclosed in the embodiment of the present invention, as shown in fig. 9, the layout structure 100 includes a P-type substrate 101, an N-type well region 102 is formed in the P-type substrate 101, and the following fig. 10 to fig. 15 (the latter diagram is based on the former diagram) will describe each part of the layout structure according to an exemplary layout drawing sequence, which is not a limited sequence and may have other suitable drawing sequences, which do not represent the process manufacturing sequence of the inverter, and the following term "forming" may be understood as drawing forming in the embodiment of the present invention.
Further, as shown in fig. 10, the source region and the drain region of NMOS and PMOS, and the region positions of the well region junction region, the substrate junction region, and the close doped region are respectively located in the P-type substrate 101 and the N-type well region 102, and a first active region 103, a second active region 104, a third active region 105, a fourth active region 106, and a fifth active region 107 are respectively formed.
Further, as shown in fig. 11, a polysilicon common gate 108 is formed on the first active region 103 and the fifth active region 107 for an input terminal of the inverter. In some cases, the symmetry axes of the first active region 103 and the fifth active region 107 may be on the same line, and the polysilicon common gate 108 may also be on the same line. The polysilicon common gate 108 divides the implantable region of the first active region 103 into a left region and a right region, such that after the doping step, the left region (which is at a smaller relative distance from the third active region 105) may be the drain region of the NMOS and the right region (which is at a greater relative distance from the third active region 105) may be the source region of the NMOS. Similarly, the polysilicon common gate 108 divides the fifth active region 107 into two implantable regions and correspondingly forms the source (right) and drain (left) regions of the PMOS.
Further, as shown in fig. 12, a first P-type implantation mask region 109 (which may be a layout identification region, and refer to embodiment 2 in the process) is formed at the position of the second active region 104, and similarly, a second P-type implantation mask region 110 and a third P-type implantation mask region 111 are formed, so that the first N-type active region can be obtained in the position region of the first active region 103 in the N-type ion implantation process step, and a second N-type active region can be obtained in the position region of the fourth active region 106.
Further, as shown in fig. 13, a first N-type implantation mask region 112 is formed at the position of the first active region 103 (at this time, a layout identification region may be formed, and in the process, in embodiment 2, the first P-type implantation mask region 109, the second P-type implantation mask region 110, and the third P-type implantation mask region 111 still need to be retained in the layout structure, so as to gradually form a complete layout structure), and similarly, a second N-type implantation mask region 113 is formed, so that the first P-type active region can be obtained in the position region of the second active region 104 in the P-type ion implantation process step, and the other two P-type active regions are obtained in the position regions of the third active region 105 and the fifth active region 107, respectively. For the first N-type injection mask region 112, the first P-type injection mask region 109 is on the right side, the second P-type injection mask region 110 is on the left side, the first P-type injection mask region 109 is tightly attached to the first N-type injection mask region 112, and the second P-type injection mask region 110 is spaced apart from the first N-type injection mask region 112. The second masked P-type implant region 110, the first masked N-type implant region 112, and the first masked P-type implant region 109 may be aligned in a direction of alignment, and the direction of alignment may be parallel to a linear direction of a boundary (e.g., length or width) of the N-type well region 102.
Further, as shown in fig. 14, contact holes (e.g., black rectangular small blocks 114) are formed in the respective active regions. As shown in fig. 15, an interconnect layer is formed, in which case the interconnect layer may be a metal layer including a first metal segment 115 for connection to a drain voltage or a power supply (a drain voltage contact may be regarded as a part of metal on the fourth active region 106), a second metal segment 116 for connection to a source voltage or ground (a source voltage contact may be regarded as a part of metal on the third active region 105), a third metal segment 117 for the aforementioned ohmic contact (an implementation of the conductor segment in the aforementioned embodiments), and a fourth metal segment 118 for an output terminal of the inverter. If the position region of the second metal segment 116 is below the layout structure and the position region of the first metal segment 115 is above the layout structure, the third metal segment 117 may be a rectangular region, and a lower boundary (projection of a line) of the rectangular region may be adjacent to a straight line where the lower boundary (line) of the first active region 103 is located or a straight line where the lower boundary of the second active region 104 is located. Since the third metal segment 117 and the second metal segment 116 are integrally formed in fig. 15, the lower boundary of the rectangular area is not separately shown.
Example 5
Embodiments of the present invention belong to the same inventive concept as embodiments 1 to 4, and embodiments of the present invention provide an integrated circuit product including the semiconductor device in embodiment 1, or
The integrated circuit product comprises the inverter of embodiment 3, or
The integrated circuit product includes the layout structure in embodiment 4.
In some implementations, the integrated circuit product may further include a product package, such as a chip package, and the integrated circuit product may be a chip including the aforementioned semiconductor device, inverter, and the like. In some cases, the integrated circuit product may further include an intellectual property core package, and the integrated circuit product may also be an intellectual property core (software module or hardware medium) containing data corresponding to the layout structure, which may be stably stored in a machine-readable data storage medium, or may be a fabricated mask.
Example 6
The embodiment of the invention and the embodiments 1 to 5 all belong to the same inventive concept, and the embodiment of the invention provides electronic equipment and a computer-readable storage medium.
Electronic devices are intended to represent various forms of devices that have instruction processing capabilities and computing capabilities. The memory stores instructions executable by the at least one processor, and the at least one processor implements the method in the foregoing embodiments by executing the instructions stored by the memory.
The computer-readable storage medium may be configured with a computer program which, when executed by a processor, implements the method in the aforementioned embodiments.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
Those skilled in the art will understand that all or part of the steps in the method according to the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present application. The electronic device may include an instruction processing device in various integrated forms (such as a microcontroller MCU, micro-controller unit; System on Chip, SoC) of integrated circuits, transistors, and the like, and the storage medium may include: various media that can store program code, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, may be non-transitory.
In addition, any combination of various different implementation manners of the embodiments of the present invention is also possible, and the embodiments of the present invention should be considered as disclosed in the embodiments of the present invention as long as the combination does not depart from the spirit of the embodiments of the present invention.

Claims (26)

1. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate;
the first doping region is formed on the substrate and is a doping region of a source region and a drain region of the first MOS;
the second doped region is formed in the substrate, the distance between the second doped region and the source region is smaller than the distance between the second doped region and the drain region, and the conductivity types of the second doped region and the source region are opposite;
an interconnect layer having conductivity in contact with the second doped region and the source region.
2. The semiconductor device according to claim 1, further comprising:
and the third doped region is formed on the substrate, and the distance between the third doped region and the source region is greater than that between the second doped region and the source region.
3. The semiconductor device according to claim 2,
the boundary of the second doped region is adjacent to the boundary of the first doped region.
4. The semiconductor device according to claim 3,
the third doped region is spaced from the boundary of the first doped region.
5. The semiconductor device according to any one of claims 2 to 4,
the contact of the interconnection layer with the second doping region and the source region is ohmic contact;
the interconnect layer includes a source voltage contact end of the third doped region.
6. The semiconductor device according to claim 5,
the interconnect layer includes a conductor segment;
the conductor segment is in contact with the second doped region and the source region, and the conductor segment is used for forming an equivalent circuit connection;
the equivalent circuit connection is the connection of the source region, through the conductor segment, with the second doped region, the body, and the source voltage contact.
7. The semiconductor device according to claim 1, wherein the base is a substrate, characterized by further comprising:
the well region is formed on the substrate;
the fourth doped region is formed in the well region and is a doped region of a source region and a drain region of the second MOS;
the second MOS is PMOS, and the first MOS is NMOS.
8. The semiconductor device according to claim 1, wherein the body is a well region of a substrate, the semiconductor device further comprising:
the fourth doped region is formed on the substrate and is a doped region of a source region and a drain region of the second MOS;
the second MOS is PMOS, and the first MOS is NMOS.
9. A method of manufacturing a semiconductor device, comprising:
forming a first doped region of a substrate, wherein the first doped region is a doped region of a source region and a drain region of a first MOS;
forming a second doped region of the substrate, wherein the distance between the second doped region and the source region is smaller than the distance between the second doped region and the drain region, and the conductivity type of the second doped region is opposite to that of the source region;
forming a conductive interconnect layer in contact with the second doped region and the source region.
10. The method of manufacturing a semiconductor device according to claim 9, wherein after the forming the first doped region of the base body and before the forming the conductive interconnect layer, the method further comprises:
and forming a third doped region of the substrate, wherein the distance between the third doped region and the source region is greater than the distance between the second doped region and the source region.
11. The method of manufacturing a semiconductor device according to claim 10, wherein the forming of the second doped region of the base body, wherein,
the boundary of the second doped region is adjacent to the boundary of the first doped region.
12. The method of manufacturing a semiconductor device according to claim 11, wherein the third doped region of the base is formed, wherein,
the third doped region is spaced from the boundary of the first doped region.
13. The method for manufacturing a semiconductor device according to any one of claims 10 to 12, wherein the forming of the conductive interconnect layer includes:
forming ohmic contacts of the second doped region and the source region;
forming a source voltage contact terminal of the third doped region.
14. The method of manufacturing a semiconductor device according to claim 13, wherein the forming ohmic contacts to the second doped region and the source region comprises:
forming a conductor segment in contact with the second doped region and the source region, the conductor segment for forming an equivalent circuit connection;
the equivalent circuit connection is the connection of the source region, through the conductor segment, with the second doped region, the body, and the source voltage contact.
15. The method of manufacturing a semiconductor device according to claim 9, wherein the base is a substrate, wherein before the forming of the conductive interconnection layer, the method further comprises:
forming a well region of the substrate;
forming a fourth doped region in the well region, the fourth doped region being a doped region of a source region and a drain region of the second MOS,
the second MOS is PMOS, and the first MOS is NMOS.
16. The method of manufacturing a semiconductor device according to claim 9, wherein the base is a well region of a substrate, and wherein before the forming of the conductive interconnection layer, the method further comprises:
forming a fourth doped region in the substrate, the fourth doped region being a doped region of a source region and a drain region of a second MOS,
the second MOS is PMOS, and the first MOS is NMOS.
17. An inverter, comprising:
a P-type substrate;
the first N-type doped region is formed in the P-type substrate and is used for forming a doped region of a source region and a doped region of a drain region of the NMOS;
the first P-type doped region is formed on the P-type substrate;
the distance between the first P-type doped region and the source region is smaller than the distance between the first P-type doped region and the drain region;
an interconnect layer having conductivity in contact with the first P-type doped region and the source region.
18. The inverter of claim 17, further comprising:
and the second P-type doped region is formed on the P-type substrate, and the distance between the second P-type doped region and the source region is greater than the distance between the first P-type doped region and the source region.
19. The inverter according to claim 18,
the contact of the interconnection layer with the first P-type doped region and the source region is ohmic contact;
and the interconnection layer is provided with a source voltage contact end of the second P-type doped region.
20. The inverter of claim 19, wherein the interconnect layer comprises:
a conductor segment in contact with the first P-type doped region and the source region, the conductor segment for forming an equivalent circuit connection;
the equivalent circuit is connected to the source region and is connected to the first P-type doped region, the P-type substrate and the source voltage contact terminal through the conductor segment.
21. The inverter according to any one of claims 17 to 20, further comprising:
the N-type well region is formed on the P-type substrate;
the third P-type doped region is formed in the N-type well region and is used for forming doped regions of a source region and a drain region of the PMOS;
the second N-type doped region is formed in the N-type well region;
the interconnection layer is in contact with the second N-type doped region and the source electrode of the PMOS;
and the interconnection layer is provided with a drain voltage contact end of the second N-type doped region.
22. The inverter of claim 21, further comprising:
the polysilicon common gate is formed on the P-type substrate and the N-type well region and is used for forming the grid electrodes of the NMOS and the PMOS and the input end of the inverter;
the interconnection layer is in contact with the third P-type doped region and the first N-type doped region and is used for forming connection of the drain electrode of the NMOS and the drain electrode of the PMOS and an output end of the inverter.
23. A layout structure, characterized in that the layout structure comprises:
a P-type substrate;
the first N-type active region is formed on the P-type substrate and used for forming a source region and a drain region of an NMOS;
the first P-type active region is formed on the P-type substrate;
the distance between the first P type active region and the source region is smaller than the distance between the first P type active region and the drain region;
an interconnect layer having conductivity in contact with the first P-type active region and the active region.
24. An electronic device, comprising:
at least one processor;
a memory coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the at least one processor implementing the method of any one of claims 9 to 16 by executing the instructions stored by the memory.
25. An integrated circuit product comprising a semiconductor device as claimed in any one of claims 1 to 8, or
The integrated circuit product comprising an inverter as claimed in any one of claims 17 to 22, or
The integrated circuit product comprising the layout structure of claim 23.
26. A computer readable storage medium storing computer instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 9 to 16.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990865A (en) * 2021-12-28 2022-01-28 北京芯可鉴科技有限公司 Silicon controlled rectifier, chip and circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6215135B1 (en) * 1998-08-04 2001-04-10 U.S. Philips Corporation Integrated circuit provided with ESD protection means
US20060049463A1 (en) * 2004-09-08 2006-03-09 Kil-Ho Kim High voltage operating electrostatic discharge protection device
US7777277B2 (en) * 2008-01-24 2010-08-17 Raydium Semiconductor Corporation Dual triggered silicon controlled rectifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6215135B1 (en) * 1998-08-04 2001-04-10 U.S. Philips Corporation Integrated circuit provided with ESD protection means
US20060049463A1 (en) * 2004-09-08 2006-03-09 Kil-Ho Kim High voltage operating electrostatic discharge protection device
US7777277B2 (en) * 2008-01-24 2010-08-17 Raydium Semiconductor Corporation Dual triggered silicon controlled rectifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990865A (en) * 2021-12-28 2022-01-28 北京芯可鉴科技有限公司 Silicon controlled rectifier, chip and circuit

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