CN113781951B

CN113781951B - Display panel and driving method

Info

Publication number: CN113781951B
Application number: CN202010516564.6A
Authority: CN
Inventors: 袁丽君; 张粲; 丛宁; 王灿; 牛晋飞
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-06-09
Filing date: 2020-06-09
Publication date: 2022-10-04
Anticipated expiration: 2040-06-09
Also published as: CN113781951A

Abstract

The invention discloses a display panel and a driving method, comprising a substrate base plate, a plurality of light-emitting modules, at least one gray scale control module, at least one row selection module and a plurality of data input modules, wherein the light-emitting modules, the gray scale control module, the at least one row selection module and the data input modules are formed on the substrate base plate; the gray scale control module can provide various gray scale signals for the electrically connected light emitting modules, and the data input module can provide data signals for the light emitting modules. The light emitting module can select one of the received multiple gray scale signals according to the received data signal and emit light according to the selected gray scale signal.

Description

Display panel and driving method

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a driving method thereof.

Background

Micro-LED (Micro light emitting diode) is a new generation display technology, and the LED structure design is thinned, miniaturized and arrayed, so that the Micro-LED has higher brightness, better luminous efficiency and lower power consumption compared with the existing OLED (organic light emitting diode) technology. The Micro-LED has the problems that the dominant peak drifts under different current densities, and the low efficiency is difficult to realize low gray scale under low current density.

Disclosure of Invention

The embodiment of the invention provides a display panel and a driving method, which are used for realizing different gray scales.

Therefore, an embodiment of the present invention provides a display panel, including a substrate base, and a plurality of light emitting modules, at least one gray scale control module, at least one row selecting module, and a plurality of data input modules formed on the substrate base;

the m gray scale signal ends of one gray scale control module are electrically connected with at least one row of light emitting modules, one row selection module is electrically connected with at least one row of light emitting modules, and the m data signal ends of one data input module are electrically connected with a plurality of light emitting modules in one row;

the gray scale control module is configured to provide gray scale signals to the electrically connected light emitting modules through the m gray scale signal ends according to signals of the trigger signal ends, wherein m is greater than or equal to 1 and is an integer;

the row selection module is configured to provide a selection signal to the corresponding light emitting module through the selection signal terminal under the signal control of the selection control terminal;

the data input module is configured to provide data signals to the electrically connected plurality of light emitting modules through the m data signal terminals under the signal control of the data control terminal;

the light emitting module is configured to receive the data signal and the gray scale signal and emit light under control of the data signal and the gray scale signal.

Optionally, the light emitting module includes a data latch module, a light emitting driving module and a light emitting device;

wherein the data latch module is configured to latch the received data signal and provide the data signal to the light-emitting driving module under the control of the selection signal;

the light-emitting driving module is configured to receive the data signal and the plurality of gray scale signals and drive the light-emitting device to emit light according to the received gray scale signals under the control of the data signal.

Optionally, the light emitting driving module comprises: the display device comprises m gray scale switch transistors, a first light emitting control transistor, a second light emitting control transistor, a storage capacitor and a driving transistor;

the first ends of the m gray scale switch transistors are electrically connected with the m gray scale signal ends in a one-to-one correspondence manner, the control ends of the m gray scale switch transistors are electrically connected with the data latch module, and the second ends of the m gray scale switch transistors are electrically connected with the control end of the first light-emitting control transistor;

the first end of the first light-emitting control transistor is electrically connected with a first reference signal end, and the second end of the first light-emitting control transistor is electrically connected with the grid electrode of the driving transistor;

the first end of the second light-emitting control transistor is electrically connected with a second reference signal end, the control end of the second light-emitting control transistor is electrically connected with the trigger signal end, and the second end of the second light-emitting control signal end is electrically connected with the grid electrode of the driving transistor;

a first end of the storage capacitor is electrically connected with a first power supply end, and a second end of the storage capacitor is electrically connected with the grid electrode of the driving transistor;

the first electrode of the driving transistor is electrically connected with the first power supply end, and the second electrode of the driving transistor is electrically connected with the anode of the light-emitting device.

Optionally, the data latch module includes: m data switching transistors and m latches;

first ends of the m data switch transistors are electrically connected with the m data signal ends in a one-to-one correspondence manner, control ends of the m data switch transistors are electrically connected with one selection signal end, and second ends of the m data switch transistors are electrically connected with first ends of the m latches in a one-to-one correspondence manner;

and the second ends of the m latches are electrically connected with the control ends of the m gray scale switch transistors in a one-to-one correspondence manner.

Optionally, the latch comprises a first inverter and a second inverter;

the input end of the first phase inverter is electrically connected with the second end of the corresponding data switch transistor, and the output end of the first phase inverter is electrically connected with the control end of the corresponding gray-scale switch transistor;

the input end of the second phase inverter is electrically connected with the output end of the first phase inverter, and the output end of the second phase inverter is electrically connected with the input end of the first phase inverter.

Optionally, dividing the plurality of light emitting modules into a plurality of row groups; one of the row groups includes four rows of the light emitting modules, and the light emitting modules included in different row groups are different;

one of the row selection modules is electrically connected with the four rows of light emitting modules in one of the row groups;

one gray scale control module is electrically connected with the four rows of light-emitting modules in one row group;

one of the data input modules is electrically connected to one of the columns of light emitting modules in the one row group.

Optionally, m =4, the 4 gray scale signal terminals of the gray scale control module include a first gray scale signal terminal, a second gray scale signal terminal, a third gray scale signal terminal, and a fourth gray scale signal terminal; the gray scale control module comprises: the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, the sixth switch transistor, the seventh switch transistor, the eighth switch transistor, the first NOR gate, the second NOR gate, the third NOR gate, the fourth NOR gate, the first gray-scale inverter, the second gray-scale inverter, the third gray-scale inverter and the fourth gray-scale inverter;

a first end of the first switching transistor is electrically connected with the trigger signal end, a control end of the first switching transistor is electrically connected with a first clock signal end, and a second end of the first switching transistor is electrically connected with a first input end of the first nor gate;

the second input end of the first NOR gate is electrically connected with the second clock signal end, and the output end of the first NOR gate is electrically connected with the first end of the first gray-scale phase inverter;

the second end of the first gray-scale phase inverter is electrically connected with the first gray-scale signal end;

a first end of the second switching transistor is electrically connected with a second end of the first switching transistor, a control end of the second switching transistor is electrically connected with the second clock signal end, and a second end of the second switching transistor is electrically connected with the first gray scale signal end;

the first end of the third switching transistor is electrically connected with the first gray scale signal end, the control end of the third switching transistor is electrically connected with the second clock signal end, and the second end of the third switching transistor is electrically connected with the first input end of the second NOR gate;

a second input end of the second nor gate is electrically connected with a first clock signal end, and an output end of the second nor gate is electrically connected with a first end of the second gray-scale inverter;

a second end of the second gray-scale inverter is electrically connected with the second gray-scale signal end;

a first end of the fourth switching transistor is electrically connected with a second end of the third switching transistor, a control end of the fourth switching transistor is electrically connected with the first clock signal end, and a second end of the fourth switching transistor is electrically connected with the second gray scale signal end;

a first end of the fifth switching transistor is electrically connected with the second gray-scale signal end, a control end of the fifth switching transistor is electrically connected with the first clock signal end, and a second end of the fifth switching transistor is electrically connected with a first input end of the third nor gate;

a second input end of the third NOR gate is electrically connected with a second clock signal end, and an output end of the third NOR gate is electrically connected with a first end of the third gray-scale phase inverter;

a second end of the third gray-scale phase inverter is electrically connected with the third gray-scale signal end;

a first end of the sixth switching transistor is electrically connected with a second end of the fifth switching transistor, a control end of the sixth switching transistor is electrically connected with the second clock signal end, and a second end of the sixth switching transistor is electrically connected with the third gray scale signal end;

a first end of the seventh switching transistor is electrically connected with the third gray scale signal end, a control end of the seventh switching transistor is electrically connected with the second clock signal end, and a second end of the seventh switching transistor is electrically connected with a first input end of the fourth nor gate;

a second input end of the fourth NOR gate is electrically connected with a first clock signal end, and an output end of the fourth NOR gate is electrically connected with a first end of the fourth gray-scale phase inverter;

a second end of the fourth gray-scale inverter is electrically connected with the fourth gray-scale signal end;

a first end of the eighth switching transistor is electrically connected to a second end of the seventh switching transistor, a control end of the eighth switching transistor is electrically connected to the first clock signal end, and a second end of the eighth switching transistor is electrically connected to the fourth grayscale signal end.

Optionally, m =4, the 4 data signal terminals of the data input module include: a first data signal terminal, a second data signal terminal, a third data signal terminal and a fourth data signal terminal; the data input module includes: the first inverter, the second inverter, the third nand gate and the fourth nand gate are connected in series; the data control end comprises a first data control end and a second data control end;

a first input end of the first nand gate is electrically connected with a second end of the third inverter, a second input end of the first nand gate is electrically connected with a second end of the fourth inverter, and an output end of the first nand gate is electrically connected with the first data signal end;

a first input end of the second nand gate is electrically connected with a first data control end, a second input end of the second nand gate is electrically connected with a second end of the fourth inverter, and an output end of the second nand gate is electrically connected with a second data signal end;

a first input end of the third nand gate is electrically connected with a second end of the third inverter, a second input end of the third nand gate is electrically connected with a second data control end, and an output end of the third nand gate is electrically connected with a third data signal end;

a first input end of the fourth nand gate is electrically connected with the first data control end, a second input end of the fourth nand gate is electrically connected with the second data control end, and an output end of the fourth nand gate is electrically connected with the fourth data signal end;

a first end of the third inverter is electrically connected with the first data control end;

a first end of the fourth inverter is electrically connected to the second data control end.

Optionally, the plurality of selection signal terminals of the row selection module include: the first selection signal end, the second selection signal end, the third selection signal end and the fourth selection signal end; the row selection module includes: the first inverter, the sixth inverter, the fifth NAND gate, the sixth NAND gate, the seventh NAND gate, the eighth NAND gate, the first OR gate, the second OR gate, the third OR gate and the fourth OR gate; the selection control end comprises a first selection control end, a second selection control end and a third selection control end;

a first input end of the fifth nand gate is electrically connected with a second end of the fifth inverter, a second input end of the fifth nand gate is electrically connected with a second end of the sixth inverter, and an output end of the fifth nand gate is electrically connected with a first input end of the first or gate;

the second input end of the first or gate is electrically connected with the third selection control end, and the output end of the first or gate is electrically connected with the first selection signal end;

a first input end of the sixth nand gate is electrically connected with the first selection control end, a second input end of the sixth nand gate is electrically connected with a second end of the sixth inverter, and an output end of the sixth nand gate is electrically connected with the second selection signal end;

a first input end of the seventh nand gate is electrically connected with a second end of the fifth inverter, a second input end of the seventh nand gate is electrically connected with a second selection control end, and an output end of the seventh nand gate is electrically connected with a first input end of the third or gate;

a second input end of the third or gate is electrically connected with the third selection control end, and an output end of the third or gate is electrically connected with the third selection signal end;

a first input end of the eighth nand gate is electrically connected with the first data control end, a second input end of the eighth nand gate is electrically connected with the second selection control end, and an output end of the eighth nand gate is electrically connected with a first input end of the fourth or gate;

a second input end of the fourth or gate is electrically connected with the third selection control end, and an output end of the fourth or gate is electrically connected with the fourth selection signal end;

a first end of the fifth inverter is electrically connected with the first selection control end;

and the first end of the sixth inverter is electrically connected with the second selection control end.

Correspondingly, an embodiment of the present invention further provides a method for driving any one of the display panels, including:

in the data writing stage, a signal of a second level is loaded on the trigger signal end, the row selection module is controlled to sequentially load a signal of a first level on each selection signal end, the gray scale control module is controlled to load a signal of a second level on each gray scale signal end, and the data input module is controlled to provide a data signal for each data signal end;

in the first light-emitting stage, a signal of a first level is loaded on a trigger signal end, a row selection module is controlled to load a signal of a second level on each selection signal end, and a gray scale control module is controlled to load a signal of a second level on each gray scale signal end;

and in the second light-emitting stage, a signal of a second level is loaded on the trigger signal end, the row selection module is controlled to load a signal of the second level on each selection signal end, and the gray scale control module is controlled to sequentially load a signal of the first level on each gray scale signal end.

The invention has the following beneficial effects:

the embodiment of the invention provides a display panel and a driving method, comprising a substrate base plate, a plurality of light-emitting modules, at least one gray scale control module, at least one row selection module and a plurality of data input modules, wherein the light-emitting modules, the gray scale control module, the row selection module and the data input modules are formed on the substrate base plate; the gray scale control module can provide various gray scale signals for the electrically connected light emitting modules, and the data input module can provide data signals for the light emitting modules. The light emitting module can select one of the received multiple gray scale signals according to the received data signal and emit light according to the selected gray scale signal.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a light emitting module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a row group in a display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a gray scale control module according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a data input module according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a row selection module according to an embodiment of the present invention;

fig. 7 is a flowchart of a driving method of a display panel according to an embodiment of the invention;

fig. 8 is a signal timing diagram of a display panel according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "electrically connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As shown in fig. 1, a display panel provided in an embodiment of the present invention includes: a substrate base plate 10, and a plurality of light emitting modules 100, at least one gray scale control module 200, at least one row selection module 300, and a plurality of data input modules 400 formed on the substrate base plate 10;

the m gray scale signal terminals L1 to Lm of one gray scale control module 200 are electrically connected to at least one row of light emitting modules 100, one row selection module 300 is electrically connected to at least one row of light emitting modules 100, and the m data signal terminals S1 to Sm of one data input module 400 are electrically connected to a plurality of light emitting modules 100 in one row;

the gray scale control module 200 is configured to provide a gray scale signal to the electrically connected light emitting module 100 through m gray scale signal terminals according to a signal of the trigger signal terminal STV, wherein m is greater than or equal to 1 and is an integer;

the row selection module 300 is configured to provide a selection signal to the corresponding light emitting module 100 through the selection signal terminals G1 to Gx under the signal control of the selection control terminal a; wherein x is not less than 1 and is an integer;

the data input module 400 is configured to provide a data signal to the electrically connected plurality of light emitting modules 100 through the m data signal terminals S1 to Sm under signal control of the data control terminal D;

the light emitting module 100 is configured to receive a data signal and a gray-scale signal and emit light under the control of the data signal and the gray-scale signal.

According to the display panel provided by the embodiment of the invention, various gray scale signals can be provided for the electrically connected light emitting modules through the gray scale control module, and data signals can be provided for the light emitting modules through the data input module. The light emitting module can select one of the received multiple gray scale signals according to the received data signal and emit light according to the selected gray scale signal.

Further, the display panel provided by the embodiment of the invention can be a Micro-LED display panel. The light emitting device in the light emitting module 100 may be a Micro-LED, and the light emitting module 100 may provide a constant current to the Micro-LED light emitting device when emitting light, so that a problem that in the related art, the dominant peak of the Micro-LED shifts at different current densities, and a low efficiency is difficult to achieve a low gray scale at a low current density can be avoided.

It should be noted that the light emitting module 100 may receive multiple gray scale signals to control the light emitting time of the light emitting devices, so as to control the light emitting time of the light emitting devices with different colors in the pixels, and further control the gray scale of the pixels. For example, in the embodiment of the present invention, the gray scale control module 200 provides the gray scale signals to the electrically connected light emitting module 100 through the m gray scale signal terminals, and then one gray scale signal terminal corresponds to one gray scale signal, so that the gray scale control module 200 provides the m gray scale signals to the light emitting module 100. That is, for one light emitting module 100, there may be m light emitting conditions, and if the display panel performs color mixing by three colors of red, green and blue, that is, one pixel in the display panel includes the red light emitting module 100, the green light emitting module 100 and the blue light emitting module 100, the display panel may implement m light emitting conditions ³ If m is 4, the display panel can realize 64 gray levels.

In particular implementations, as shown in fig. 1, the gray scale control module 200 may be used to provide gray scale signals to the multi-row light emitting module 100. Alternatively, one gray scale control module 200 may provide gray scale signals to only one row of light emitting modules 100.

In specific implementation, in the embodiment of the present invention, as shown in fig. 2, the light emitting module 100 may include a data latch module 120, a light emitting driving module 110, and a light emitting device L;

wherein the data latch module 120 is configured to latch the received data signal and provide the data signal to the light emitting driving module 110 under the control of the selection signal;

the light emitting driving module 110 is configured to receive a data signal and a plurality of gray scale signals, and drive the light emitting device to emit light according to the received gray scale signals under the control of the data signal.

The light emitting module 100 in the embodiment of the invention includes the data latch module 120, which can latch the received data signal and keep the data signal supplied to the light emitting driving module 110 stable.

In an implementation, the light emitting driving module 110 drives the light emitting device to emit light according to the received gray scale signals, and provides a constant current to the light emitting device when the light emitting device emits light, where each gray scale signal is used to control the light emitting time of the light emitting device. The driving of the light emitting device by the light emitting driving module 110 according to the received gray scale signal may specifically include: when the light emission starts, the light emission driving module 110 supplies a constant current to the light emitting device and stops supplying the current to the light emitting device after a certain time according to a gray scale signal. In a specific implementation, a signal is required to be set for controlling the light emitting driving module 110 to start supplying current to the light emitting device, and since the gray scale control module 200 is configured to supply the gray scale signal to the light emitting module 100 according to the signal of the trigger signal terminal, the signal may be the signal of the trigger signal terminal.

In specific implementation, in the embodiment of the present invention, as shown in fig. 2, the light emitting driving module 110 may include: m gray scale switch transistors Mg1 to Mgm, a first light emission control transistor ML1, a second light emission control transistor ML2, a storage capacitor Cst, and a drive transistor TFT;

the first ends of the m gray scale switch transistors are electrically connected with the m gray scale signal ends in a one-to-one correspondence manner, the control ends of the m gray scale switch transistors are electrically connected with the data latch module 120, and the second ends of the m gray scale switch transistors are electrically connected with the control end of the first light emitting control transistor;

a first terminal of the first light emission control transistor ML1 is electrically connected to the first reference signal terminal VGH, and a second terminal of the first light emission control transistor ML1 is electrically connected to the gate electrode of the driving transistor TFT;

a first end of the second light emission control transistor ML2 is electrically connected to the second reference signal terminal VGL, a control end of the second light emission control transistor ML2 is electrically connected to the trigger signal terminal STV, and a second end of the second light emission control signal terminal ML2 is electrically connected to the gate electrode of the driving transistor TFT;

a first end of the storage capacitor Cst is electrically connected to the first power terminal VDD, and a second end of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor TFT;

a first electrode of the driving transistor TFT is electrically connected to the first power terminal VDD, and a second electrode of the driving transistor is electrically connected to an anode of the light emitting device.

In a specific implementation, in an embodiment of the present invention, as shown in fig. 2, the data latch module 120 may include: m data switch transistors Md1 to Mdm and m latches;

the first ends of the m data switch transistors are electrically connected with the m data signal ends S1-Sm in a one-to-one correspondence mode, the control ends of the m data switch transistors are electrically connected with a selection signal end Gx, and the second ends of the m data switch transistors are electrically connected with the first ends of the m latches in a one-to-one correspondence mode;

and the second ends of the m latches are electrically connected with the control ends of the m gray-scale switch transistors Mg 1-Mgm in a one-to-one correspondence manner.

Alternatively, the latch may include a first inverter I1 and a second inverter I2; the input end of the first phase inverter I1 is electrically connected with the second end of the corresponding data switch transistor, and the output end of the first phase inverter I1 is electrically connected with the control end of the corresponding gray-scale switch transistor; the input end of the second phase inverter I2 is electrically connected with the output end of the first phase inverter, and the output end of the second phase inverter I2 is electrically connected with the input end of the first phase inverter I1. The first terminal of the latch is the input terminal of the first inverter I1, the second terminal of the latch is the output terminal of the first inverter I1, and the latch inverts the received data signal and provides the inverted data signal to the gray-scale switching transistor.

Alternatively, the latch may not invert the received data signal, as shown in fig. 2, the input end of the first inverter I1 is electrically connected to the second end of the corresponding data switching transistor and the control end of the corresponding gray-scale switching transistor, the output end of the first inverter I1 is electrically connected to the input end of the second inverter I2, and the output end of the second inverter I2 is electrically connected to the input end of the first inverter I1. I.e. the first and second ends of the latch are the same end.

In practical implementation, in the embodiment of the present invention, as shown in fig. 3, the plurality of light emitting modules 100 are divided into a plurality of row groups; four rows of light emitting modules 100 may be included in one row group, and the light emitting modules 100 included in different row groups are different;

one row selection module 300 is electrically connected with four rows of light emitting modules 100 in one row group;

one gray scale control module 200 is electrically connected with four rows of light emitting modules 100 in one row group;

a data input module 400 is electrically connected to a column of light emitting modules 100 in a row group.

In a specific implementation, the number of rows of the light emitting modules 100 included in one row group is not limited to four rows, and may be determined by design according to actual needs, and is not limited herein.

In practical implementation, as shown in fig. 4, in the embodiment of the present invention, if m =4, the 4 gray scale signal terminals of the gray scale control module 200 include a first gray scale signal terminal L1, a second gray scale signal terminal L2, a third gray scale signal terminal L3, and a fourth gray scale signal terminal L4; the gray scale control module 200 may include: a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, a fifth switching transistor M5, a sixth switching transistor M6, a seventh switching transistor M7, an eighth switching transistor M8, a first nor gate NO1, a second nor gate NO2, a third nor gate NO3, a fourth nor gate NO4, a first grayscale inverter Ig1, a second grayscale inverter Ig2, a third grayscale inverter Ig3, and a fourth grayscale inverter Ig4;

a first end of the first switching transistor M1 is electrically connected to the trigger signal terminal STV, a control end of the first switching transistor M1 is electrically connected to the first clock signal terminal CB, and a second end of the first switching transistor M1 is electrically connected to a first input end of the first nor gate NO 1;

a second input end of the first nor gate NO1 is electrically connected with the second clock signal end CK, and an output end of the first nor gate NO1 is electrically connected with a first end of the first grayscale inverter Ig 1;

a second end of the first gray-scale inverter Ig1 is electrically connected to the first gray-scale signal end L1;

a first end of the second switching transistor M2 is electrically connected to a second end of the first switching transistor M1, a control end of the second switching transistor M2 is electrically connected to the second clock signal terminal CK, and a second end of the second switching transistor M2 is electrically connected to the first gray-scale signal terminal L1;

a first end of the third switching transistor M3 is electrically connected to the first gray-scale signal end L1, a control end of the third switching transistor M3 is electrically connected to the second clock signal end CK, and a second end of the third switching transistor M3 is electrically connected to a first input end of the second nor gate NO 2;

a second input terminal of the second nor gate NO2 is electrically connected to the first clock signal terminal CB, and an output terminal of the second nor gate NO2 is electrically connected to a first terminal of the second gray-scale inverter Ig 2;

a second terminal of the second gray-scale inverter Ig2 is electrically connected to the second gray-scale signal terminal L2;

a first end of the fourth switching transistor M4 is electrically connected to a second end of the third switching transistor M3, a control end of the fourth switching transistor M4 is electrically connected to the first clock signal terminal CB, and a second end of the fourth switching transistor M4 is electrically connected to the second gray scale signal terminal L2;

a first end of the fifth switching transistor M5 is electrically connected to the second gray scale signal end L2, a control end of the fifth switching transistor M5 is electrically connected to the first clock signal end CB, and a second end of the fifth switching transistor M5 is electrically connected to a first input end of the third nor gate NO 3;

a second input end of the third nor gate NO3 is electrically connected to the second clock signal terminal CK, and an output end of the third nor gate NO3 is electrically connected to a first end of the third grayscale inverter Ig 3;

a second end of the third grayscale inverter Ig3 is electrically connected to the third grayscale signal end L3;

a first end of the sixth switching transistor M6 is electrically connected to the second end of the fifth switching transistor M5, a control end of the sixth switching transistor M6 is electrically connected to the second clock signal end CK, and a second end of the sixth switching transistor M6 is electrically connected to the third grayscale signal end L3;

a first end of the seventh switching transistor M7 is electrically connected to the third grayscale signal end L3, a control end of the seventh switching transistor M7 is electrically connected to the second clock signal end CK, and a second end of the seventh switching transistor M7 is electrically connected to a first input end of the fourth nor gate NO 4;

a second input end of the fourth nor gate NO4 is electrically connected to the first clock signal end CB, and an output end of the fourth nor gate NO4 is electrically connected to a first end of the fourth grayscale inverter Ig4;

a second end of the fourth grayscale inverter Ig4 is electrically connected to the fourth grayscale signal terminal L4;

a first terminal of the eighth switching transistor M8 is electrically connected to the second terminal of the seventh switching transistor M7, a control terminal of the eighth switching transistor M8 is electrically connected to the first clock signal terminal CB, and a second terminal of the eighth switching transistor M8 is electrically connected to the fourth grayscale signal terminal L4.

In specific implementation, the gray scale control module 200 shown in fig. 4 can be regarded as a cascade of 4-level shift registers, and different gray scale signals can be output through the output ends of the shift registers of different levels by delaying the signals. When the value of m is not 4, the structure of the gray scale control module 200 can be adjusted by adjusting the number of cascaded shift registers. Of course, in the implementation, as long as the gray-scale control module 200 can output a plurality of gray-scale signals, the specific structure of the gray-scale control module is not limited thereto, and is not limited thereto.

Specifically, in order to unify the manufacturing process, in the display panel provided in the embodiment of the present invention, as shown in fig. 2 and fig. 4, all the transistors may be P-type transistors, and certainly, all the transistors may also be N-type transistors, which is not limited herein.

Specifically, in the display panel provided in the embodiment of the present invention, the P-type transistor is turned on by a low level signal and turned off by a high level signal; the N-type transistor is turned on under the action of a high-level signal and is turned off under the action of a low-level signal.

Specifically, in the display panel provided in the embodiment of the present invention, each Transistor may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), which is not limited herein. Depending on the type of each transistor and the signal of the control terminal of each transistor, the control terminal of each transistor may be used as a gate, the first terminal of each transistor may be used as a source, and the second terminal of each transistor may be used as a drain, or the first terminal of each transistor may be used as a drain and the second terminal may be used as a source, which are not specifically distinguished herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 5, m =4, then the 4 data signal terminals of the data input module 400 include: the data input module 400 includes a first data signal terminal S1, a second data signal terminal S2, a third data signal terminal S3, and a fourth data signal terminal S4, and includes: a third inverter I3, a fourth inverter I4, a first nand gate NA1, a second nand gate NA2, a third nand gate NA3, and a fourth nand gate NA4; the data control end comprises a first data control end D0 and a second data control end D1;

a first input end of the first nand gate NA1 is electrically connected with a second end of the third inverter I3, a second input end of the first nand gate NA1 is electrically connected with a second end of the fourth inverter I4, and an output end of the first nand gate NA1 is electrically connected with the first data signal end S1;

a first input end of the second nand gate NA2 is electrically connected with the first data control end D0, a second input end of the second nand gate NA2 is electrically connected with a second end of the fourth inverter I4, and an output end of the second nand gate NA2 is electrically connected with the second data signal end S2;

a first input end of the third nand gate NA3 is electrically connected with a second end of the third inverter I3, a second input end of the third nand gate NA3 is electrically connected with the second data control end D1, and an output end of the third nand gate NA3 is electrically connected with the third data signal end S3;

a first input end of the fourth nand gate NA4 is electrically connected with the first data control end D0, a second input end of the fourth nand gate NA4 is electrically connected with the second data control end D1, and an output end of the fourth nand gate NA4 is electrically connected with the fourth data signal end S4;

a first end of the third inverter I3 is electrically connected with the first data control end D0;

a first terminal of the fourth inverter I4 is electrically connected to the second data control terminal D1.

As for the data input module 400 shown in fig. 5, providing data signals to the electrically connected light emitting modules 100 through 4 data signal terminals under the signal control of the data control terminal specifically includes:

loading a low level to the first data control end D0, loading a low level to the second data control end D1, outputting a low level by the first data signal end S1, outputting a high level by the second data signal end S2, outputting a high level by the third data signal end S3, and outputting a high level by the fourth data signal end S4;

loading a low level to the first data control terminal D0 and a high level to the second data control terminal D1, then outputting a high level by the first data signal terminal S1, outputting a low level by the second data signal terminal S2, outputting a high level by the third data signal terminal S3, and outputting a high level by the fourth data signal terminal S4;

loading a high level to the first data control end D0 and loading a low level to the second data control end D1, wherein the first data signal end S1 outputs a high level, the second data signal end S2 outputs a high level, the third data signal end S3 outputs a low level, and the fourth data signal end S4 outputs a high level;

a high level is loaded to the first data control terminal D0, and a high level is loaded to the second data control terminal D1, so that the first data signal terminal S1 outputs a high level, the second data signal terminal S2 outputs a high level, the third data signal terminal S3 outputs a high level, and the fourth data signal terminal S4 outputs a low level.

For a light emitting module 100, only one gray scale signal is used for emitting light at a time, so the data signal output by the data input module 400 may only include an active level, and the light emitting module 100 selects the gray scale signal according to the received data signal of the active level. For the data input module 400 shown in fig. 5, if the active level is low level, which of the first data signal terminal S1 to the fourth data signal terminal S4 outputs low level can be controlled by adjusting the signals of the first data control terminal D0 and the second data control terminal D1. When the valid level is a high level, one high level and three low levels need to be output, and the first nand gate NA1 to the fourth nand gate NA4 may be replaced by and gates. Of course, the specific structure of the data input module 400 may be the same as that of the related art, and is not limited herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 6, the plurality of selection signal terminals of the row selection module 300 include: a first selection signal terminal G1, a second selection signal terminal G2, a third selection signal terminal G3 and a fourth selection signal terminal G4; the row selection module 300 includes: a fifth inverter I5, a sixth inverter I6, a fifth nand gate NA5, a sixth nand gate NA6, a seventh nand gate NA7, an eighth nand gate NA8, a first or gate OG1, a second or gate OG2, a third or gate OG3, and a fourth or gate OG4; the selection control end comprises a first selection control end A0, a second selection control end A1 and a third selection control end A2;

a first input end of the fifth nand gate NA5 is electrically connected to a second end of the fifth inverter I5, a second input end of the fifth nand gate NA5 is electrically connected to a second end of the sixth inverter I6, and an output end of the fifth nand gate NA5 is electrically connected to a first input end of the first or gate OG 1;

a second input end of the first or gate OG1 is electrically connected with the third selection control end A2, and an output end of the first or gate OG1 is electrically connected with the first selection signal end G1;

a first input end of a sixth nand gate NA6 is electrically connected with the first selection control end A0, a second input end of the sixth nand gate NA6 is electrically connected with a second end of the sixth inverter I6, and an output end of the sixth nand gate NA6 is electrically connected with a first input end of the second or gate OG 2;

a second input end of the second or gate OG2 is electrically connected with the third selection control end A2, and an output end of the second or gate OG2 is electrically connected with the second selection signal end G2;

a first input end of the seventh nand gate NA7 is electrically connected to a second end of the fifth inverter I5, a second input end of the seventh nand gate NA7 is electrically connected to the second selection control end A1, and an output end of the seventh nand gate NA7 is electrically connected to a first input end of the third or gate OG 3;

a second input end of the third or gate OG3 is electrically connected with the third selection control end A2, and an output end of the third or gate OG3 is electrically connected with the third selection signal end G3;

a first input end of the eighth nand gate NA8 is electrically connected with the first data control end, a second input end of the eighth nand gate NA8 is electrically connected with the second selection control end A1, and an output end of the eighth nand gate NA8 is electrically connected with a first input end of the fourth or gate OG4;

a second input end of the fourth or gate OG4 is electrically connected with the third selection control end A2, and an output end of the fourth or gate OG4 is electrically connected with the fourth selection signal end G4;

a first end of the fifth inverter I5 is electrically connected with the first selection control end A0;

a first terminal of the sixth inverter I6 is electrically connected to the second selection control terminal A1.

In a specific implementation, when four light emitting modules 100 are included in one row group, the structure of the row selection module 300 may be as shown in fig. 6, and when the number of rows of light emitting modules 100 included in one row group is not four, the structure of the row selection module 300 may be the same as that in the related art, for example, may be a cascaded shift register, and is not limited herein.

In specific implementation, the specific circuit structures of the inverter, the nand gate, the and gate, the or gate, and the nor gate in this document may be substantially the same as those in the related art, and are not described herein again.

Based on the same inventive concept, an embodiment of the present invention further provides a method for driving any one of the above display panels, as shown in fig. 7, including:

s701, in a data writing stage, loading a signal of a second level to a trigger signal end, controlling a row selection module to sequentially load a signal of a first level to each selection signal end, controlling a gray scale control module to load a signal of a second level to each gray scale signal end, and controlling a data input module to provide a data signal to each data signal end;

s702, in a first light-emitting stage, loading a signal of a first level to a trigger signal end, controlling a row selection module to load a signal of a second level to each selection signal end, and controlling a gray scale control module to load a signal of a second level to each gray scale signal end;

and S703, in the second light-emitting stage, loading a signal of a second level to the trigger signal end, controlling the row selection module to load a signal of the second level to each selection signal end, and controlling the gray scale control module to sequentially load a signal of the first level to each gray scale signal end.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

Next, taking a row group of the display panel shown in fig. 3, the light-emitting module shown in fig. 2, the gray-scale control module shown in fig. 4, the data input module shown in fig. 5 and the row selection module shown in fig. 6 as examples, the operation process of the display panel according to the embodiment of the present invention will be described with reference to the signal timing diagram shown in fig. 8. In the following description, 1 represents a high level, and 0 represents a low level. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values. Specifically, the first data writing stage t1, the second data writing stage t2, the third data writing stage t3, the fourth data writing stage t4, the first light-emitting stage t5, the second light-emitting stage t6, the third light-emitting stage t7, the fourth light-emitting stage t8, and the fifth light-emitting stage t9 in the signal timing diagram shown in fig. 8 are taken as examples for description. The signal of the first reference signal terminal VGH is at a high level, and the signal of the second reference signal terminal VGL is at a low level.

The first clock signal terminal CB is electrically connected to the control terminals of the first, fourth, fifth and eighth switching transistors M1, M4, M5 and M8, and the second clock signal terminal CK is electrically connected to the control terminals of the second, third, sixth and seventh switching transistors M2, M3, M6 and M7. When CB =1, the first switching transistor M1, the fourth switching transistor M4, the fifth switching transistor M5, and the eighth switching transistor M8 are all turned off; when CB =0, the first, fourth, fifth, and eighth switching transistors M1, M4, M5, and M8 are all turned on. When CK =1, the second switching transistor M2, the third switching transistor M3, the sixth switching transistor M6, and the seventh switching transistor M7 are all turned off; when CK =0, the second switching transistor M2, the third switching transistor M3, the sixth switching transistor M6, and the seventh switching transistor M7 are all turned on.

In the first to fourth data writing phases t1 to t4, STV =1, A2=0.STV =1, the first nor gate NO1 in the gray scale control module only outputs a low level, i.e., L1=1, the first input terminal of the second nor gate NO2 receives a high level when the third switching transistor M3 is turned on, the second input terminal of the second nor gate NO2 receives a high level when the third switching transistor M3 is turned off, and the second nor gate NO2 only outputs a low level, i.e., L2=1, similarly, the signals of the third gray scale signal terminal L3 and the fourth gray scale signal terminal L4 are both high levels. When the 4 gray-scale switching transistors Mg1 to Mg4 in the light emitting module are turned on, a high level signal is provided to the control terminal of the first light emitting control transistor ML1, so that the first light emitting control transistor ML1 is turned off. Since STV =1, the second light emission controlling transistor ML2 is also not turned on. The driving transistor TFT is turned off and all the light emitting modules do not emit light. Since A2=0, when each nand gate outputs a high level, the corresponding selection signal terminal also outputs a high level, and when the nand gate outputs a low level, the corresponding selection signal terminal also outputs a low level.

In the first data writing phase t1, A1=0 and A0=0, G1=0, G2=1, G3=1 and G4=1, so that all the 4 data switching transistors Md1 to Md4 in the light emitting modules in the first row are turned on, and all the 4 data switching transistors Md1 to Md4 in the light emitting modules in the second, third and fourth rows are turned off. The light emitting modules in each row and each column of the first row receive data signals through the first data signal end S1 to the fourth data signal end S4, the data signals are latched through the first inverter I1 and the second inverter I2, and the data signals are provided for the corresponding gray scale switch transistors, the data signals comprise a low level signal and three high level signals, one of the 4 gray scale switch transistors Mg1 to Mg4 is conducted, and the conducted gray scale switch transistor conducts the control end of the first light emitting control transistor ML1 and one of the 4 gray scale signal ends L1 to L4.

In the second data writing phase t2, A1=0 and A0=1, G1=1, G2=0, G3=1 and G4=1, so that all the 4 data switching transistors Md1 to Md4 in the light emitting modules in the second row are turned on, and all the 4 data switching transistors Md1 to Md4 in the light emitting modules in the first row, the third row and the fourth row are turned off. In the third data writing stage t3, A1=1 and A0=0, G1=1, G2=1, G3=0 and G4=1, so that all of the 4 data switching transistors Md1 to Md4 in the light emitting modules in the third row are turned on, and all of the 4 data switching transistors Md1 to Md4 in the light emitting modules in the first row, the second row and the fourth row are turned off. In the fourth phase t4 of data writing, A1=1 and A0=1, G1=1, G2=1, G3=1 and G4=0, so that all 4 data switching transistors Md1 to Md4 in the fourth row of light emitting modules are turned on, and all 4 data switching transistors Md1 to Md4 in the first, second and third rows of light emitting modules are turned off. For the second row of light-emitting modules when data is written into the second stage t2, the third row of light-emitting modules when data is written into the third stage t3, and the fourth row of light-emitting modules when data is written into the fourth stage t4, the working process of the second row of light-emitting modules is substantially the same as that of the first row of light-emitting modules in the first stage t1, which is not described herein again.

In the first to fifth light-emitting phases t5 to t9, A2=1, G1=1, G2=1, G3=1, and G4=1, so that all of the 4 data switching transistors Md1 to Md4 in the 4 rows of light-emitting modules are turned off. The light emitting module no longer accepts the data signal. The data latch module in the light-emitting module still latches the data signal input from the first data writing stage t1 to the fourth data writing stage t4, and controls one of the 4 gray-scale switch transistors Mg1 to Mg4 to be turned on.

In the first light emitting phase t5, STV =0, cb =0, ck =1.CB =0, the first switching transistor M1 is turned on, and the low level signal of the trigger signal terminal STV is supplied to the first input terminal of the first nor gate NO1, so that the first nor gate NO1 outputs the low level signal. CK =1, the second switching transistor M2 is turned off. The first gray scale signal terminal L1 outputs a high level signal, and the second gray scale signal terminal L2, the third gray scale signal terminal L3, and the fourth gray scale signal terminal L4 all keep outputting a high level signal. STV =0, the second emission control transistor ML2 is turned on, and a low-level signal of the second reference signal terminal VGL is supplied to the gate of the driving transistor TFT to turn on the driving transistor TFT. All the light emitting modules in the row group emit light.

In the light emitting second stage t6, STV =1, cb =1, ck =0.STV =1, and the second emission control transistor ML2 is turned off. CB =1, the first switching transistor M1 is turned off. The first input terminal of the first nor gate NO1 is maintained at a low level, CK =0, so that the first nor gate NO1 outputs a high level signal and the first gray scale signal terminal L1 outputs a low level signal. CK =0, the second switching transistor M2 is turned on, and the low level signal output from the first gray level signal terminal L1 is provided to the first input terminal of the first nor gate NO 1. CK =0, the third switching transistor M3 is turned on, and provides a low level signal to the first input terminal of the second nor gate NO2, CB =1, so that the second nor gate NO2 outputs a low level signal, the second grayscale signal terminal L2 outputs a high level signal, and the third grayscale signal terminal L3 and the fourth grayscale signal terminal L4 still output a high level signal. For the light emitting module with the first gray scale switch transistor Mg1 turned on, the first gray scale switch transistor Mg1 provides the low level signal output by the first gray scale signal terminal L1 to the control terminal of the first light emitting control transistor ML1 to turn on the first light emitting control transistor ML1, and provides the high level signal of the first reference signal terminal VGH to the gate of the driving transistor TFT to turn off the driving transistor, so that the light emitting module stops emitting light.

In the light-emitting third stage t7, STV =1, cb =0, ck =1.STV =1, and the second emission control transistor ML2 is turned off. The first switching transistor M1 is turned on to supply a high level signal to the first input terminal of the first nor gate NO1, CK =1, so that the first nor gate NO1 outputs a low level signal and the first gray scale signal terminal L1 outputs a high level signal. The first input terminal of the second nor gate NO2 is maintained as a low level signal, CB =0, so that the second nor gate NO2 outputs a high level signal and the second gray scale signal terminal L2 outputs a low level signal. The fifth switching transistor M5 is turned on, and provides a low level signal to the first input terminal of the third nor gate NO3, CK =1, so that the third nor gate NO3 outputs a low level signal, and the third gray-scale signal terminal L3 outputs a high level signal, and the fourth gray-scale signal terminal L4 still keeps outputting a high level signal. For the light emitting module with the second gray-scale switching transistor Mg2 turned on, the second gray-scale switching transistor Mg2 provides the low level signal output by the second gray-scale signal terminal L2 to the control terminal of the first light emitting control transistor ML1 to turn on the first light emitting control transistor ML1, and provides the high level signal of the first reference signal terminal VGH to the gate of the driving transistor TFT to turn off the driving transistor TFT, so that the light emitting module stops emitting light.

In the fourth stage t8 of light emission, STV =1,cb =1,ck =0.STV =1, and the second emission control transistor ML2 is turned off. The first input terminal of the first nor gate NO1 holds a high level signal, CK =1, so that the first nor gate NO1 outputs a low level signal and the first gray scale signal terminal L1 outputs a high level signal. The third switching transistor M3 is turned on to supply a high level signal to the first input terminal of the second nor gate NO1, CB =1, so that the second nor gate NO2 outputs a low level signal and the second gray scale signal terminal L2 outputs a high level signal. The first input terminal of the third nor gate NO3 is maintained at the low level signal, CK =0, so that the third nor gate NO3 outputs the high level signal and the third grayscale signal terminal L3 outputs the low level signal. The sixth switching transistor M6 is turned on to supply a low level signal to the first input terminal of the third nor gate NO 3. The seventh switching transistor M7 is turned on to supply the low level signal to the first input terminal of the fourth nor gate NO4, CB =1, so that the fourth nor gate NO4 outputs the low level signal and the fourth grayscale signal terminal L4 outputs the high level signal. For the light emitting module with the third gray scale switch transistor Mg3 turned on, the third gray scale switch transistor Mg3 provides the low level signal output by the third gray scale signal terminal L3 to the control terminal of the first light emitting control transistor ML1 to turn on the first light emitting control transistor ML1, and provides the high level signal of the first reference signal terminal VGH to the gate of the driving transistor TFT to turn off the driving transistor TFT, so that the light emitting module stops emitting light.

In the fifth light-emitting phase t9, STV =1, cb =0, ck =1.STV =1, and the second emission control transistor ML2 is turned off. The first gray-scale signal terminal L1 and the second gray-scale signal terminal L2 keep outputting high level signals. The fifth switching transistor M5 is turned on to supply a high level signal to the first input terminal of the third nor gate NO3, CK =1, so that the third nor gate NO3 outputs a low level signal and the third gray scale signal terminal L3 outputs a high level signal. The first input terminal of the fourth nor gate NO4 holds the low level signal, CB =0, so that the fourth nor gate NO4 outputs the high level signal and the fourth grayscale signal terminal L4 outputs the low level signal. For the light emitting module with the fourth gray scale switch transistor Mg4 turned on, the fourth gray scale switch transistor Mg4 provides the low level signal output by the fourth gray scale signal terminal L4 to the control terminal of the first light emitting control transistor ML1 to turn on the first light emitting control transistor ML1, and provides the high level signal of the first reference signal terminal VGH to the gate of the driving transistor TFT to turn off the driving transistor TFT, so that the light emitting module stops emitting light.

In summary, the light emitting module turned on by the first gray-scale switching transistor Mg1 stops emitting light at the second light emitting stage t6, the light emitting module turned on by the second gray-scale switching transistor Mg2 stops emitting light at the third light emitting stage t7, the light emitting module turned on by the third gray-scale switching transistor Mg3 stops emitting light at the fourth light emitting stage t8, and the light emitting module turned on by the fourth gray-scale switching transistor Mg4 stops emitting light at the fifth light emitting stage t 9. The light emitting time of the light emitting module is divided into four conditions, so that different gray scale display is realized.

A gray scale control module can provide gray scale signals to the plurality of rows of light emitting modules, so that the display panel can be driven by Global timing. Specifically, in the display panel as shown in fig. 3, the gray scale control module supplies gray scale signals to four rows of light emitting modules. Alternatively, a gray scale control module may provide gray scale signals to only one row of light emitting modules, so that the display panel may be driven in sequential timing.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A display panel is characterized by comprising a substrate base plate, a plurality of light emitting modules, at least one gray scale control module, at least one row selection module and a plurality of data input modules, wherein the light emitting modules, the at least one gray scale control module, the at least one row selection module and the plurality of data input modules are formed on the substrate base plate;

the gray scale control module is configured to provide gray scale signals to the electrically connected light emitting modules through the m gray scale signal ends according to signals of the trigger signal ends, wherein m is more than or equal to 1 and is an integer;

the light emitting module is configured to receive the data signal and the gray scale signal and emit light under the control of the data signal and the gray scale signal;

the light-emitting module comprises a data latch module, a light-emitting drive module and a light-emitting device;

the data latch module is configured to latch the received data signal and provide the data signal to the light-emitting driving module under the control of the selection signal;

the light-emitting driving module is configured to receive the data signal and a plurality of gray scale signals and drive the light-emitting device to emit light according to the received gray scale signals under the control of the data signal.

2. The display panel according to claim 1, wherein the light emission driving module includes: the display device comprises m gray scale switch transistors, a first light emitting control transistor, a second light emitting control transistor, a storage capacitor and a driving transistor;

the first end of the second light-emitting control transistor is electrically connected with a second reference signal end, the control end of the second light-emitting control transistor is electrically connected with the trigger signal end, and the second end of the second light-emitting control transistor is electrically connected with the grid electrode of the driving transistor;

3. The display panel according to claim 2, wherein the data latch module includes: m data switching transistors and m latches;

and the second ends of the m latches are electrically connected with the control ends of the m gray-scale switch transistors in a one-to-one correspondence manner.

4. The display panel according to claim 3, wherein the latch includes a first inverter and a second inverter;

5. The display panel according to any one of claims 1 to 4, wherein the plurality of light emitting modules are divided into a plurality of row groups; one of the row groups includes four rows of the light emitting modules, and the light emitting modules included in different row groups are different;

one row selection module is electrically connected with the four rows of light-emitting modules in one row group;

one of the gray scale control modules is electrically connected with the four rows of light emitting modules in one of the row groups;

6. The display panel according to claim 5, wherein m =4, and the 4 gray scale signal terminals of the gray scale control module include a first gray scale signal terminal, a second gray scale signal terminal, a third gray scale signal terminal, and a fourth gray scale signal terminal; the gray scale control module comprises: the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, the sixth switch transistor, the seventh switch transistor, the eighth switch transistor, the first NOR gate, the second NOR gate, the third NOR gate, the fourth NOR gate, the first gray-scale inverter, the second gray-scale inverter, the third gray-scale inverter and the fourth gray-scale inverter;

the second end of the first gray scale phase inverter is electrically connected with the first gray scale signal end;

a second input end of the second nor gate is electrically connected with a first clock signal end, and an output end of the second nor gate is electrically connected with a first end of the second gray-scale phase inverter;

a first end of the fourth switching transistor is electrically connected with a second end of the third switching transistor, a control end of the fourth switching transistor is electrically connected with the first clock signal end, and a second end of the fourth switching transistor is electrically connected with the second gray-scale signal end;

a first end of the fifth switching transistor is electrically connected with the second gray scale signal end, a control end of the fifth switching transistor is electrically connected with the first clock signal end, and a second end of the fifth switching transistor is electrically connected with a first input end of the third nor gate;

a second end of the third gray scale inverter is electrically connected with the third gray scale signal end;

a second end of the fourth gray-scale phase inverter is electrically connected with the fourth gray-scale signal end;

7. The display panel of claim 5, wherein m =4, and the 4 data signal terminals of the data input module comprise: a first data signal terminal, a second data signal terminal, a third data signal terminal and a fourth data signal terminal; the data input module includes: the first NAND gate is connected with the first inverter and the second inverter; the data control end comprises a first data control end and a second data control end;

and the first end of the fourth inverter is electrically connected with the second data control end.

8. The display panel of claim 5, wherein the plurality of selection signal terminals of the row selection module comprise: the first selection signal end, the second selection signal end, the third selection signal end and the fourth selection signal end; the row selection module comprises: a fifth inverter, a sixth inverter, a fifth nand gate, a sixth nand gate, a seventh nand gate, an eighth nand gate, a first or gate, a second or gate, a third or gate, and a fourth or gate; the selection control end comprises a first selection control end, a second selection control end and a third selection control end;

a first input end of the sixth nand gate is electrically connected with a first selection control end, a second input end of the sixth nand gate is electrically connected with a second end of the sixth inverter, and an output end of the sixth nand gate is electrically connected with the second selection signal end;

a first end of the sixth inverter is electrically connected to the second selection control end.

9. A driving method of the display panel according to any one of claims 1 to 8, comprising:

in the data writing stage, a signal of a second level is loaded on a trigger signal end, the row selection module is controlled to sequentially load a signal of a first level on each selection signal end, the gray scale control module is controlled to load a signal of a second level on each gray scale signal end, and the data input module is controlled to provide a data signal for each data signal end;