CN214336296U

CN214336296U - LED drive circuit

Info

Publication number: CN214336296U
Application number: CN202023312104.6U
Authority: CN
Inventors: 刘召军; 吕志坚; 何先顺; 陈锐; 黄利将; 盘福波; 叶嘉豪
Original assignee: Shenzhen Stan Technology Co Ltd
Current assignee: Shenzhen Stan Technology Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-10-01
Anticipated expiration: 2030-12-31

Abstract

The embodiment of the utility model discloses LED drive circuit, include: a signal receiving module for receiving a row drive signal, a first column drive signal, and a second column drive signal; a signal holding module for holding the first column drive signal according to the row drive signal; the adjusting module is connected with the LED chip and used for receiving an adjusting signal and driving the LED chip to emit light according to the first row of driving signals, the second row of driving signals and the adjusting signal. The embodiment of the utility model provides a LED drive circuit can realize the drive of high pixel density and the Micro-LED display screen of large tracts of land simultaneously, can realize low-power consumption and efficient drive simultaneously, makes the Micro-LED display module group have better luminance homogeneity and contrast.

Description

LED drive circuit

Technical Field

The embodiment of the utility model provides a relate to the semiconductor technology field, especially relate to a LED drive circuit.

Background

Micro Light-Emitting diodes (Micro-LEDs) have self-luminous display characteristics, are all-solid-state LEDs, have long life, high brightness, low power consumption, small size, and ultra-high resolution, can be applied to extreme environments such as high temperature or radiation, and are planned as a new generation of display technology by more and more manufacturers.

The product morphology of Micro-LED can be divided into two directions: a Micro-display of high pixel density (PPI (Pixels Per inc) >1000) Micro-LED array and a larger size display screen of low pixel density (PPI <1000) Micro-LED array. The driving method for the Micro-LED is classified into a high pixel density display driving and a low pixel density display driving. However, neither the high pixel density display driving nor the low pixel density display driving can achieve driving of a large area display screen of high pixel density.

SUMMERY OF THE UTILITY MODEL

In view of this, the embodiment of the present invention provides an LED driving circuit to realize the driving of the Micro-LED array with high pixel density and large area.

An embodiment of the utility model provides a LED drive circuit, include:

a signal receiving module for receiving a row drive signal, a first column drive signal, and a second column drive signal;

a signal holding module for holding the first column drive signal according to the row drive signal;

the adjusting module is connected with the LED chip and used for receiving an adjusting signal and driving the LED chip to emit light according to the first row of driving signals, the second row of driving signals and the adjusting signal.

Furthermore, the signal receiving module includes a first NMOS transistor and a second NMOS transistor, a gate of the first NMOS transistor is connected to a gate of the second NMOS transistor and is configured to receive a row driving signal, a drain of the first NMOS transistor is configured to receive a first column driving signal, and a drain of the second NMOS transistor is configured to receive a second column driving signal.

Further, the signal holding module comprises a first PMOS transistor, a second PMOS transistor, a third NMOS transistor and a fourth NMOS transistor;

the grid electrode of the first PMOS tube, the grid electrode of the third NMOS tube, the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube are connected;

the grid electrode of the second PMOS tube, the grid electrode of the fourth NMOS tube, the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube are connected;

the grid electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube;

the drain electrode of the first PMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the fourth NMOS tube;

the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are both connected with the anode of the working power supply;

and the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are both connected with the negative electrode of the working power supply.

Furthermore, the adjusting module comprises a third PMOS tube and a fourth PMOS tube, the grid electrode of the third PMOS tube is used for receiving adjusting signals, the source electrode of the third PMOS tube is connected with the anode of the working power supply, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third NMOS tube, and the drain electrode of the fourth PMOS tube is connected with the LED chip.

Further, the LED driving circuit further includes a column scanning module, the column scanning module includes a shift register and a latch, a data input end of the shift register receives a column control signal, a data output end of the shift register is connected to a data input end of the latch, and a data output end of the latch outputs a first column driving signal.

Further, the first column driving signal is input into an inverter to obtain a second column driving signal.

Further, the LED driving circuit further comprises an adjustment signal generating circuit, wherein the adjustment signal generating circuit comprises a control circuit, a current adjusting circuit, a decoder circuit and a mirror circuit;

the current regulating circuit is used for generating a regulating current;

the mirror circuit is used for copying the regulating current to generate a plurality of mirror currents;

the decoder circuit includes a plurality of switches, and generates a regulation signal based on a plurality of the mirror currents according to the number of closed switches;

the control circuit is used for outputting the adjusting signal according to the control signal.

Furthermore, the current regulating circuit comprises a power supply, a current adder, a current subtracter and an NMOS tube; the current adder is used for generating a current adding signal, the current subtracter is used for generating a current subtracting signal, the current adding signal and the current subtracting signal are subtracted to generate an adjusting current, and the adjusting current is input to the mirror image circuit through the power supply and the NMOS tube.

Furthermore, the mirror circuit comprises a plurality of NMOS tubes, the base electrode of each NMOS tube is connected with the current regulating circuit, the source electrode of each NMOS tube is grounded, and the drain electrode of each NMOS tube is connected with a corresponding switch in the decoder circuit.

Furthermore, the decoder circuit further comprises a plurality of decoders connected in series, and the data output end of each decoder is connected with the data input end of the next decoder after being connected with one switch.

The embodiment of the utility model provides a LED drive circuit can realize the drive of high pixel density and the Micro-LED display screen of large tracts of land simultaneously, can realize low-power consumption and efficient drive simultaneously, makes the Micro-LED display module group have better luminance homogeneity and contrast.

Drawings

Fig. 1 is a schematic block diagram of an LED driving circuit according to a first embodiment of the present invention;

fig. 2 is a circuit structure diagram of an LED driving circuit according to a first embodiment of the present invention;

fig. 3 is a circuit structure diagram of a column scanning sub-circuit according to a second embodiment of the present invention;

fig. 4 is a circuit structure diagram of a line scanning circuit according to a third embodiment of the present invention;

fig. 5 is a circuit structure diagram of a regulating signal generating circuit according to a fourth embodiment of the present invention;

fig. 6 is a circuit structure diagram of a current regulating circuit according to a fourth embodiment of the present invention;

fig. 7 is a circuit structure diagram of a decoder circuit according to a fourth embodiment of the present invention;

fig. 8 is a timing diagram of a column scanning sub-circuit according to a fifth embodiment of the present invention;

fig. 9 is a timing diagram of a line scanning circuit according to a fifth embodiment of the present invention;

fig. 10 is a timing diagram of row-column scanning of an LED driving circuit according to a fifth embodiment of the present invention;

fig. 11 is a timing diagram of a refresh rate of 120Hz according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or circuits depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a circuit, a function, a procedure, a subroutine, a subprogram, etc.

Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "plurality", "batch" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Example one

Fig. 1 is a schematic diagram of an LED driving circuit according to an embodiment of the present invention, which is applicable to driving a Micro-LED array with a high pixel density and a large area, such as driving a Micro-LED matrix with a pixel density of 5000PPI and a resolution of 1920x 1080.

As shown in fig. 1, a first embodiment of the present invention provides an LED driving circuit, which includes: the signal receiving module 10 is used for receiving a row driving signal, a first column driving signal and a second column driving signal; the signal holding module 20 is configured to hold a first column driving signal according to a row driving signal; the adjusting module 30 is connected to the LED chip, and the adjusting module 30 is configured to receive the adjusting signal and drive the LED chip to emit light according to the first row driving signal, the second row driving signal, and the adjusting signal.

The row driving signal is a driving signal of a row where the LED chip is located in the LED array, the first column driving signal is a driving signal of a column where the LED chip is located in the LED array, and the second column driving signal and the first column driving signal are opposite signals. The adjusting signal is used for adjusting the light emitting brightness of the LED chip. The signal holding module 20 can hold the first column driving signal for a period of time, thereby prolonging the light emitting time of the LED chip and making the light emission of the display screen more uniform.

Further, refer to fig. 2. Fig. 2 is a circuit diagram of an LED driving circuit according to an embodiment of the present invention.

The signal receiving module 10 includes a first NMOS transistor NMOS1 and a second NMOS transistor NMOS 2. The gate of the first NMOS transistor NMOS1 and the gate of the second NMOS transistor NMOS2 are connected to receive the Row driving signal Row1, the drain of the first NMOS transistor NMOS1 is used to receive the first column driving signal Data1, and the drain of the second NMOS transistor NMOS2 is used to receive the second column driving signal Data _ 1.

The signal holding module 20 comprises a first PMOS transistor PMOS1, a second PMOS transistor PMOS2, a third NMOS transistor NMOS3 and a fourth NMOS transistor NMOS 4; the grid electrode of the first PMOS tube PMOS1, the grid electrode of the third NMOS tube NMOS3, the drain electrode of the second PMOS tube PMOS2 and the drain electrode of the fourth NMOS tube NMOS4 are connected; the grid electrode of the second PMOS tube PMOS2, the grid electrode of the fourth NMOS tube NMOS4, the drain electrode of the first PMOS tube PMOS1 and the drain electrode of the third NMOS tube NMOS3 are connected; the grid electrode of the third NMOS transistor NMOS3 is connected with the source electrode of the first NMOS transistor NMOS1, and the grid electrode of the fourth NMOS transistor NMOS4 is connected with the source electrode of the second NMOS transistor NMOS 2; the drain electrode of the first PMOS tube PMOS1 is connected with the drain electrode of the third NMOS tube NMOS3, and the drain electrode of the second PMOS tube PMOS2 is connected with the drain electrode of the fourth NMOS tube NMOS 4; the source electrode of the first PMOS transistor PMOS1 and the source electrode of the second PMOS transistor PMOS2 are both connected with the positive electrode VDD of the working power supply; the source electrode of the third NMOS transistor NMOS3 and the source electrode of the fourth NMOS transistor NMOS4 are both connected with the negative electrode VSS of the working power supply.

The adjusting module 30 comprises a third PMOS transistor PMOS3 and a fourth PMOS transistor PMOS4, a gate of the third PMOS transistor PMOS3 is used for receiving an adjusting signal Iref, a source of the third PMOS transistor PMOS3 is connected with a positive electrode of a working power supply, a drain of the third PMOS transistor PMOS3 is connected with a source of the fourth PMOS transistor PMOS4, a gate of the fourth PMOS transistor PMOS4 is connected with a gate of the third NMOS transistor NMOS3, and a drain of the fourth PMOS transistor PMOS4 is connected with the LED chip.

In the LED driving circuit shown in fig. 2, when the Row driving signal Row1 is 0, the EN signal remains in the original state, i.e., 0 or 1.

When the Row driving signal Row1 is equal to 1, the first column driving signal Data1 and the second column driving signal Data _1 are transmitted to the signal holding module 20, so that the EN signal follows the second column driving signal Data _ 1.

When the Row driving signal Row1 is equal to 1, the first column driving signal Data1 is equal to 1, and the second column driving signal Data _1 is equal to 0, EN is equal to 0 at this time, the fourth PMOS transistor PMOS4 is turned on, and the first column driving signal Data1 controls the state of the LED chip in combination with the adjusting signal Iref signal. The larger the voltage (VDD-Iref) of the adjusting signal Iref is, the larger the current flowing through the LED chip is, the larger the brightness of the LED chip is, so that the brightness of the LED chip can be adjusted by changing the adjusting signal Iref.

The embodiment of the utility model provides a LED drive circuit is the drive circuit of single LED chip, and when the drive LED array, every LED chip all connects the utility model provides a LED drive circuit. According to the number n of the LED chips in the LED array, the corresponding row driving signal is recorded as Rown, the first column driving signal is recorded as Datan, and the second column driving signal is recorded as Data _ n.

Example two

Referring to fig. 3, on the basis of the above embodiment, the LED driving circuit according to the second embodiment of the present invention further includes a column scanning module 40. The column scan block 40 comprises a shift register diff1 and a latch diff _ D1, the Data input D of the shift register diff1 receiving the column control signal Data, the Data output of the shift register diff1 being connected to the Data input D1 of the latch, the Data output of the latch diff _ D1 outputting the first column drive signal Data 1.

The shift register diff1 also includes a reset terminal R and a clock signal terminal C, and the latch diff _ d1 also includes a reset terminal R1 and a clock signal terminal C1. The Reset terminal R of the shift register diff1 is connected to the same Reset signal Reset as the Reset terminal R1 of the latch diff _ D1, the clock signal terminal C of the shift register diff1 is connected to the first clock signal CLK _ D, and the clock signal terminal C1 of the latch diff _ D1 is connected to the second clock signal CLK _ L.

When the column scan module 40 is in operation, when the first clock signal CLK _ D is rising, the Data output terminal of the shift register diff1 samples the column control signal Data received by the Data input terminal D, and the sampled Data is stored at the Data output terminal. Meanwhile, when the second clock signal CLK _ L is rising, the Data output terminal of the latch diff _ d1 samples the signal at the Data output terminal of the shift register diff1, and outputs the first column driving signal Data 1. The first column driving signal Data1 is input to the drain of the first NMOS transistor NMOS1 of the signal receiving module. Meanwhile, the first column driving signal Data1 is further input to an inverter (not shown in the figure), a second column driving signal Data _1 opposite to the first column driving signal Data1 is obtained, and the second column driving signal Data _1 is input to the drain of the second NMOS transistor NMOS2 of the signal receiving module.

In this embodiment, the column scanning module 40 is a column signal generating circuit in the LED driving circuit corresponding to a single LED chip. When the LED array is driven, a plurality of column scanning modules 40 are connected in series to form a column scanning sub-circuit, as shown in fig. 3, the column scanning sub-circuit is a column signal generating circuit for a part of LED chips in the LED array, and a column scanning circuit formed by a plurality of parallel column scanning sub-circuits is a column signal generating circuit for all LED chips in the LED array.

Referring to fig. 3, in the column scan sub-circuit, n column scan blocks 40 are included, and the nth column scan block 40 includes a shift register diffn and a latch diff _ dn. The Reset terminals R of all the shift registers (diff 1-diff) and the Reset terminals R1 of all the latches (diff _ D1-diff _ dn) are all connected with the same Reset signal Reset, the clock signal terminals C of all the shift registers (diff 1-diff) are connected with the first clock signal CLK _ D, and the clock signal terminals C1 of all the latches (diff _ D1-diff _ dn) are connected with the second clock signal CLK _ L. The data input end D of the shift register diffi of the ith column scanning module is connected with the data output end of the shift register diffi-1 of the (i-1) th column scanning module. The Data output end of the latch diff _ di of the ith column scanning module outputs the first column driving signal Datai to the drain of the first NMOS transistor NMOS1 of the signal receiving module 10 of the ith LED chip, and the second column driving signal Data _ i obtained by the inverter is input to the drain of the second NMOS transistor NMOS2 of the corresponding signal receiving module 10.

EXAMPLE III

Referring to fig. 4, on the basis of the above embodiment, the LED driving circuit provided by the third embodiment of the present invention further includes a line scanning module 60. The line scan module includes a register diff1, which includes an input terminal, a Reset terminal, a clock signal terminal and an output terminal, wherein the Reset terminal is connected to the Reset signal Reset, the clock signal terminal is connected to the clock signal CLK, and the input terminal is connected to the line signal Vscan. When the clock signal CLK is at the rising edge, the register diff1 samples the Row signal Vscan at the input end, and the output end outputs the Row driving signal Row1 to the gate of the first NMOS transistor NMOS1 and the gate of the second NMOS transistor NMOS2 of the signal receiving module 10.

The line scanning module 60 is a line driving signal generating circuit corresponding to a single LED chip, and when the LED array is driven, n line scanning modules 60 are connected in series to form a line scanning circuit of the entire LED array, as shown in fig. 4. The Reset ends of all registers (diff 1-diffn) are connected with a Reset signal Reset, the clock signal ends of all registers (diff 1-diffn) are connected with a clock signal CLK, the input end of the 1 st register diff1 is connected with a line signal Vscan, the input end of the ith register diffi is connected with the output end of the (i-1) th register diffi-1, and the output end of the ith register diffi outputs a line driving signal Rowi to the gate of the first NMOS tube NMOS1 and the gate of the second NMOS tube NMOS2 of the signal receiving module 10 corresponding to the ith LED chip.

Example four

Referring to fig. 5, on the basis of the above embodiment, the LED driving circuit provided by the fourth embodiment of the present invention further includes an adjustment signal generating circuit. The adjustment signal generation circuit includes a control circuit 54, a current adjustment circuit 51, a decoder circuit 53, and a mirror circuit 52, and the mirror circuit 52 is connected to the control circuit 54 through the decoder circuit 53.

The current regulating circuit 51 generates a regulated current Iin. Further, the specific structure of the current regulation circuit 51 can refer to fig. 5. As shown in fig. 6, the current adjusting circuit 51 includes a power supply 511, a current adder 512, a current subtractor 513, and an NMOS transistor NM 0. The current adder 512 includes two inputs: a current input terminal I _ plus, the current signal of which is active on the rising edge, and a reset terminal I _ reset, which outputs a current plus signal Ip. The current subtractor 513 includes two input terminals: a current input terminal I _ minus, the current signal of which is active on the rising edge, and a reset terminal I _ reset, which outputs a current minus signal In. The current addition signal Ip and the current subtraction signal In are subtracted to obtain a regulated current Iin, i.e., Iin — Ip-In, which is then input to the NMOS transistor NM0 through the power supply 511. Reset signal to reset terminal I _ reset: 0-0V, 1-vdd, and the maximum regulating order of the regulating current Iin is +/-20.

Further, the current regulation circuit 51 operates according to the following principle: the reset signal is 0, and the adjustment current Iin is reset. The reset signal is 1, the current signal at the current input terminal I _ plus of the current adder 512 is 0, and the rising edge of the current signal at the current input terminal I _ minus of the current subtractor 513 may decrease the adjustment current Iin. The reset signal is 1, the current signal at the current input terminal I _ plus of the current adder 512 is 1, and the rising edge of the current signal at the current input terminal I _ minus of the current subtractor 513 resets the adjustment current Iin. The reset signal is equal to 1, the current input terminal I _ minus of the current subtractor 513 is equal to 0, and the rising edge of the current signal at the current input terminal I _ plus of the current adder 512 may increase the adjustment current Iin. The reset signal is 1, the current input terminal I _ minus of the current subtractor 513 is 1, and the rising edge of the current signal at the current input terminal I _ plus of the current adder 512 resets the current Iin.

The mirror circuit 52 includes a plurality of NMOS transistors (NM 1-NMn), each of which can copy the adjustment current Iin to obtain a mirror current of the same magnitude. The decoder circuit 53 includes a plurality of switches S1 to Sn, and each NMOS transistor in the mirror circuit 52 is connected to one switch in the decoder circuit 53. When the switches in the decoder circuit 53 are closed, the mirror currents corresponding to the NMOS transistors are input to the decoder circuit 53, and then the number of closed switches, that is, the number of mirror currents input to the decoder circuit 53, are added to obtain the adjustment signal Iref, and if the number of closed switches is N, then Iref is Iin N.

Further, referring to fig. 7, a specific circuit diagram of the decoder circuit 53 is shown. The decoder circuit 53 includes a plurality of decoders diff 1-diffn each including an input terminal D, a reset terminal R, a clock signal terminal C, and an output terminal, and a plurality of switches S1-Sn. The Reset ends of all decoders are connected with a Reset signal Reset _ I, the clock signal ends of all decoders are connected with a counting signal Data _ I, the Data input end of the first decoder diff1 is connected with the anode VDD of the working power supply, and the input end of the ith decoder diffi is connected with the output end of the (I-1) th decoder diffi-1 through a switch Si-1. Resetting when the Reset signal Reset _ I is at a low level, wherein the number of closed switches is 0 after resetting, and then the adjusting signal Iref is 0; when the Reset signal Reset _ I is at a high level, the decoder circuit 53 starts counting, and when the rising edge of the count signal Data _ I is increased by 1, the number of closed switches S is increased by 1, and when the number of closed switches is equal to N, Iref is Iin N.

The control circuit 54 includes two PMOS transistors: the drain electrodes of the PMS and the PMO are connected and connected with the output end of the decoder circuit 53, the source electrodes of the PMS and the PMO are both connected with the working current anode VDD, the grid electrode of the PMS is the input end of a control signal Switch _ I, and the grid electrode of the PMO is the output end of a regulating signal Iref. The control signal Switch _ I is a switching signal for controlling whether the adjustment signal Iref obtained by the decoder circuit 53 is output, and when the control signal Switch _ I is at a high level, the gate of the PMO outputs the adjustment signal Iref ═ Iin × N; when the control signal Switch _ I is low, the gate of the PMO outputs the adjustment signal Iref — 0.

EXAMPLE five

The structure of the LED driving circuit according to an embodiment of the present invention is described below with reference to fig. 2 to 10.

In one embodiment, a Micro-LED array with a driving pixel density of 5000ppi and a resolution of 1920x1080 is taken as an example. Each LED chip in the Micro-LED array is connected to an LED driver circuit as shown in fig. 2.

The column scanning circuit in the LED driving circuit of the Micro-LED array is composed of 20 column scanning sub-circuits as shown in fig. 3, each column scanning sub-circuit includes 96 column scanning modules 40, and there are 96 shift registers and 96 latches. In each column scanning sub-circuit, the clock signal terminals C of all the shift registers (diff 1-diffn) are connected with a first clock signal CLK _ D; the clock signal end C1 of all the latches (diff _ d 1-diff _ dn) is connected with the second clock signal CLK _ L; the Data input terminal D of the shift register diff1 of the 1 st column scan block 40 is connected to the column control signal Data, and the Data input terminal D of the shift register diffi of the i-th column scan block 40 is connected to the Data output terminal of the shift register diffi-1 of the i-1 st column scan block (2 < i < 95). Each column scanning sub-circuit has a corresponding column control signal Data, and the column scanning circuits have 20 column control signals Data, which are recorded as Da <1:20 >. Each column scanning sub-circuit outputs 96 first column driving signals Data1 to Data96, 96 first column driving signals Data _1 to Data _96 are obtained after the input of an inverter, and a column scanning circuit composed of 20 column scanning sub-circuits outputs 1920 first column driving signals and the first column driving signals.

When the column scanning sub-circuit works, the rising edge of the first clock signal CLK _ D samples the column control signal Data, 1 is added to the rising edge of the first clock signal CLK _ D, and the column control signal Data is shifted from the shift register diffi to diffi +1 by 1, so that the first-in first-out operation is realized. Every 96 rising edges, the column scanning subcircuit finishes sampling 96-bit data, the 96-bit data is recorded as D <1:96> from left to right, and the data D <1:96> is temporarily stored at the output of each latch of the shift register until the next rising edge of the first clock signal CLK _ D. The rising edge of the second clock signal CLK _ L latches the 96-bit data D <1:96> registered by the shift register to the output of the latch to obtain the corresponding first column driving signal, which is recorded as data <1:96> from left to right until the next rising edge of the second clock signal CLK _ L. The timing diagram of the column scanning sub-circuit is shown in fig. 8.

Since the 20 column scan sub-circuits share the first clock signal CLK _ D and the second clock signal CLK _ L, 96 rising edges of the first clock signal CLK _ D complete data sampling from the 1 st column to the 1920 columns, and 1 rising edge of the second clock signal CLK _ L stores the sampled data of the 1 st column to the 1920 columns at the output of the latch.

The row scanning circuit in the LED driving circuit of the Micro-LED array is composed of 1080 registers as shown in fig. 4. The Reset terminals of all the registers (diff 1-diffn) are connected with a Reset signal Reset, the clock signal terminals of all the registers (diff 1-diffn) are connected with a clock signal CLK, the input terminal of the 1 st register diff1 is connected with a line signal Vscan, and the input terminal of the ith register diffi is connected with the output terminal of the (i-1) th register diffi-1. The line scanning circuit outputs 1080 line driving signals Row1 to Row1080, and sequentially lines 1 by line, that is, Row of one line is 1, and rows of the other 1079 lines are 0. When Row of a certain Row is equal to 1, the first column driving signal Data <1:1920> Data of the Row is read at the same time and transmitted to the signal receiving module and the signal holding module.

The Row scanning circuit operates to Reset when the Reset signal Reset is at a low level, and outputs Row1-1080 after Reset as 0. When the Reset signal Reset is at a high level, the clock signal CLK rises to sample, and the data signal at the input end of the register is transmitted to the output end to form Row driving signals Row 1-Row 1080. The remaining state output signal remains. Fig. 9 is a timing chart of the row scanning circuit.

When the row driving signal Rowi is at a high level, signals at the output ends (1920 outputs) of the latches are transmitted to the corresponding signal receiving circuits at the ith row, and finally Data transmission to the signal holding circuits is achieved. The above process is circulated 1080 times, and then the 1920 × 1080 pixel matrix reads the adjusting signal Iref simultaneously, so that the Micro-LED matrix is scanned by one subfield, the subfield scanning time plus the light emitting time is one subfield time, 8 subfields constitute 1 frame of picture, and fig. 10 is a row-column scanning timing chart.

The adjusting signal generating circuit comprises 512 NMOS transistors, namely NM 0-NM 511. NM0 and NM 1-NM 511 constitute a mirror image transistor copy of the adjusting current Iin flowing through NM0 (S1-S511 are closed), when the control signal Switch _ I is high, the adjusting signal Iref is equal to the sum of the currents flowing through NM 1-NM 511 (Iref 511-Iin). When the control signal Switch _ I is low, the adjustment signal Iref is 0.

Further, the LED driving circuit provided in this embodiment may implement 256 levels of gray scale adjustment of a Micro-LED array with a pixel density of ultrahigh resolution, for example, 256 levels of gray scale adjustment of a Micro-LED array with a resolution of 1920 × 1080 at 5000 ppi. The gray level adjusting method mainly comprises the following steps: PWM (Pulse-Width Modulation), PAM (Pulse-Amplitude Modulation), and PFM (Pulse-Frequency Modulation).

PWM is the adjustment of the width of the light emitting area of each subfield. In this embodiment, 1 frame of picture is composed of 8 subfields (denoted as subfields 1 to 8), the light emitting region width ratio of the 8 subfields is set to 1:2:4:8:16:32:64:128, and Data input to the 8 subfields is denoted as d1 to d 8. The gray scale calculation method is as follows: the Gray scale (Gray) is 1 × d1+2 × d2+4 × d3+8 × d4+16 × d5+32 × d6+64 × d7+128 × d 8. When Data input to the subfield m is at a high level, dm is 1; when Data input to the subfield is at a low level, dm is 0. When Data input to all subfields are high level, if d 1-d 8 are all 1, Gray is 256; when Data input to all subfields are low, if d1 to d8 are all 0, Gray is 0.

PAM is the amplitude of the light emitting area adjustment signal Iref for each subfield. If the amplitude ratio of the light emitting area adjusting signals Iref of the subfields 1-8 is set to be 1:2:4:8:16:32:64:128, 256 levels of gray levels can be realized, and the calculation method is as follows: the Gray scale (Gray) is 1 × d1+2 × d2+4 × d3+8 × d4+16 × d5+32 × d6+64 × d7+128 × d 8. When Data input to the subfield m is at a high level, dm is 1; when Data input to the subfield is at a low level, dm is 0. When Data input to all subfields are high level, if d 1-d 8 are all 1, Gray is 256; when Data input to all subfields are low, if d1 to d8 are all 0, Gray is 0.

PFM adjusts the width of the scanning area of each subfield and fixes the amplitude of the adjusting signal Iref, and the width of the light emitting area is set to 0, i.e., the width of the scanning area is equal to the width of the subfield. Then, setting the width ratio of the subfields 1-8 to 1:2:4:8:16:32:64:128, 256-level gray scale can be realized, and the calculation method is as follows: the Gray scale (Gray) is 1 × d1+2 × d2+4 × d3+8 × d4+16 × d5+32 × d6+64 × d7+128 × d 8. When Data input to the subfield m is at a high level, dm is 1; when Data input to the subfield is at a low level, dm is 0. When Data input to all subfields are high level, if d 1-d 8 are all 1, Gray is 256; when Data input to all subfields are low, if d1 to d8 are all 0, Gray is 0.

Exemplary timing parameters using a PAM, 120Hz refresh rate are as follows:

for CLK _ D, its period T is 5ns and frequency f is 200 MHz;

for CLK _ L, its period T is 5 × 96 ns and frequency f is 2.08 MHz;

for CLK, its period T5 × 96 × 480ns and frequency f 2.08 MHz;

wherein t is 0-0.1 ns for the delay of CLK and CLK _ L;

the width of the subfield scanning area is equal to the width of the subfield light emitting area.

Each frame is composed of 8 sub-fields, T_CLK5ns, 20 split screen; t is_{frame_sub}＝T _CLK1080 × (1920/20) × 2 ═ 518.4us ═ 2 ═ 1.0368 ms; the address selection time of each sub-field Micro-LED array is 518.4us, and the light emitting time is 518.4 us; t is_frame＝T_{frame_sub}*8＝8.2944ms≈8.3ms， f_frame120 Hz. The timing diagram is shown in fig. 11.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims

1. An LED driving circuit, comprising:

2. The LED driving circuit according to claim 1, wherein the signal receiving module comprises a first NMOS transistor and a second NMOS transistor, a gate of the first NMOS transistor and a gate of the second NMOS transistor are connected and configured to receive a row driving signal, a drain of the first NMOS transistor is configured to receive a first column driving signal, and a drain of the second NMOS transistor is configured to receive a second column driving signal.

3. The LED driving circuit according to claim 2, wherein the signal holding module comprises a first PMOS transistor, a second PMOS transistor, a third NMOS transistor and a fourth NMOS transistor;

4. The LED driving circuit according to claim 3, wherein the adjusting module comprises a third PMOS transistor and a fourth PMOS transistor, a gate of the third PMOS transistor is used for receiving an adjusting signal, a source of the third PMOS transistor is connected to a positive electrode of a working power supply, a drain of the third PMOS transistor is connected to a source of the fourth PMOS transistor, a gate of the fourth PMOS transistor is connected to a gate of the third NMOS transistor, and a drain of the fourth PMOS transistor is connected to the LED chip.

5. The LED driving circuit of claim 1, further comprising a column scan module, the column scan module comprising a shift register and a latch, a data input of the shift register receiving a column control signal, a data output of the shift register being coupled to a data input of the latch, a data output of the latch outputting a first column drive signal.

6. The LED driver circuit of claim 5, wherein the first column drive signal is input into an inverter to obtain the second column drive signal.

7. The LED drive circuit according to claim 1, further comprising an adjustment signal generation circuit including a control circuit, a current adjustment circuit, a decoder circuit, and a mirror circuit;

the current regulating circuit is used for generating a regulating current;

8. The LED driving circuit according to claim 7, wherein the current regulating circuit comprises a power supply, a current adder, a current subtractor and an NMOS transistor; the current adder is used for generating a current adding signal, the current subtracter is used for generating a current subtracting signal, the current adding signal and the current subtracting signal are subtracted to generate an adjusting current, and the adjusting current is input to the mirror image circuit through the power supply and the NMOS tube.

9. The LED driving circuit according to claim 7, wherein the mirror circuit comprises a plurality of NMOS transistors, a base of each NMOS transistor is connected to the current regulating circuit, a source of each NMOS transistor is grounded, and a drain of each NMOS transistor is connected to a corresponding switch in the decoder circuit.

10. The LED driving circuit of claim 7, wherein the decoder circuit further comprises a plurality of decoders connected in series, the data output of each decoder being connected to a switch and then to the data input of the next decoder.