CN113777409A

CN113777409A - Distributed capacitive sensor system

Info

Publication number: CN113777409A
Application number: CN202110964601.4A
Authority: CN
Inventors: 孙滕谌; 张大华; 孟凡; 石万文
Original assignee: Beijing Tashan Technology Co ltd
Current assignee: Beijing Tashan Technology Co ltd
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2021-12-10

Abstract

A distributed capacitive sensor system is provided. A distributed capacitive sensor system is provided, comprising a plurality of nodes interconnected; each node of the plurality of nodes comprises: one or more analog signal ports; at least one of the plurality of nodes further comprises a capacitive-to-digital converter (CDC); at least one of the plurality of nodes further comprises one or more capacitive plates; the analog signal ports of the nodes are used for coupling the analog signal ports of other nodes; a first node of the plurality of nodes comprises a capacitive-to-digital converter (CDC) and one or more capacitive plates; the capacitance-to-digital converter of the first node applies a first excitation signal to one or more capacitance plates of the first node and obtains a first response to the first excitation signal from one or more first analog signal ports of the first node.

Description

Distributed capacitive sensor system

Technical Field

The present application relates to distributed capacitive sensor systems, and in particular to distributed capacitive sensor systems formed from node interconnections including a CDC (capacitive Digital Converter) located at different locations.

Background

Capacitive based sensors are widely used. Similar to ADC (Analog Digital Converter), CDC (capacitive Digital Converter) measures capacitance values and converts them to Digital outputs. Fig. 1 shows a schematic diagram of a capacitance measuring cell that measures capacitance using CDC.

The CDC includes an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC). Optionally, the CDC further includes a self-capacitance signal line port (SCA), an active shield signal line port (SHD), and/or a synchronous clock port (CLK). EXC stands for excitation source, e.g. a square wave signal source.

In one mode of operation, the two plates of the capacitor (Cm) being measured are connected to a stimulus signal line port (AEC) and a mutual capacitance input signal line port (ACC), respectively, to form a mutual capacitance measurement loop. The excitation source EXC is connected to an excitation signal line port (AEC), the CDC applies an excitation signal to the plates of the capacitance (Cm) through its excitation signal line port (AEC), and collects a response to the excitation signal acquired from the plates of the capacitance (Cm) through its mutual capacitance input signal line port (ACC), and measures the capacitance value of the capacitance (Cm) from the response. Since both plates of the capacitor (Cm) are connected to the CDC, the capacitor (Cm) is referred to as a mutual capacitance.

In a further operating mode, one plate of the capacitance (Cs) to be measured is connected to the self-capacitance signal line port (SCA), largely as the other plate of the capacitance (Cs) to be measured, and the self-capacitance measuring circuit is formed via the ground terminal (AGND) of the CDC. The capacitance (Cs) is referred to as the self-capacitance. The excitation source EXC is connected to a self-capacitance signal line port (SCA), and the CDC applies an excitation to the capacitance (Cs) through the self-capacitance signal line port (SCA) and obtains a response to measure a capacitance value thereof.

The CDC may apply a variety of capacitance measurement principles. By way of example, for a mutual capacitance (Cm), the CDC charges the capacitance (Cm) through its excitation signal line port (AEC), acquires the voltage value of the charged capacitance (Cm) through the mutual capacitance input signal line port (ACC), and accesses the sigma-delta modulator, after low-pass filtering, outputs a digital quantity representative of the voltage value of the capacitance (Cm) to be measured. As yet another example, an excitation signal source (denoted as EXC) within the CDC is dynamically connected to the self-capacitance signal line port (SCA) while disconnecting the self-capacitance signal line port (SCA) to, for example, a sigma-delta modulator within the CDC to charge the self-capacitance (Cs), and at a subsequent time, disconnecting the excitation signal source (EXC) from the self-capacitance signal line port (SCA) and turning on the self-capacitance signal line port (SCA) with the sigma-delta modulator to convert the voltage value of the capacitance (Cs) to a digital quantity representative of its capacitance value.

In some cases, a self-capacitance signal line port (SCA) of the CDC is replaced with a pump signal line port (AEC) or a mutual capacitance input signal line port (ACC), such that the CDC does not provide a separate self-capacitance signal line port (SCA). To replace the self-capacitance signal line port (SCA) with either the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), a switch is provided internally to the CDC. When the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) measure mutual capacitance, disconnecting the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) from a circuit for measuring self capacitance; and when the self-capacitance is measured by replacing the self-capacitance signal line port (SCA) with the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), connecting a circuit for measuring the self-capacitance (including an excitation source EXC) to the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), and disconnecting the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) from the circuit for measuring the mutual capacitance.

In still other cases, the CDC includes an actively shielded signal line port (SHD). For example, within the CDC, the excitation signal provided to the excitation signal line port (AEC) is provided to the active shield signal line port (SHD) through a follower. So that the output signal of the actively shielded signal line port (SHD) follows the output of the exciter signal line port (AEC). The active shielding signal line port (SHD) is used for coupling a shielding electrode, and the shielding electrode is adjacent to, covers or wraps a lead connecting the excitation signal line port (AEC) and the capacitor plate, so that signals transmitted on the lead connecting the excitation signal line port (AEC) and the capacitor plate are the same as the amplitude of signals transmitted by the active shielding signal line port (SHD), and have higher driving capability and lower internal impedance. The shielding electrode can reduce parasitic capacitance interference generated by a lead wire connected with a capacitance plate, avoid overlarge reference capacitance value and reduce the resolution of capacitance measurement.

Still by way of example, within the CDC, the active shield signal line port (SHD) is connected to the self-capacitance signal line port (SCA) via a follower, such that the output signal of the active shield signal line port (SHD) follows the signal output from the self-capacitance signal line port (SCA). And an active shielding signal provided by an active shielding signal line port (SHD) for coupling with the shielding electrode. The shielding electrode is adjacent to, covers or wraps a lead connecting the self-capacitance signal line port (SCA) and the capacitance plate, the electrode and the ground or between the electrode and a surrounding electric conductor, so that signals transmitted on the lead connecting the self-capacitance signal line port (SCA) and the capacitance plate are the same as the amplitude of signals transmitted by the active shielding signal line port (SHD), and the shielding electrode has larger driving capability and lower internal impedance. The shielding electrode reduces the parasitic capacitance interference generated by the lead wire connected with the capacitance plate and the periphery of the plate, and avoids or reduces the influence on the resolution of capacitance measurement caused by overlarge reference capacitance value.

Optionally, the CDC further includes a synchronous clock port (CLK). In one example, a synchronous clock port (CLK) serves as an input port to provide a clock signal to the CDC. A clock signal provided from the CDC port is used to indicate the timing of switch switching within the CDC to enable measurement of mutual and/or self capacitance through multiple stages. In yet another example, a synchronous clock port (CLK) provides a clock signal to the outside as an output port of the CDC. The CDCs synchronize their own timing with the operation of other circuits by outputting a clock signal externally, e.g., so that they perform measurement processes concurrently with one or more other CDCs.

Disclosure of Invention

In contact and/or non-contact touch applications of various electrical appliances such as capacitive robot e-skin, geographic e-skin, capacitance tomography and elevator keys, a capacitance measurement unit with CDC as the core often needs to measure a plurality of capacitances at different positions, sometimes needs to dynamically change the area of a capacitance plate in the measurement process to adapt the sensing distance and the measurement sensitivity of a capacitive sensor as required, or is used as a shielding electrode of the capacitive sensor to eliminate external coupling signal interference. In applications where capacitance is measured over a large spatial range, the length of the leads introduces non-negligible interference. In a large space range, the number/types of detected objects may be more, and demands are made on distributed capacitance measurement.

For ease of industrial manufacture and deployment, a node is provided that carries the capacitance measuring unit or a component thereof. The nodes have uniform specifications to facilitate mass production and deployment in the field. The plurality of nodes are respectively arranged at the appointed position of the space to be detected, and the existence, the movement and the change condition of the substances and the objects on the surface, the nearby and the inside of the space to be detected are measured.

In CDC-based capacitance measurements, this is accomplished by applying an excitation signal to the plates of the measured capacitance and detecting the response of the measured capacitance to the applied signal, and the signal processing of the capacitance measurement process occurs in the analog domain rather than the digital domain, so that the capacitance measurement process is sensitive to noise and requires that the excitation signal and the response have a common reference potential so that the excitation signal is comparable to the response. This will provide a CDC of excitation signals and received responses, constrained within a relatively small physical space (e.g., located on the same chip) to provide a common reference potential for the excitation signals and corresponding responses. This constraint is in contrast to the requirement that the distributed capacitive sensor system be used in a relatively large physical space.

Further, due to the diversity of object or material sizes to be measured or the need for dynamic configuration or rotation measurements of multiple pairs of electrodes as in the case of capacitive tomography applications, the capacitance plates of the nodes and the CDC are also required to have the capability of configuring and measuring across the nodes.

To address one or more of the above needs, embodiments in accordance with the present application provide a distributed capacitive sensor system including a plurality of candidate nodes located at different locations. One or more of the candidate nodes includes the CDC and some of the nodes include capacitive plates. In measuring capacitance, the CDC of one node generates an excitation signal that is applied to the capacitive plate for the capacitance being measured, the CDC also acquires a response corresponding to the excitation signal, and the capacitance measurement is completed. The capacitive plates for the capacitance being measured are provided by one or more nodes and need not be at the same node as the CDC. The CDC of one node thus allows the capacitance to be measured throughout the distributed capacitive sensor system using the capacitive plates to which any node is connected.

According to embodiments of the application, an analog signal router is also provided to distribute excitation signals generated by the CDC and responses to be transmitted to the CDC in a distributed capacitive sensor system. Such that the analog signals required by the CDC to measure the capacitance formed by the candidate capacitive plates are routed or communicated to the designated target at runtime. The analog signal router is for example an integral part of the node. In a further distributed application comprising a plurality of nodes, a plurality of analog signal routers form a network for distributing or conveying analog signals, and the transmission path of the analog signals in the network can be dynamically adjusted. By adjusting the transmission path of the analog signal provided by the analog signal router, not only a plurality of working modes of measuring one or more self-capacitance or mutual capacitance by a single CDC (programmable data controller) are supported, but also the area of the capacitance plate can be flexibly enlarged or reduced, so that under the condition that the deployed hardware is not changed in an application field, different requirements of a changed application scene on the capacitance measuring unit are adapted by combining or selecting the existing capacitance plate.

In addition, according to the analog signal router of the application, parallel or serial measurement of a plurality of CDCs which are relatively independent can be realized, and therefore cooperative measurement of the multi-capacitance measuring units is realized. The cooperation is embodied in combination or cooperation of the capacitor plates distributed in the plurality of capacitance measuring units, and also comprises cooperative measurement of a plurality of capacitances required by one application by the plurality of capacitance measuring units, so that the flexibility, the sensitivity, the sensing distance and the measuring speed of self capacitance or/and mutual capacitance measurement are increased. The plurality of nodes can be laid in a space to be measured according to a plane, a curved surface or a line, and the nodes are connected with each other through the ports, the switches and the connecting lines in two linear independent tangent vector directions of the plane or the curved surface, so that the self-capacitance and mutual-capacitance measurement in the space near the single node can be realized, the mutual-capacitance and self-capacitance measurement formed by capacitance plates (or combinations thereof) of any number of nodes can also be realized, and the monitoring or the measurement of objects to be measured between the capacitance plates of the plurality of nodes or near the capacitance plates of the plurality of nodes can be further realized. And an analog signal router according to embodiments of the present application, also such that the CDC of one of the nodes, may be configured or programmable to measure the CDC of the capacitance using the capacitive plates of any other node or nodes.

According to embodiments of the present application, a digital router is also provided to distribute data packets in a distributed capacitive sensor system to distribute configuration information (and/or programming information) to an analog signal router. The analog signal routers of one or more nodes are thereby configured to establish a transmission path for analog signals in the distributed sensor system.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 shows a schematic diagram of a capacitance measurement cell that measures capacitance using CDC;

FIG. 2A illustrates a block diagram of an analog signal router according to an embodiment of the present application;

FIG. 2B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 2C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 2D illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 3A illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 3B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 3C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 4A illustrates a schematic diagram of a capacitive channel according to an embodiment of the present application;

FIG. 4B illustrates a schematic diagram of a capacitive channel according to yet another embodiment of the present application;

FIG. 4C illustrates a schematic diagram of a capacitive channel according to yet another embodiment of the present application;

FIG. 5A illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 5B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 5C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 5D illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 6A illustrates a capacitive sensor network according to an embodiment of the present application;

FIG. 6B illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 6C illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 6D illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 6E illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 7 illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 8A illustrates a capacitive sensor network according to an embodiment of the present application;

FIG. 8B illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 8C illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 9A illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 9B illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 9C illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 10 illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 11A illustrates a capacitive sensor network according to yet another embodiment of the present application;

FIG. 11B illustrates a capacitive sensor network according to yet another embodiment of the present application; and

FIG. 12 illustrates a capacitive sensor network according to yet another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 2A illustrates a block diagram of an analog signal router according to an embodiment of the present application.

Referring to fig. 2A, an analog signal router according to an embodiment of the present application includes a self-capacitance signal line ASC (211), a plurality of switches (KAS1-KAS4, KBS1-KBS4 … …, KDS1-KDS4, also referred to as capacitive port coupling switches), and a plurality of capacitive ports (210, 212, 214, 216 … …) for connecting capacitive plates. By way of example, the CDC includes a self-capacitance signal line port (SCA).

In the example of fig. 2A, the capacitive port coupling switches correspond to the capacitive ports one-to-one, and each capacitive port is connected to the self-capacitance signal line ASC (211) through the corresponding capacitive port coupling switch. Thus, by closing a capacitive port coupling switch (e.g., KAS1), its corresponding capacitive port (210) is coupled to the self-capacitance signal line ASC (211), and thus to the self-capacitance signal line port (SCA) of the CDC. It is to be understood that the capacitive port to the self-capacitance signal line ASC (211) may be directly connected or indirectly connected via one or more components and/or leads, and the term "coupled" is used to express various connection modes including direct connection and indirect connection, and the application is not intended to limit the implementation thereof. Such that a signal applied by the CDC to its self-capacitance signal line port (SCA) is passed to a capacitance port (e.g., 210) corresponding to a capacitance port coupling switch (e.g., KAS1), which in turn acts on a capacitance plate coupled to the capacitance port (210). And optionally, signals received from the capacitive port (e.g., 210) are also transmitted to the self-capacitance signal line port (SCA) of the CDC through the capacitive port coupling switch (e.g., KAS1), and then the self-capacitance signal line ASC (211). It is appreciated that the capacitive plates and the CDC may not be part of an analog signal router according to embodiments of the present application, but rather the capacitive plates are externally connected to the analog signal router capacitive ports and one or more ports of the CDC (e.g., self-capacitance signal line ports (SCAs)) are externally connected to the analog signal router (e.g., via the CDC coupling switch KSC). Therefore, the analog signal router is suitable for capacitor plates of various shapes, sizes and/or materials and CDCs of various specifications.

In the example of fig. 2A, the capacitive ports are divided into groups, each group including 4 capacitive ports. Each group of capacitor ports is connected to a corresponding group of capacitor plates (indicated by A, B, C and D). The exemplary capacitor unit comprises 4 right-angle fan-shaped capacitor plates, and the 4 capacitor plates jointly form a circle and correspond to a circular touch key. Thus each group of 4 capacitive ports is used to connect 4 capacitive plates of 1 touch key. It is understood that the plurality of capacitive ports may be identical to one another, and the grouping of the capacitive ports is merely illustrative.

With continued reference to FIG. 2A, when the plurality of switches (e.g., KAS1-KAS4) are simultaneously closed, the self-capacitance signal line ASC (211) is connected to the plurality of capacitance ports (210, 212, 214, and 216) such that the stimulus signal provided by the self-capacitance signal line port (SCA) of the CDC is simultaneously provided to the capacitance plates coupled to the plurality of capacitance ports (210, 212, 214, and 216). In this way, the capacitance plates coupled to the capacitance ports respectively have equal potential, so that the capacitance plates coupled to the capacitance ports respectively are spliced to form a capacitance plate with a larger area (or different shapes) as an excitation electrode for measuring capacitance. The larger capacitor plate helps to measure the effect of objects further from the capacitor plate on the capacitance formed by the capacitor plate. In a similar manner, by closing a different number of multiple switches (KAS1-KAS4, KBS1-KBS4 … …, KDS1-KDS4), the capacitive plates coupled to the respective capacitive ports of the different number are spliced to form capacitive plates of different areas (or different shapes).

According to the embodiment of the application, the analog signal router is further used for CDC time-sharing measurement of the capacitance formed by the capacitor plates connected with the same or different capacitor ports. Such that a single CDC and the capacitive plates coupled to multiple capacitive ports form multiple identical or different capacitive measurement cells at different times. For example, at time T1, switch KAS1 is closed, while the other switches (KAS2-KAS4, KBS1-KBS4 … …, KDS1-KDS4) are all open, CDC forming a capacitance measurement unit with the capacitive plate coupled to capacitive port 210; at time T2, switch KAS2 is closed and the other switches (KAS1, KAS3, KAS4, KBS1-KBS4 … …, KDS1-KDS4) are open, and the CDC forms a capacitance measurement unit with the capacitive plate coupled to capacitive port 212. Optionally, the CDC forms a capacitance measurement unit with the same or different capacitive plates in sequence at a plurality of times, continuous or discontinuous.

In some cases, the CDC measures self-capacitance through its self-capacitance signal line port (SCA). By coupling the self-capacitance signal line port (SCA) of the CDC to, for example, capacitance ports KAS3 and KAS4, the CDC measures the self-capacitance with respect to ground of the capacitive plates formed by the splicing together of the capacitive plates to which capacitance ports KAS3 and KAS4 are respectively connected.

For simplicity, all switches in the analog signal router (KAE1, KAE3, KAE4, KBE1-KBE4 … …, KDE1-KDE4, and optionally KAEC) are also referred to as analog switch matrices.

In the example of fig. 2A, the CDC includes a single port (self-capacitance signal line port (SCA)), such that the analog signal router routes the analog signal for the CDC only through a single self-capacitance signal line ASC (211). Alternatively, if the CDC includes an excitation signal line port (AEC), the analog signal router routes the analog signal for the CDC through the excitation signal line, accordingly. Still alternatively or additionally, the CDC includes a mutual capacitance input signal line port (ACC), and accordingly the analog signal router routes the analog signal for the CDC through the mutual capacitance input signal line.

Optionally, the analog signal router further comprises a ground port for connecting to ground. The analog signal router also includes, for example, a ground signal line and a ground switch. The ground signal line is connected to the ground port and also to each of the capacitor ports through the ground switch. The grounding switch is arranged in a one-to-one manner with the capacitance port. So that one or more capacitive ports may be connected to a grounded signal line. Whereby the capacitive port is connected to the ground port or disconnected by configuration or programming of the analog signal router. Still optionally, the analog signal router further comprises a ground port coupling switch for connecting or disconnecting the ground port to a ground signal line, thereby making the analog signal router configurable or programmable to be connected to ground. The analog signal router optionally also may configurably or programmably connect the ground port/ground signal line to, for example, the CDC.

FIG. 2B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

The analog signal router of the embodiment of fig. 2B includes an excitation signal line (AE), a mutual capacitance input signal line (AC), an optional self-capacitance signal line (ASC), a plurality of switches (KAE1-KAE5, KAC1-KAC5, KAS1-KAS5, also referred to as capacitive port coupled switches), and a plurality of capacitive ports (210, 212, 214, 216 and 218) for connecting the capacitive plates. In the embodiment of fig. 2B, a plurality of CDC coupled switches (KAEC, KACC and optionally KSC) are also included. The CDC includes an excitation signal line port (AEC), a mutual capacitance input signal line port (ACC), and an optional self capacitance signal line port (SCA).

The combination of excitation signal lines (AE), mutual capacitance input signal lines (AC) and optional self-capacitance signal lines (ASC) is called a set of connection lines. Each connection line of the set of connection lines (excitation signal line (AE), mutual capacitance input signal line (AC) and optional self capacitance signal line (ASC) are connected in the same manner as the capacitance port and the CDC.

The connection lines of the connection line set are connected with the ports of the CDC in a one-to-one mode. The number of the CDC coupling switches is the same as the number of the connection lines of the connection line set and also as the number of the ports of the CDC, such that each CDC coupling switch couples the connection line of its corresponding connection line set to the corresponding port of the CDC. For example, the excitation signal line (AE) is connected to the excitation signal line port (AEC) through a CDC coupling switch (KAEC), the mutual capacitance input signal line (AC) is connected to the mutual capacitance input signal line port (ACC) through a CDC coupling switch (KACC), and the self capacitance signal line (ASC) is connected to the self capacitance signal line port (SCA) through a CDC coupling switch (KSC). The connection lines of the connection banks are thus connected only to ports of the CDC corresponding thereto and are not connected to other ports of the CDC. Optionally, to adapt the CDC with different port configurations, a connection line number of the connection set of the analog signal router is no less than a port number of the CDC such that each port of the CDC is connected to one of the connection lines of the connection set and two or more ports of the CDC are avoided from being connected to the same connection line.

Each connection line of the set of connection lines (excitation signal line (AE), mutual capacitance input signal line (AC) and optional self-capacitance signal line (ASC)) is coupled to one of the capacitive ports via a set of capacitive port coupling switches (referred to as a sub-switch set). These sub-switch groups also form part of the analog switch matrix. The number of the switches in the sub-switch group is the same as the number of the connecting lines in the connecting line group.

In fig. 2B, the connection line group includes 3 connection lines, and thus each sub-switch group includes 3 switches. For example, capacitive port 210 is coupled to (each of) the set of connection lines through a set of sub-switches (KAE1, KAC1, KAS1), and capacitive port 212 is coupled to the set of connection lines through a set of sub-switches (KAE2, KAC2, KAS 2). With such an arrangement, each capacitive port is enabled to be connected to any of the connection lines of the set of connection lines, thereby enabling the capacitive port to be coupled to any one of the ports (AEC, ACC or SCA) of the CDC.

According to an embodiment of the application, at most only one switch of the plurality of switches of the sub-switch group is closed at any time, while the other switches of the sub-switch group are open, so that the capacitive port is coupled to at most only one connection line of the connection line group at any time. So that each sub-switch group also avoids coupling two or more connection lines of a connection line group. It is allowed that all switches of the group of sub-switches are open at a certain time.

At some point, it is permissible for the plurality of sub-switch groups to have their respective corresponding capacitive ports all coupled to one of the connection lines of the connection line group, so as to simultaneously couple a certain connection line of the connection line group to the plurality of capacitive ports. For example, the sub-switch group (KAE1, KAC1, KAS1) couples the capacitive port 210 to the mutual capacitive input signal line AC, and the sub-switch group (KAE2, KAC2, KAS2) couples the capacitive port 212 to the mutual capacitive input signal line AC, thereby coupling the mutual capacitive input signal line AC to the plurality of capacitive ports (210 and 212) at that time, and thereby simultaneously coupling the respective capacitive plates of the plurality of capacitive ports (210 and 212). Thereby enlarging the area of the capacitive plate coupled to the mutual capacitance input signal line AC or changing the shape of the capacitive plate.

The analog signal router according to the embodiment of fig. 2B is further adapted to different operating modes of the CDC. When the CDC is operating in a mode for measuring mutual capacitance, the CDC applies an excitation signal to the measured capacitance through an excitation signal line port (AEC) of the CDC, and acquires a response of the measured capacitance to the excitation signal through a mutual capacitance input signal port (ACC) of the CDC. By way of example, one plate of the mutual capacitance being measured is connected to the capacitance port 210, while the other plate is connected to the capacitance port 212. When the CDC is operating and an excitation signal is output through the excitation signal line port (AEC), connecting the excitation signal line port (AEC) of the CDC to the excitation signal line AE of the connected bank by closing the CDC coupling switch KAEC, connecting the excitation signal line AE to the capacitive port 210 by closing the switch KAE1 (and opening the switches KAC1 and KAS1), thereby applying the excitation signal output by the excitation signal line port (AEC) of the CDC to the capacitive plate coupled to the capacitive port 210; and simultaneously closing switch KACC and switch KAC2 to couple capacitive port 212 to a mutual capacitive input signal line port (ACC) of the CDC and opening switches KAE2, KAS2 and KSC, whereby the CDC receives through its mutual capacitive input signal line port (ACC) a response of a capacitive plate coupled to capacitive port 212 to the aforementioned stimulus signal.

When the CDC operates in a measured self-capacitance mode, the CDC applies a stimulus to the measured capacitance through its self-capacitance signal line port (SCA) and acquires a response. By way of example, the capacitive plate of the measured self-capacitance is connected to capacitive port 216. The capacitor plate to which the capacitor port 216 is connected forms a self-capacitance Cs with ground. In operation of the CDC, capacitive port coupling switch KAS4 is closed (switch KAE4 is open from switch KAC4) and switch KSC is closed to connect a self-capacitance signal line port (ASC) of the CDC to self-capacitance signal line ASC and thus to the capacitive plate of coupling capacitive port 216.

In a further optional mode of operation, the CDC measures the self-capacitance through its self-capacitance signal line port (SCA) while the mutual capacitance is also measured through its excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC). For example, while closing the CDC coupling switches KAEC and KACC, and switches KAE1 and KAC2 (opening switches KAC1, KAS1, KAE2 and KAS2), closing the CDC coupling switch KSC and switch KAS4 (opening switches KAE4 and KAC4) simultaneously measures the mutual capacitance formed by the capacitive plates connected to

capacitive ports

210 and 212, and the self-capacitance of the capacitive plate connected to capacitive port 216.

According to yet another embodiment of the present application, the CDC includes only the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) and does not include the self capacitance signal line port (SCA), but replaces the function of the self capacitance signal line port (SCA) by the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC). In this case, the connection line set of the analog signal router according to the embodiment of the present application includes the excitation signal line (AE) and the mutual capacitance input signal line (AC), and may not include the self capacitance signal line (ASC). Accordingly, switches (KAS1-KAS4, and KSC) for connecting self-capacitance signal lines (ASCs) are not included in the analog switch matrix.

As yet another example, the area, position, and/or shape of the capacitive plates of the capacitive measurement cell formed by the CDC and the capacitive plates is adjusted by opening or closing a plurality of capacitive port coupling switches corresponding to the same connection line of the connected line group. For example, a plurality of capacitive port coupled switches (KAE1-KAE5) corresponding to an excitation signal line (AE) are selectively opened and closed (forming a capacitive plate having a given area, position and/or shape) such that an excitation signal line port (AEC) of the CDC forms an excitation path with the capacitive plate to which each of the plurality of capacitive port coupled switches is coupled; a plurality of capacitive port coupling switches (KAC1-KAC5) corresponding to the mutual capacitance input signal line (AC) are selectively opened and closed (forming capacitive plates having a given area, position and/or shape) such that a CDC mutual capacitance input signal line port (ACC) forms a responsive path with the capacitive plates to which the plurality of capacitive port coupling switches are respectively coupled. Thus, two capacitor plates with given areas are connected with the CDC in such a way, a complete mutual capacitance measuring unit can be formed, and the mutual capacitance can be measured. And various capacitance plate combination modes are provided, and the capacitance plate combination mode corresponds to various mutual capacitance measuring units. Different mutual capacitance measuring units can be constructed at different moments through time-sharing control over the analog switch matrix, and time-sharing mutual capacitance measurement is carried out. When the self-capacitance measurement is performed, self-capacitance plates with different areas are formed by different combinations of the self-capacitance signal line (ASC) and the switches KAS1-KAS5, and the self-capacitance plates are connected to the CDC through the opening and closing of the self-capacitance signal line (ASC) and the CDC coupling switch KSC, so that different self-capacitance measurement units are formed, and the self-capacitance measurement is performed. Different self-capacitance measuring units can be constructed at different moments through time-sharing control over the analog switch matrix, and time-sharing self-capacitance measurement is carried out.

As yet another example, the capacitor unit for a circular touch key includes 4 sectors forming a circle and connected to the

capacitor ports

210, 212, 214 and 216, respectively, and the capacitor unit further includes a same plate a disposed opposite to the 4 sectors, the plate a being connected to the capacitor port 218. Plate A forms a mutual capacitance with each of the 4 sector plates (denoted A1, A2, A3, and A4). According to the analog signal router of the embodiment of the present application, the CDC is connected to each of the 4 mutual capacitances (a1, a2, A3, and a4) at different times to measure each mutual capacitance. At yet another time, switches KAE1-KAE4 are all closed to connect

capacitive ports

210, 212, 214 and 216 to excitation signal line AE and to combine the 4 sector electrodes into a whole by the excitation signal line forming an equipotential surface, the combined 4 sector electrodes forming a mutual capacitance with plate A and the mutual capacitance being measured by CDC. Therefore, through the analog signal router, the fact that multiple capacitors are measured in a time-sharing mode through a single CDC and a plurality of fixed capacitor ports is achieved.

Fig. 2C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

The analog signal router of the embodiment of fig. 2C is similar in composition to the analog signal router illustrated in fig. 2B. In the embodiment of FIG. 2C, an example is given of different combinations of capacitive plates being provided to the CDC by an analog signal router. The analog signal router of the embodiment of fig. 2C includes an excitation signal line (AE), a mutual capacitance input signal line (AC), an optional self-capacitance signal line (ASC), a plurality of switches (KAE1-KAE4, KAC1-KAC4, KAS1-KAS4, KBE1-KBE4, KBC1-KBC4, KBS1-KBS4, also referred to as capacitance port coupled switches), and a plurality of capacitance ports (210, 212, 214, 216, 240, 242, 244, and 246) for connecting the capacitance plates.

In one example, the capacitor plates (a1 and A3) associated with each of the non-adjacent capacitor ports (e.g., 210 and 214) may form a capacitor plate a, which may be combined by closing switches KAE1 and KAE3 simultaneously (connecting the two capacitor ports via excitation signal line AE), by closing switches KAC1 and KAC3 (connecting the two capacitor ports via mutual capacitance input signal line AC), and by closing switches KAS1 and KAS3 (connecting the two capacitor ports via self-capacitance signal line ASC). When this combination is achieved, the remaining switches of the sub-switch group corresponding to the capacitive port remain open (e.g., switches KAC1, KAS1, KAC3, and KAS3 remain open when the two

capacitive ports

210 and 214 are connected by excitation signal line AE).

As yet another example, a combination of two adjacent capacitor plates, such as capacitor plates A4 and B1 connected to capacitor

ports

216 and 240, may be implemented to form a capacitor plate B. When this combination is implemented, the state of the switch is similar to the above example.

As yet another example, a combination of 3 capacitor plates may be implemented, such as capacitor plates C formed by the combination of B2, B3, and B4 among the capacitor plates connected to the

capacitor ports

242, 244, and 246. By analogy, the capacitor plates can be formed in any number and combination by connecting the line groups and the corresponding switch groups of the capacitor port access. The different combination modes can carry out flexible configuration and time-sharing configuration and capacitance measurement according to measurement requirements.

Fig. 2D illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

As yet another example, the CDC also includes a synchronized clock signal line port (CLK) and an actively shielded signal line port (SHD), the analog signal router of the embodiment of fig. 2D also including an actively shielded signal line (ASH) and a synchronized clock signal line (ACLK) as compared to the analog signal router shown in fig. 2C.

Alternatively, the actively shielded signal line (ASH) is coupled to the capacitive port in the same way as the other connection lines of the connection line set, i.e. by the switch coupling of the sub-switch sets, one capacitive port is coupled to only one connection line of the connection line set at the same time, whereas the actively shielded signal line (ASH) may be coupled to a plurality of capacitive ports simultaneously. At this time, the active shield signal line (ASH) becomes one of the connection lines of the connection line group. In an example where the connection line group includes 4 connection lines (excitation signal line (AE), mutual capacitance input signal line (AC), self capacitance signal line (ASC), and active shield signal line (ASH)), each sub-switch group includes a corresponding 4 switches. In the example of FIG. 2D, capacitive port coupling switches (KASH1-KASH4, KBSH1-BSH4) are also included for coupling the capacitive ports with the active shield signal lines (ASH).

In operation, if the active shield signal line (ASH) is connected to the shield electrode (230) via the capacitive port (e.g., 214) and the excitation signal line (AE) is connected to the capacitive plate via the capacitive port (216), then the switch (KASH3) is closed concurrently with the switch KAE4 to provide an active shield signal to the shield electrode (230) while providing an excitation signal to the capacitive plate connected to the capacitive port (216).

Alternatively or additionally, the analog signal router further comprises an actively shielded signal port (260), the actively shielded signal line (ASH) being connected to the actively shielded signal port (260). The actively shielded signal port (260) is dedicated to connecting actively shielded signal lines (ASH) without connecting to other connection lines of the set of connection lines. At this time, the analog switch matrix of the analog signal router may not include the switches (KASH1-KASH4, KBSH1-KBSH 4). In some cases, the CDC provides an actively shielded signal having a greater amplitude (voltage and/or current) than the excitation signal, and accordingly the actively shielded signal line ASH and/or the actively shielded signal port (260) is adapted to transmit the actively shielded signal. Since the actively shielded signal port (260) does not need to be connected to other connection lines of the connection line set, the actively shielded signal port is connected to the actively shielded signal line (ASH) only through a switch (not shown) or directly without a switch. In operation, if an actively shielded signal line is connected to the shielding electrode (232) through the actively shielded signal port (260) and an excitation signal line AE is connected to the capacitive plate through the capacitive port (210), the switch (KAE1) is closed accordingly to provide an actively shielded signal to the shielding electrode (232) at the same time as the excitation signal is provided to the capacitive plate connected to the capacitive port (210).

Alternatively, the CDC does not provide an actively shielded signal port, but rather an actively shielded signal is generated by an analog signal router according to embodiments of the present application. For this purpose, the analog signal router comprises a follower (not shown in fig. 2D) connecting the excitation signal line (AE) with the actively shielded signal line (ASH) to apply the excitation signal obtained by the excitation signal line from the CDC to the actively shielded signal line (ASH). Still alternatively, a switch is further provided between the excitation signal line (AE) and the active shield signal line (ASH) to open or close the connection therebetween.

Optionally, the analog signal router further comprises a synchronous clock signal line (ACLK) and a synchronous clock port (262). The synchronous clock port 262 is optionally the same or different from the capacitive port. The synchronous clock signal line (ACLK) does not belong to a connection bank. An optional switch is included between the synchronous clock signal line (ACLK) and the synchronous clock port (262) to open or close the connection between the two. The synchronous clock signal line (ACLK) is coupled to the synchronous clock signal line port (CLK) of the CDC.

The CDC coupled switch of the analog signal router further includes a switch KSH and a switch KCL, an active shield signal port (SHD) for connecting the active shield signal line (ASH) and the CDC, and a synchronous clock signal line port (CLK) for the synchronous clock signal line (ACLK) and the CDC, respectively.

In one embodiment, the synchronizing clock port (262) receives a synchronizing clock signal from outside the analog signal router, and the synchronizing clock signal line (ACLK) provides the synchronizing clock signal acquired from the synchronizing clock port (262) to the synchronizing clock signal line port (CLK) of the CDC through the CDC coupling switch KCL. The synchronized clock signal indicates the timing at which the CDC initiates the capacitance measurement. Optionally, the synchronized clock signal also indicates a plurality of operational phases of the CDC measurement capacitance.

FIG. 3A illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

In the example of FIG. 3A, the capacitance measurement unit includes multiple CDCs (CDC1 and CDC2 are shown). Multiple CDCs may be operated simultaneously to measure multiple capacitances simultaneously.

Referring to fig. 3A, the set of connection lines of the analog signal router includes an excitation signal line (AE), a mutual capacitance input signal line (AC), and a self capacitance signal line (ASC). The CDC1 and the CDC2 are connected to the connection line set through respective CDC coupling switches. By way of example, the CDC1 corresponding CDC coupling switches (KAEC1 and KACC1) are closed (and switches KAE1 and KAC2 are closed) such that CDC1 measures the mutual capacitance formed by the capacitive plates connected to the capacitive ports (310 and 312) through the capacitive ports (310 and 312). At the same time or at different times when the mutual capacitance is measured by the CDC1, the CDC coupled switch (KSC2) corresponding to the CDC2 is closed (and switch KAS4 is closed), so that the CDC2 measures the self-capacitance through the capacitive port (314).

In the embodiment shown in FIG. 3A, each connection of the set of connections is shared by CDC1 and CDC 2. The same connection line cannot be used simultaneously from slave CDC1 and CDC2 to avoid collisions. Thus, if the CDC coupling switch KAEC1 is closed, switch KAEC2 should be open to avoid connecting connection line AE to both the excitation signal line ports (AEC) of CDC1 and CDC 2. The CDC1 and CDC2 share the connection lines of the connected banks in a time-sharing manner. For example, CDC1 is connected to the mutual capacitance input signal line AC at time T1, whereas CDC2 is not connected to the mutual capacitance input signal line AC at time T1 but is connected to the mutual capacitance input signal line AC at a time different from T1.

According to the embodiment of fig. 3A, the analog signal router connects the plurality of CDCs through sets of CDC coupling switches (KAEC1, KACC1 and KSC1, and KAEC2, KACC2 and KSC2), each set of CDC coupling switches for connecting a set of connection lines to one of the CDCs. And the plurality of CDCs timeshares the same connection line of the connected set of lines. At any time, at most one connection line of the set of connection lines is connected to one CDC.

FIG. 3B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

In contrast to the embodiment of FIG. 3A, in the embodiment of FIG. 3B, the analog signal router provides a shared excitation signal line AE for multiple CDCs, while providing each CDC with its own exclusive mutual capacitance input signal line (AC1, AC2, and AC 3).

In the example of fig. 3B, the capacitance measurement unit includes a plurality of CDCs (CDC1, CDC2, CDC3, and CDC4 are shown). Multiple CDCs may be operated simultaneously to measure multiple capacitances simultaneously. CDC1 and CDC2 each include an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC), and CDC3 and CDC4 each include only a mutual capacitance input signal line port (ACC). By way of example, the excitation signal line ports of CDC1 and CDC2 are independent of each other, such that CDC1 and CDC2 may output different excitation signals simultaneously. Whereas CDC3 and CDC4 do not have an excitation line port, but rather borrow the excitation line port (AEC) of CDC 1. For example, when measuring mutual capacitance, CDC3 provides a stimulus signal to the measured capacitance through the stimulus signal line port (AEC) of CDC1, and receives the response of the measured capacitance to the stimulus signal from the mutual capacitance input signal line port (ACC) of CDC 3. Optionally, each CDC also measures a self-capacitance. When the self-capacitance is measured by CDC1 or CDC2, a mutual capacitance input signal line port (ACC) thereof applies a stimulus to a plate of the measured capacitance in a time-sharing manner and acquires a response, and the applied stimulus is generated by a stimulus signal source of CDC1 or CDC2 itself. When CDC3 or CDC4 measures self capacitance, their mutual capacitance input signal line port (ACC) time-divisionally applies a stimulus, generated by a stimulus signal source such as CDC1, to the plate of the measured capacitance and acquires a response. Within each CDC, the excitation signal source of CDC1 is coupled to CDC3 and/or CDC 4.

According to the embodiment of fig. 3B, the analog signal router includes a plurality of CDC-coupled switch sets (KAEC1 and KACC1, KAEC2 and KACC2, KACC3, and KACC4), each CDC-coupled switch set corresponding to one of the CDCs, the CDC-coupled switch sets for coupling its corresponding CDC to the set of connection lines. Optionally, the number of switches of the CDC-coupled switch bank is the same as the number of ports of the corresponding CDC. The CDCs use the same connection line of the connected bank in a time-sharing manner. At any time, at most one connection line of the set of connection lines is connected to one CDC.

To accommodate the change in the amount of CDC, in the embodiment illustrated in fig. 3B, the group in which the excitation signal line (AE) is located is referred to as a connected line group, and the group in which one of the mutual capacitance input signal lines (AC1, AC2, or AC3) is located is referred to as a capacitance channel connected line group. In FIG. 3B, the sets of connection lines include only excitation signal lines (AE), and each set of capacitive channel connection lines includes one of the mutual capacitance input signal lines. The connecting wire of the capacitor channel connecting wire group is also connected with the capacitor port through the capacitor port coupling switch. Correspondingly, the capacitor ports are coupled with each connecting line of the connecting line group and all the capacitor channel connecting line groups through the sub-switch groups, so that the switch number of the sub-switch groups is the same as the sum of the number of all the connecting lines of the connecting line groups and all the capacitor channel connecting line groups, and the sub-switch groups are in one-to-one correspondence. For a sub-switch group, the switches of the sub-switch group are at most only one switch closed at any time, and the other switches are all open, so that the capacitive port is at most only coupled to one of all the connection lines connecting the group of lines and all the groups of capacitive channel connection lines at any time.

At some point, it is permissible for the plurality of sub-switch groups to have their respective corresponding capacitive ports all coupled to one of the connection lines of the connection line group or the capacitive via connection line group, so as to simultaneously couple a certain connection line of the connection line group or the capacitive via connection line group to the plurality of capacitive ports.

The capacitance channel connection line sets correspond to the CDC one by one. Therefore, if the number of CDCs needing coupling is increased, the capacitance channel connection line set is only required to be increased according to the number of CDCs. While the set of connection lines provides only one in the analog signal router. In one example, a single set of connection lines is connected to all CDCs through a CDC coupling switch. In another example, the set of connection lines is coupled to one of the CDCs, while the excitation signal source is shared within the plurality of CDCs.

Fig. 3C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

In contrast to the embodiment of fig. 3B, the set of connection lines in the embodiment of fig. 3C further comprises an active shield signal line (ASH) and/or a synchronous clock signal line (ACLK). The active shield signal line (ASH) corresponds to the excitation signal line (AE). An actively shielded signal line (ASH) is coupled to the CDC through a CDC coupling switch. Optionally, the CDCs share an actively shielded signal line (ASH), such that the actively shielded signal line (ASH) is coupled to one of the CDCs through one CDC coupling switch.

Optionally, the synchronous clock signal line (ACLK) does not belong to a connection line of the connection line group. Still alternatively, the CDCs share a synchronous clock signal line (ACLK)

In the example of fig. 3C, the set of connection lines is shared by all CDCs, and the set of capacitance-channel connection lines correspond one-to-one to the CDCs. In order to adapt to the increase of CDC, capacitance channel connection line sets are added in the same quantity as that of CDC, CDC coupling switch sets are added and used for connecting the newly added capacitance channel connection line sets and the newly added CDC, and capacitance port coupling switches are added for each sub-switch set and used for coupling capacitance ports corresponding to the sub-switch set where the sub-switch set is located to the newly added capacitance channel connection line sets.

FIG. 4A shows a schematic diagram of a capacitive channel according to an embodiment of the present application.

FIG. 4A presents an implementation of CDC utilizing analog signal router mutual capacitance measurements according to an embodiment of the present application. An excitation signal line port (AEC) of the CDC is coupled to an excitation signal line (AE) through a switch KAEC, a mutual capacitance input signal line port (ACC) of the CDC is coupled to a mutual capacitance input signal line (AC) through a switch KACC, a capacitance port (410) is coupled to the excitation signal line (AE) through a switch KAE1, and a capacitance port (412) is coupled to the mutual capacitance input signal line (AC) through a switch KAC 2. The capacitor plates connected to the respective capacitor ports 410, 412 form a mutual capacitance a 1. When the mutual capacitance measurement is performed, the switches KAE1, KAC2, KAEC and KACC are closed and the remaining switches of the analog switch matrix of the analog signal router remain open, so that the excitation signal line port (AEC) of the CDC, the mutual capacitance a1 and the mutual capacitance input signal line port (ACC) and the corresponding connection lines constitute a path for measuring the mutual capacitance a1, on which the CDC measures the mutual capacitance a 1.

According to the analog signal router of the embodiments of the present application, different paths are formed by opening or closing of the switches of the analog switch matrix, through which the CDC measures different capacitances coupled to the different paths. The path formed by the analog signal router for measuring capacitance for the CDC is referred to as a capacitance channel. The capacitive channel is used to couple the CDC and the capacitive plate such that the CDC measures the capacitance formed by the capacitive plate. The capacitive path is dynamic and may be changed as the switch opens or closes. The capacitive channels are simultaneously associated, and over time, the capacitive channels are created, changed, or released.

According to embodiments of the present application, a capacitive channel is, in general, a path formed by an analog switch matrix coupling a set of connection lines to at least one capacitive port and a capacitive-to-digital converter at a given moment. The capacitive channel includes a path for an electrical signal formed by one or more connection lines of the set of connection lines, one or more capacitive ports, and one or more switches of the analog switch matrix having a specified state. Typically, for a single CDC, at the same time, an analog signal router provides only a single capacitive channel to the CDC, such that the CDC measures capacitance through the single capacitive channel. And changing a switch state of the analog signal router to provide another capacitive channel to the CDC such that the CDC measures capacitance through the other capacitive channel as the capacitance measurement is completed or changes over time.

The capacitive channels have designated resources provided by the analog signal router, including one or more connection lines connecting the bank/bank of capacitive channels, one or more capacitive ports, and one or more switches of the analog switch matrix having designated states. At the same time, the resource is exclusively occupied by the capacitance channel. At different times, each capacitive channel may share resources.

For multiple CDCs, at the same time, the analog signal router may provide a respective capacitive channel to each CDC. The capacitive channels provided for each CDC have different resources from each other to avoid interference among the capacitive channels.

The capacitance channels include self-capacitance channels and mutual capacitance channels. The CDC measures the self-capacitance through a self-capacitance channel and the mutual capacitance through a mutual capacitance channel.

The example of fig. 4A shows mutual capacitance channels (indicated by bold lines). In FIG. 4A, the mutual capacitance path includes resources including an excitation signal line (AE), a mutual capacitance input signal line (AC), capacitance ports (410 and 412), switches KAE1, KAC2, KAEC and KACC.

FIG. 4B shows a schematic diagram of a capacitive channel according to yet another embodiment of the present application.

The example of fig. 4B shows a self-capacitance channel (indicated by the bold line). In fig. 4B, the resources of the self-capacitance channel include self-capacitance signal lines (ASCs), capacitance ports (420 and 422, coupling capacitance plates A3 and a4, respectively), switches KAS3, KAS4, and KSCs. In the example of fig. 4B, the self-capacitance signal line port (ASC) of the CDC is connected to the self-capacitance signal line (ASC) through switch KSC, capacitor plate A3 is connected to the self-capacitance signal line (ASC) through switch KAS3, and capacitor plate a4 is connected to the self-capacitance signal line (ASC) through switch KAS 4. Capacitor plates A3 and a4 constitute the plates of self-capacitance Cs. When a self-capacitance measurement is made, switches KAS3, KAS4 and KSC are closed, the other switches of the analog switch matrix are open, and capacitor plates A3 and a4 are at equal potential, so that capacitor plates A3 and a4 combine to form one plate of the self-capacitance Cs being measured. The ground acts as the other plate of the self-capacitance Cs. The self-capacitance Cs, the self-capacitance signal line (ASC), the ground and the connecting lines therebetween constitute a path for measuring the self-capacitance Cs, and the CDC measures the self-capacitance Cs on the path.

Further, by closing the switches (e.g., KAS1, KAS2, KBS1 … …) connecting the self-capacitance signal line (ASC) with other capacitance ports, a further capacitance path is formed that connects the capacitance plate for measuring the self-capacitance to more capacitance ports, so that the capacitance plate of the self-capacitance can have a larger area and different shapes. Thus, according to embodiments of the application, different capacitive channels are formed by configuring the opening or closing of the switches of the analog signal router, such that the CDC allows different capacitances to be measured through the different capacitive channels without changing the deployed hardware.

FIG. 4C shows a schematic diagram of a capacitive channel according to yet another embodiment of the present application.

The example of fig. 4C shows two capacitive channels existing simultaneously, one being a mutual capacitive channel and the other being a self capacitive channel. CDC1 measures the mutual capacitance Cm through a mutual capacitance channel and CDC2 measures the self-capacitance Cs through a self-capacitance channel. Optionally, CDC1 and CDC2 perform respective capacitance measurements simultaneously.

In the mutual capacitance path, switches KAE1, KAC2 and switches KAEC, KACC of corresponding CDC1 are closed such that excitation signal line (AE), mutual capacitance input signal line (AC), capacitance ports (430, 432), and switches (KAE1, KAC2, KAEC, and KACC) form a mutual capacitance path.

In the self-capacitance channel, switches KBS3, KBS4 and switch KSC2 of corresponding CDC2 are closed, so that the self-capacitance signal line (ASC), the capacitance ports (440 and 442) and the switches (KBS3, KBS4 and KSC2) form the self-capacitance channel. The reason why the switches KBS3 and KBS4 are closed at the same time is to enlarge the area of the capacitor plate of the self-capacitance.

In the analog switch matrix, the switches other than switches KAE1, KAC2, KAEC, KACC, KBS3, KBS4, and KSC2 are kept off.

Thus, a plurality of capacitive channels are formed simultaneously by the analog signal router such that a plurality of CDCs simultaneously perform measurements of a plurality of capacitances through respective capacitive channels in parallel.

In an alternative embodiment, CDC1 shares the excitation signal source internally with CDC2, and CDC2 utilizes the excitation signal line port (AEC) of CDC 1. In this case, CDC1 and CDC2 cannot operate simultaneously. Accordingly, in fig. 4C. The mutual capacitance channel and the self-capacitance channel provided by the analog signal router can not work at the same time, but work in a time-sharing mode. For example, at time T1, CDC1 measures the mutual capacitance Cm through the mutual capacitance channel, while at a later or different time T2, CDC2 measures the self-capacitance Cs through the self-capacitance channel.

FIG. 5A illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

In contrast to the analog signal router shown in fig. 2A, the analog signal router of fig. 5A also includes an analog routing controller. The analog routing controller couples to and controls opening or closing of one or more switches of an analog switch matrix of the analog signal router. By arranging the analog routing controller, the capacitance channel provided by the analog signal router can be changed in a working site. It will be appreciated that an analog routing controller is not necessary. The opening or closing of the switches of the analog switch matrix can be set in a manner known in the art on the production line and/or on the working site of the analog router. While the analog routing controller takes over control of the switches of the analog switch matrix and may build a higher description level, e.g. abstracting the control objects as capacitive channels instead of switches. The external part thus for example instructs the analog routing controller to create, release the specified capacitive channel, without the external part having to be concerned with the state of the individual switches required for building the capacitive channel.

As an example, the analog routing controller in fig. 5A records states of all switches of an analog switch matrix of the analog signal router, the analog routing controller is connected to a control terminal of each switch of the analog switch matrix, and the control terminals of the switches determine actions and/or states of the switches according to a control signal received from the analog routing controller. The analog routing controller also receives external configuration information to change the state of one or more switches of its recorded analog switch matrix. And the configuration information further indicates an opportunity for the analog routing controller to apply the recorded state of the one or more switches to the control terminals of the one or more switches.

Again by way of example. The analog routing controller is operated by an internal component such as a CPU or an external component as a control interface of the analog signal router. The CPU or a program memory accessed by the CPU may be programmed to set the manner in which the CPU operates the analog signal router. By operating or configuring the analog routing controller, internal or external components control the analog signal router to form the capacitive channels.

As yet another example, the analog routing controller includes a memory. The state of one or more switches of the analog switch matrix recorded by the memory is set by programming the memory, or is simulated at different times.

FIG. 5B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

Fig. 5B shows an example in which the analog routing controller includes a matrix control register set, a sequential state controller, and a selector.

The matrix control register set includes a plurality of registers, the registers of the matrix control register set including a plurality of bits, each bit corresponding to state information of one of the switches of the analog switch matrix. In one example, the number of bits of the register of the matrix control register set is the same as the number of switches of the analog switch matrix, so that each bit of the register corresponds to one switch of the analog switch matrix. In yet another example, the number of bits of the register of the matrix control register set is smaller than the number of switches of the analog switch matrix, e.g., the register is a 32-bit register. So that the plurality of registers of the matrix control register set collectively store state information for all switches of the analog switch matrix.

The matrix control register sets have recorded therein state information for switches of an analog switch matrix, e.g., for various capacitive channels. For example, each register of the matrix control register set corresponds to state information of a switch of the analog switch matrix required to construct one of the capacitive channels. In yet another example, multiple (but not all) registers of the matrix control register bank correspond to state information for switches of an analog switch matrix required to construct one of the capacitive channels. The sequential state controller successively selects a plurality of registers required for constructing a certain capacitance channel, and the state of a plurality of switches in the analog switch matrix is set by using the value of each bit of the registers.

A sequential state controller is a sequencer, state machine, or microprocessor that outputs a specified value or specified sequence of values corresponding to an input. The value output by the sequence state controller is used to indicate the selection of one of the registers in the matrix control register set. Optionally, the matrix control register bank is coupled to a selector, which selects one of the registers of the matrix control register bank as an output according to an output of the sequential state controller and provides the selected one as an output to the plurality of switches of the analog switch matrix.

In one example, the number of bits in the registers of the matrix control register bank is the same as the number of switches in the analog switch matrix, and accordingly, to create a capacitance channel, the sequential state controller selects a single register of the matrix control register bank to set the state of each switch of the analog switch matrix. In yet another example, the number of bits of the registers of the matrix control register set is less than the number of switches of the analog switch matrix, and accordingly, to create one capacitance channel, the sequential state controller sets the states of the plurality of switches of the analog switch matrix by selecting the plurality of registers of the matrix control register set by a sequence of values.

The selector outputs each bit of the register of the currently selected matrix control register group to the control port of the switch corresponding to the analog switch matrix so as to control the opening or closing of the corresponding switch.

The matrix control register set may be configured to write thereto control information for controlling the switches of the analog switch matrix. The values of the registers of the matrix control register set are updated, for example, by an external configuration port or processor.

Fig. 5C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

Fig. 5C shows an example in which the analog routing controller includes a register, the number of bits of the register is the same as the number of switches of the analog switch matrix, the bits of the register correspond to the switches of the analog switch matrix of the analog routing controller one-to-one, and each bit of the register of the analog routing controller is coupled to one of the switches of the analog switch matrix of the analog routing controller, and the bits of the register are used to control the opening or closing of the corresponding switch. For example, an analog switch matrix has 128 switches, and accordingly the width of the register of the analog routing controller is 128 bits.

According to the embodiment of fig. 5C, the values of the registers of the analog routing controller correspond to one or more capacitive channels provided by the analog signal router at a time, which are simultaneously present. In response to an update of the value of the register of the analog routing controller, one or more switches of the analog switch matrix of the analog signal router (corresponding to the changed bits of the register) are reset to an operating state, and accordingly, the capacitive path provided by the analog signal router also changes.

Still by way of example, the single register of the analog routing controller of FIG. 5C corresponds to multiple bus addresses. For example, the register is 128 bits wide, corresponding to 4 addresses of a 32-bit bus (e.g., A0-A3), and the 32 bits of the register are accessed via each bus address. An external component such as a CPU, also coupled to the bus, sets this register by accessing the bus address (a 0-A3) to update the capacitive channel provided by the analog signal router at runtime.

Fig. 5D illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

Fig. 5D shows an example in which the analog routing controller includes a matrix control register set and a selector. In contrast to the example of FIG. 5B, FIG. 5D illustrates an analog routing controller that does not include a sequential state controller.

The selector selects one of the matrix control register groups as an output according to an instruction of an external component such as a CPU. The selector selects the output bits of the register to be respectively coupled to one of the switches of the analog switch matrix of the analog signal router to control the open or closed state of the corresponding switch.

In some cases, the width of the bus (such as 32 bits) is much smaller than the number of switches of the analog switch matrix. By setting the matrix control register group, an external component such as a CPU is enabled to output all state information necessary for setting the analog switch matrix through a single bus access, thereby setting all switches of the analog switch matrix at the same time.

Alternatively, the control ports of the switches of the analog switch matrix are provided with bus addresses, so that an external component can directly set the switches of the analog switch matrix in a manner of accessing the bus. Although the number of switches set at a time is smaller than the bus width, the state update of all the switches of the analog switch matrix is completed by a plurality of bus cycles. And in some cases, only some of the switches of the analog switch matrix change state in two adjacent capacitance measurements, so that only the states of these switches need to be updated.

To measure capacitance over a larger spatial range, the capacitance(s) that may exist anywhere in space are measured, and according to embodiments of the present application, a capacitive sensor network is also constructed with an analog signal router and a CDC. The capacitive sensor network includes a plurality of nodes distributed at different locations, a plurality of capacitive plates, and 1 or more CDCs. And the CDC and the capacitor plate are dynamically combined into a capacitance measuring unit. Besides changing the area of the capacitor plates to adapt to the targets to be detected with different distances, shapes and materials, the capacitor plates at different positions are cooperated in space/time to obtain space/time distinguishing/tracking of the targets to be detected.

FIG. 6A illustrates a capacitive sensor network according to an embodiment of the present application.

Referring to fig. 6A, a capacitive sensor network includes two nodes. The two nodes have, for example, the same configuration. Each node of the capacitive sensor network has the same configuration, and large-scale production and deployment of the nodes are facilitated. Optionally, the nodes of the capacitive sensor network have different configurations, e.g., some nodes include the CDC and some nodes do not include the CDC, to further reduce costs.

The two nodes each include an analog signal router (610 and 620) and a CDC (CDC1 and CDC 2). Analog signal router 610 is connected to CDC1, while analog signal router 620 is connected to CDC 2. By way of example, the CDC includes a shared port (ACC/SCA) that serves as both a mutual capacitance input signal line port (ACC) and a self capacitance signal line port (SCA).

An analog signal router (e.g., 610) includes a mutual capacitance input signal line AC, a cross-chip mutual capacitance input signal line IAC, a plurality of switches (KIACE, KIACW, KIACS, and KIACN, also referred to as analog signal port coupled switches). The combination of multiple switches of an analog signal router is referred to as an analog switch matrix. The mutual capacitance input signal line AC and the trans-chip mutual capacitance input signal line IAC are corresponding and connected to each other. The mutual capacitance input signal line AC is connected to a port (ACC/SCA) of the CDC. The cross-chip mutual capacitance input signal line IAC is coupled to analog signal ports (IACE, IACW, IACs, and IACN) through switches (KIACE, KIACW, KIACS, and KIACN), respectively. The switches (KIACE, KIACW, KIACS and KIACN) are in one-to-one correspondence with the analog signal ports (IACE, IACW, IACS and IACN) so as to couple the cross-chip mutual capacitance input signal line IAC to one or more analog signal ports, and an analog signal port (e.g., IACW 612) can only be connected to the cross-chip mutual capacitance input signal line IAC through the switch (KIACW) corresponding thereto.

As an example, the four analog signal ports (IACE, IACW, IACS, and IACN) of the analog signal router 610 are all analog signal ports for inputting the signal line IAC across the mutual capacitance of the chip, and are respectively located in the east (E), west (W), south (S), and north (N) directions of the chip (the chip where the node is located) to which the analog signal router belongs, so that when the chip is disposed or mounted on the plane of the circuit board, leads are led out to the outside of the chip in the east, west, south, and north directions. In fig. 6A, although switch KIACS is shown directly connected to mutual capacitance input signal line AC for simplicity of drawing, and/or for limitation of planar topology, in an alternative embodiment, mutual capacitance input signal line AC is not directly connected to switch KIACS, but rather extends the cross-chip mutual capacitance input signal line IAC through another wiring layer of the chip to the other end (south end) of the chip and connects switch KIACS. Alternatively, the mutual capacitance input signal line AC is directly connected to the switch KIACS.

The analog signal port and the cross-chip connection line are adapted to connect to the outside of the chip and further to connect to another chip housing a node comprising an analog signal router (e.g., 620) according to embodiments of the application, such that the analog signal port and the cross-chip connection line may have different electrical characteristics than the mutual capacitance input signal line AC. Optionally, the analog signal port is also used to connect the capacitive plates.

In the example of fig. 6A, the analog signal port IACW (612) of the analog signal router 610 connects a capacitive plate that forms a self-capacitance (Cs1) with respect to ground. The analog signal port IACE is connected with the capacitor plate. CDC1 applies a stimulus to the capacitive plate connected analog signal port IACW (612) through mutual capacitance input signal line AC of analog signal router 610, cross-chip mutual capacitance input signal line IAC, switch KIACW, and measures its self-capacitance. An analog signal port (IACS) (616) is connected to an analog signal port (IACN) (624) of analog signal router 620 by lead 615.

Analog signal router 620 is connected to CDC 2. Analog signal router 620 also includes analog signal ports (IACW (622), IACE and IACS). The analog signal port IACW (622) of the analog signal router 620 connects a capacitive plate that forms a self-capacitance (Cs2) with respect to ground. The analog signal port IACE is connected with the capacitor plate.

According to embodiments of the application, analog signal routers may 610 and 620 work in concert to enable CDC1 to measure capacitance using a capacitive plate connected to either of analog signal routers 610 and 620. Similarly, CDC2 can also measure capacitance using a capacitive plate connected to either of analog signal routers 610 and 620. By way of example, switches KIACS of analog signal router 610, switches KIACN and KIACW of analog signal router 620 are closed such that the port (ACC/SCA) of CDC1 is connected to the capacitive plate (and the other switches are opened) through mutual capacitance input signal line AC of analog signal router 610, cross-chip mutual capacitance input signal line IAC (connection of mutual capacitance input signal line AC and cross-chip mutual capacitance input signal line IAC on the south side of analog signal router 610 is not shown in fig. 6A), switches KIACS and analog signal port IACs (616), via lead 615, and further through analog signal port IACN (624), switches KIACN, cross-chip mutual capacitance input signal line IAC, switches KIACW, and analog signal port IACW (622) of analog signal router 620, such that CDC1 is able to measure self-capacitance Cs2 formed by the capacitive plate not belonging to the same node as the CDC 1.

As yet another example, the switch KIACN of the analog signal router 620, the switches KIACS and KIACW of the analog signal router 610 are closed such that the port (ACC/SCA) of the CDC2 is connected to the capacitive plate (and the other switches are opened) through the mutual capacitance input signal line AC, the cross-chip mutual capacitance input signal line IAC, the switch KIACN and the analog signal port IACN (624) of the analog signal router 620 via the lead 615, and further through the analog signal port IACs (616), the switch KIACS, the cross-chip mutual capacitance input signal line IAC (the cross-chip mutual capacitance input signal line IAC connected to the switch KIACS is not shown in fig. 6A), the switch KIACW (612) of the analog signal router 610, such that the self-capacitance Cs1 is measured by the CDC 2.

FIG. 6B illustrates a capacitive sensor network according to yet another embodiment of the present application.

In the example of FIG. 6B, the two nodes each include an analog signal router (630 and 640), CDC (CDC1 and CDC 2). Analog signal router 630 is connected to CDC1, while analog signal router 640 is connected to CDC 2. The CDC (CDC1 and CDC2) includes a shared port (ACC/SCA) that serves as both a mutual capacitance input signal line port (ACC) and a self capacitance signal line port (SCA).

In contrast to the nodes of the capacitive sensor network shown in fig. 6A, in fig. 6B, the analog signal router (e.g., 630) of the node also includes one or more capacitive ports (634, 644). The capacitor port is used for connecting a capacitor plate of the node. The analog signal router (e.g., 630) of the node also includes capacitive port coupling switches (KAC1, KAC2, KAC3, and KAC4) that correspond one-to-one with the capacitive ports. The capacitive port coupling switch is used to connect or disconnect its corresponding capacitive port to a mutual capacitive input signal line (AC). The mutual capacitance input signal lines (AC) are simultaneously connected to the plurality of capacitance ports by simultaneously closing the plurality of capacitance port coupling switches, and further, the capacitance plates connected with the capacitance ports are connected. The analog signal router (e.g., 630) also includes a CDC coupled switch (KACC) for controlling the connection or disconnection of the mutual capacitance input signal line (AC) to/from the CDC port (ACC/SCA). And disconnecting the CDC of the node from the analog signal router to reduce the interference generated by the CDC, so that the analog signal router of the node is favorable for providing signals for other nodes.

The analog signal router 630 and the analog signal router 640 are connected by a lead 635. Lead 635 connects the analog signal port (IACS) (636) of analog signal router 630 with the analog signal port (IACN) (646) of analog signal router 640.

CDC1/CDC2 may be configurable or programmable coupled to one or more of the two nodes' respective capacitive plates by analog signal router 630 and/or analog signal router 640, and measure the self-capacitance of these capacitive plates to ground. The capacitor plates of the node include capacitor plates connected to the node through a capacitor port and/or capacitor plates connected to the node through an analog signal port.

Fig. 6C illustrates a capacitive sensor network according to yet another embodiment of the present application.

In the example of fig. 6C, the two nodes that form the capacitive sensor network each include an analog signal router (650 and 660), and a CDC (CDC1 and CDC 2). Analog signal router 650 is connected to CDC1, and analog signal router 660 is connected to CDC 2. The CDC (CDC1 and CDC2) includes an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC). The CDC measures the mutual capacitance through an excitation signal line port (AEC), with a mutual capacitance input signal line port (ACC), and the self-capacitance through one of its ports.

In contrast to the nodes of the capacitive sensor network shown in fig. 6B, in fig. 6C, the analog signal router (e.g., 650) of the node also includes an excitation signal line (AE) and a cross-chip excitation signal line (IAE) connecting the excitation signal line (AE), capacitive port coupled switches (KAE1-KAE4) and corresponding capacitive ports, analog signal ports (IAEE, IAEW, IAEs, IAEN), and CDC coupled switches (KAEC).

The across-chip excitation signal lines (IAE) are coupled to corresponding analog signal ports (IAEE, IAEW, IAES, IAEN) through switches (KIAEE, KIAEW, KIAES, KIAEN). The switches (KIAEE, KIAEW, KIAES, KIAEN) are coupled with the analog signal ports (IAEE, IAEW, IAES, IAEN) in a one-to-one correspondence. Although the excitation signal line (AE) is shown in fig. 6C as being connected to the analog signal port (ias) through a switch, it will be appreciated that in alternative embodiments, the excitation signal line AE is not directly connected to the analog signal port (ias), but is reconnected to the analog signal port (ias) via a switch by the cross-chip excitation signal line IAE.

The capacitive port coupling switches (KAE1-KAE4) correspond to the capacitive ports one to one. Capacitive port coupling switches (KAE1-KAE4) are used to connect the respective capacitive ports to an excitation signal line (AE). A CDC coupled switch (KAEC) connects excitation signal line AE to an excitation signal line port (AEC) of the CDC.

The combination of the excitation signal line AE and the mutual capacitance input signal line AC is referred to as a connection line group. The combination of the cross-chip excitation signal line IAE and the cross-chip mutual capacitance input signal line IAC is referred to as a cross-chip connection line group.

A plurality of (e.g., two) capacitive port coupled switches (e.g., KAE1 and KAC1, KAE2 and KAC2) that connect the same capacitive port to respective connection lines of a group of connection lines, respectively, are referred to as a sub-switch group. At the same time, at most only one of the (two) switches of the sub-switch group is closed, so that the capacitive port is connected at most to one connection line of the connection line group at any time. And through the arrangement of the sub-switch groups, the capacitance ports can be connected to any connecting line of the connecting lines at different moments. While switches (e.g., KAE1-KAE4) connecting multiple capacitive ports to one of the connecting lines of the connected bank may be closed at the same time to connect the connecting line to multiple capacitive ports at the same time.

In the embodiment of fig. 6C, the analog signal port can only be connected to one of the cross-chip connection lines of the set of cross-chip connection lines. For example, the analog signal port IAEN of the analog signal router 650 can only be connected to the cross-chip stimulus signal line IAE, while the analog signal port IACN can only be connected to the cross-chip mutual capacitance input signal line IAC. So that for one analog signal port it is connected to a set of cross-chip connection lines (and thus only one of the cross-chip connection lines of the set of cross-chip connection lines) by only one switch; and for one capacitor port, the capacitor port is connected to the connecting line group through a sub-switch group comprising a plurality of switches, wherein the number of the plurality of switches of the sub-switch group is the same as that of the connecting lines of the connecting line group, and the switches of the sub-switch group correspond to the connecting lines of the connecting line group one by one.

With this arrangement, the number of switches required for the analog signal router 650 is reduced to reduce cost and complexity, and also to reduce interference of the switches with transmitted signals when analog signals are transmitted over long distances. For example, the analog signal port IACN is connected to the excitation signal line AC through only 1 switch (KIACN), while the capacitive port (e.g., 654) is connected to the mutual capacitance input signal line IAC through 2 switches. And also reserves sufficient analog signal ports and cross-chip connection line resources for passing analog signals between nodes. For example, the stimulus signal and the response to the stimulus signal may be transmitted simultaneously between two nodes.

Further, a plurality of analog signal ports (IAEE, IAEW, IAEs, IAEN) are connected across a chip connection line (e.g., IAE) through a plurality of switches (e.g., KIAEE, KIAEW, KIAES, KIAEN), respectively. By closing these switches simultaneously, the cross-chip connection lines are connected to multiple analog signal ports simultaneously to connect the cross-chip connection lines to multiple nodes and/or capacitive plates simultaneously.

With continued reference to FIG. 6C, by way of example, CDC2 is used to measure the mutual capacitance Cm formed by the capacitor plates connected to capacitor port 654 and capacitor port 664, respectively. The

capacitor ports

654 and 664 are located at two nodes, respectively, so that the capacitor plates connected to the

capacitor ports

654 and 664 form mutual capacitance in a larger spatial range. Further, the sensor network according to the embodiment of the present application can detect objects appearing in the spatial range corresponding to the capacitor plates connected to the

capacitor ports

654 and 664. The mutual capacitance input signal line port (ACC) of CDC2 is connected to capacitance port 664 by closing switches KACC, KAC1 of analog signal router 660. And closing switches KAEC, KIAEN of analog signal router 660, closing switch kies and switch KAE3 of analog signal router 650, connecting the excitation signal line input port (AEC) of CDC2 to capacitive port 654. CDC2 applies an excitation signal to the capacitive plates connected to capacitive port 654 and obtains a response to the excitation signal from the capacitive plates connected to capacitive port 664 and measures the mutual capacitance Cm.

In the example of fig. 6C, switch KAEC, actuation signal line AE, cross-chip actuation signal line IAE, switch KIAEN, analog signal port IAEN (662), lead lines connecting analog signal port IAEN (662) with analog signal port IAEs (652), analog signal port IAEs (652) of analog switch matrix 660, cross-chip actuation connection line IAEC, switch kiase, actuation signal line AE, switch KAE3 with capacitive port 654, and switch KACC, mutual capacitance input signal line AC and switch KAC1 of analog switch matrix 660 form a capacitive channel for measuring mutual capacitance Cm. By changing the state of the switches of the switch matrix of analog switch matrix 650 and/or analog switch matrix 660, different capacitive channels are created such that CDC1 and/or CDC2 measure capacitance through the capacitive channels. The capacitive channel is dynamic. The capacitive plates to which the capacitive channels are connected and the CDC form a capacitive measurement cell.

FIG. 6D illustrates a capacitive sensor network according to yet another embodiment of the present application.

In the example of fig. 6D, the two nodes that form the capacitive sensor network each include an analog signal router (670 and 680), CDC (CDC1 and CDC 2). Analog signal router 670 is connected to CDC1, and analog signal router 680 is connected to CDC 2. The CDCs (CDC1 and CDC2) include an excitation signal line port (AEC), a shared port (ACC/SCA), an active shield signal line port (SHD), and a synchronous clock signal line port (CLK). The shared port (ACC/SCA) serves as both a mutual capacitance input signal line port (ACC) and a self capacitance signal line port (SCA). The CDC measures mutual capacitance with ports (ACC/SCA) through the excitation signal line port (AEC), and self-capacitance through one of its ports.

In contrast to the nodes of the capacitive sensor network shown in FIG. 6C, in FIG. 6D, the analog signal router (e.g., 670) of the node also includes an actively shielded signal line (ASH), a synchronous clock signal line ACLK, capacitive port coupled switches (KASH1-KASH4), switches (KASH, KCLK), CDC coupled switches (KSH, KCL), an optional actively shielded signal port, and an optional synchronous clock port.

The capacitive port coupling switch (KASH1-KASH4) connects its corresponding capacitive port to the active shield signal line (ASH). Optionally, the actively shielded signal line is one of the connection lines of the connection line set, such that the sub-switch set corresponding to one of the capacitive ports comprises, for example, 3 switches (e.g., KAE1, KAC1, and KASH1), which respectively connect the capacitive port to each of the three connection lines of the connection line set. The actively shielded signal line (ASH) is also connected through a switch KASH to an actively shielded signal port that is dedicated to transmitting actively shielded signals and is not used, for example, to connect a capacitive plate. Optionally, the actively shielded signal port is replaced with an analog signal port, accordingly, the cross-chip connection set further comprises a cross-chip actively shielded signal line (not shown), and the switch couples the cross-chip actively shielded signal line to the analog signal port. The CDC coupled switch (KSH) connects the actively shielded signal line (ASH) to an actively shielded signal port (SHD) of the CDC.

The CDC coupled switch (KCL) connects the synchronous clock signal line (ACLK) to the synchronous clock signal line port (CLK) of the CDC. The synchronous clock signal line (ACLK) is also connected to the synchronous clock port (ICLK) through a switch (KCLK). Optionally, the synchronous clock port is replaced with an analog signal port, and accordingly, the cross-chip connection set further includes a cross-chip synchronous clock signal line (not shown) connected with the synchronous clock connection line, and the switch couples the cross-chip synchronous clock signal line to the analog signal port.

By configuring the analog switch matrix of the analog signal router of the node of the sensor network, the area of a capacitor plate of the node can be enlarged, reduced and dynamically combined, the configuration of mutual capacitance and/or self capacitance can be realized, and the alternate measurement function of the capacitance can be realized. The measurement of capacitance may be accomplished by any one of the CDCs of the sensor network, or multiple CDCs in concert.

By way of example, the capacitor plates to which the

capacitor ports

672 and 674 are respectively connected form a mutual capacitance Cm 1; and the capacitor plates connected to each of the

capacitor ports

682 and 684 form a mutual capacitance Cm 2. Both CDC1 and CDC2 may measure mutual capacitances Cm1 or Cm2 through analog signal router 670 and/or analog signal router 680. As another example, switches KAEC, KACC, KAE3 of analog signal router 670 are closed (other switches are open) with KAC4 such that CDC1 applies a stimulus signal to the capacitive plate connected to capacitive port 672 through stimulus signal line port (AEC), and obtains the response of mutual capacitance Cm1 to the stimulus signal from the capacitive plate connected to capacitive port 674 through mutual capacitance input signal line port (ACC). Thereby enabling measurement of mutual capacitance Cm1 with CDC 1.

Still by way of example, switches KAEC and kiase of analog signal router 670 are closed and switches KIAEN and KBE3 of analog signal router 680 are closed such that CDC1 applies an excitation signal through excitation signal line port (AEC) to the capacitive plate connected to capacitive port 682; and switches KACC and KIACS of analog signal router 670 are closed and switches KIACN and KBC4 of analog signal router 670 are closed, such that CDC1 obtains the response of mutual capacitance Cm2 to the stimulus signal from the capacitive plate connected capacitive port 684 through mutual capacitance input signal line port (ACC). The remaining switches are not mentioned to remain open. Thereby enabling measurement of mutual capacitance Cm2 with CDC 1.

Other embodiments, such as parallel measurement of two self capacitances or one self capacitance and one mutual capacitance, etc., switch configurations that cooperatively measure capacitance across nodes may likewise be switched as desired.

In order to facilitate deployment, the capacitive sensor network can easily cover various or arbitrarily-shaped areas to be measured, and analog signal ports are arranged in different directions of nodes. For example, analog signal ports are provided in two orthogonal directions of a node so that the node can be connected to other nodes in both directions, thereby forming a capacitive sensor network with a mesh topology.

FIG. 6E illustrates a capacitive sensor network according to yet another embodiment of the present application.

In the example of fig. 6E, the four nodes constituting the capacitive sensor network each include an analog signal router (690, 692, 694, and 696), and a CDC (CDC1, CDC2, CDC3, and CDC 4). The nodes of fig. 6E are the same as the nodes of fig. 6D.

By forming a plurality of (e.g. four) nodes into a sensor network such that the capacitive plates forming the nodes of the capacitance being measured are over a larger area, the capacitance formed correspondingly covers a larger area, so that detection can be carried out over a larger area. More nodes can also realize more capacitor plate combination modes of the cross nodes, and the combination of self capacitance or mutual capacitance in a larger area range and a larger number of CDCs simultaneously participate in the time series or parallel capacitance measurement. Alternatively, in the example of fig. 6E, some nodes may not be operating and some nodes may be operating, thereby forming, for example, the capacitive sensor network of fig. 6D.

The analog signal ports IACE and IAEE of the analog signal router 690 are connected to the analog signal ports IACW and IAEW of the analog signal router 692 by lead wires, respectively. The analog signal ports IACS and IAES of the analog signal router 692 are correspondingly connected with the analog signal ports IACN and IAEN of the analog signal router 696 through leads. The analog signal ports IACW and IAEW of the analog signal router 696 are connected to the analog signal ports IACE and IAEE of the analog signal router 694 by lead wires. The analog signal ports IACS and IAES of the analog signal router 690 are connected to the analog signal ports IACN and IAEN of the analog signal router 694 by corresponding leads.

By way of example, each cross-chip connection line of each node connects 4 analog signal ports, respectively located in the east (E), west (W), south (S), north (N) (lower right, upper left) directions of the node. Thus, when a plurality of nodes form a capacitive sensor network on a plane, the cross-chip connecting line of each node (which is not located at the boundary of the network) can be connected with the corresponding cross-chip connecting lines of other nodes in four directions of east, west, south and north. In this way, the deployment of a greater number of nodes into a capacitive sensor network is simplified and the number of nodes is not limited. And 3 or other number of nodes per node connected across the chip connections as required.

The lead lines of the analog signal ports connecting the nodes may have an arbitrary shape, so that the arrangement of the plurality of nodes is not limited to a planar structure but may form a curved line or a curved surface.

Although the capacitive sensor network illustrated in fig. 6E includes 2 nodes per row and 2 nodes per column, it will be appreciated that in alternative embodiments, the number of nodes in a row and a column of the capacitive sensor network may be arbitrary and not limited. Moreover, the capacitive sensor network may be formed to cover a plane or curved surface structure of the area to be measured according to the shape characteristics of the area to be measured instead of being arranged in rows and columns. Alternatively, for a certain node, its north (S) south (N) direction is referred to as a longitudinal direction, and other nodes are connected in the longitudinal direction through analog signal ports in the north (S) south (N) direction (longitudinal direction), and further connected through analog signal ports in the longitudinal direction of the other connected nodes, so that the connected nodes may have any number in the longitudinal extension of the certain node. Similarly, there may be any number of nodes connected in a node's lateral (east (E) west (W) direction) extension. Therefore, the requirements of various capacitance plate combinations in different shapes of regions to be measured, the requirements of motion measurement and calculation near nodes and the like are met.

In an alternative embodiment, the nodes are connected by analog signal ports located in the designated direction of the nodes to further simplify deployment and to facilitate configuration or programming of the analog switch matrix of each analog signal router. For example, an east analog signal port of one node is correspondingly connected with only a west analog signal port of another node (and is connected with an east, south or north analog signal port of another node); the west-oriented analog signal port of one node is correspondingly connected with the east-oriented analog signal port of the other node; the south analog signal port of one node is correspondingly connected with the north analog signal port of another node (and the south, east or west analog signal ports of different another nodes); the north analog signal port of one node is correspondingly connected with the south analog signal port of the other node. Thus, the analog signal ports of the nodes have directional attributes in addition to corresponding designated cross-chip connection lines, and the switches connecting the analog signal ports to the cross-chip connection lines also have the same directional attributes. The directional attribute is used to address the switch to be operated when programming or configuring the analog switch matrix.

Further, the nodes of the capacitive sensor network form rows and columns. Nodes belonging to the same row are connected by analog signal ports in the east and/or west direction (but not by analog signal ports in the south/north direction); nodes belonging to the same column are connected via south-oriented and/or north-oriented analog signal ports (and not via east/west-oriented analog signal ports). Thus, the analog signal ports of the nodes have row/column attributes (row or column number) in addition to corresponding designated cross-chip connections, and the switches connecting the analog signal ports to the cross-chip connections also have the same row/column attributes. The row/column attributes are used to address a set of switches to be operated upon when programming or configuring the analog switch matrix. Each node of the capacitive sensor network can thus be addressed, further simplifying the configuration or programming of the analog switch matrix of the respective analog signal router. According to the embodiment of the application, in the capacitive sensor network, the cross-chip connecting lines of the cross-chip connecting line group of the nodes are correspondingly connected. For example, the cross-chip excitation signal line of analog signal router 690 is only connected to the cross-chip excitation signal line of analog signal router 692, for example, and is not connected to the cross-chip mutual capacitance input signal line of analog signal router 692. Thereby facilitating routing of analog signals for measuring capacitance in the network and also simplifying the deployment of multiple nodes.

By constructing the sensor network, the CDC of one of the nodes measures capacitance using the capacitive plates located at each node in the sensor network. For example, CDC1 measures mutual capacitance through capacitance plates 690-A and 690-B, mutual capacitance through capacitance plates 692-A and 692-B, mutual capacitance through capacitance plates 694-A and 694-B, and mutual capacitance through capacitance plates 696-A and 696-B. The CDC1 also enables the measurement of mutual capacitance through the capacitive plates 690-A and 692-B, the mutual capacitance formed by the two combined capacitive plates through the combined (equipotential) capacitive plates 690-A and 690-B, and the combined (equipotential) capacitive plates 692-A and 692-B. The CDC1 can also measure the self-capacitance of a capacitive plate or a combination (equipotential) of multiple capacitive plates relative to earth. The CDC1 may also measure multiple capacitances in sequence, e.g., the mutual capacitance formed by capacitor plates 690-A and 690-B, the mutual capacitance formed by capacitor plates 692-A and 692-B, the mutual capacitance formed by capacitor plates 694-A and 694-B, and the mutual capacitance formed by capacitor plates 696-A and 696-B, at a desired timing, for example, to identify a change in position of an object relative to each node.

As yet another example, the synchronous clock signal line ports (CLK) of the CDCs of the nodes of the sensor network are connected to each other through the synchronous clock ports of the nodes, the CDC1 outputs a synchronous clock signal through its synchronous clock signal line port (CLK), and the CDC2, CDC3, and CDC4 each receive a synchronous clock signal through its synchronous clock line port (CLK). Whereas CDC1 measures the mutual capacitance formed by capacitive plates 690-A and 690-B, CDC2 measures the mutual capacitance formed by capacitive plates 692-A and 692-B, CDC3 measures the mutual capacitance formed by capacitive plates 694-A and 694-B, CDC4 measures the mutual capacitance formed by capacitive plates 696-A and 696-B, and each of CDC2-CDC4 initiates its mutual capacitance measurement in response to receiving a synchronizing clock signal at its synchronizing clock signal line port (CLK), such that CDC1 indicates the timing of the other CDC to measure capacitance by outputting the synchronizing clock signal. The capacitances are measured simultaneously by multiple CDCs, for example, to more accurately identify the position of an object relative to each node at a given time.

Although not shown in fig. 6A-6E, it will be appreciated that the analog signal router in the capacitive sensor network according to fig. 6A-6E may also optionally include an analog routing controller for controlling the opening or closing of one or more switches of the analog switch matrix of the analog signal router to which it belongs.

FIG. 7 illustrates a capacitive sensor network according to yet another embodiment of the present application.

In the example of fig. 7, the capacitive sensor network includes two nodes. Each node includes an analog signal router and a plurality of CDCs. The analog signal router 710 and the analog signal router 720 have, for example, the same configuration.

The analog signal routers (710, 720) connect 3 CDCs (CDC1, CDC2, and CDC 3). The analog signal router (710, 720) includes a connection line set and 4 capacitance channel connection line sets, wherein the 3 capacitance channel connection line sets are respectively and correspondingly connected with the 3 CDCs. The set of connection lines includes an excitation signal line AE and the 4 sets of capacitance channel connection lines each include a mutual capacitance input signal line (AC1, AC2, AC3, and AC 4). Optionally, the analog signal router (710, 720) further includes a synchronous clock signal line ACLK and an active mask signal line ASH.

To facilitate connection of multiple CDCs by an analog signal router, a set of connection lines is distinguished from a set of capacitance channel connection lines. In an alternative embodiment, the analog signal router includes a single set of connecting lines and a plurality of sets of capacitive channel connecting lines. The connection line sets are shared by the plurality of CDCs, and the capacitance channel connection line sets are connected with the CDCs in a one-to-one correspondence manner, so that corresponding capacitance channel connection line sets are provided for each CDC. And the sub-switch group corresponding to each capacitance port comprises switches which are in one-to-one correspondence with the connection line groups and the connection lines of all the capacitance channel connection line groups. Optionally, the analog signal router provides a greater number of sets of capacitive channel connection lines to support more CDC when deployed. And optionally one or more sets of capacitance channel connection lines are not connected to the CDC, i.e. these sets of capacitance channel connection lines are not operational. Therefore, when the optical fiber is deployed, the analog signal router and the CDC can be provided separately without being configured together in advance, and the flexibility of deployment is improved.

The analog signal router (710, 720) also includes cross-chip connection wire sets (e.g., IAE, IAC1, IAC2, IAC3, and IAC4) that correspond one-to-one with the connection wires of the connection wire sets and all capacitance channel connection wire sets. The analog signal ports of the analog signal router in each direction of east (E), west (W), south (S) and north (N) correspond to cross-chip connecting lines of the cross-chip connecting line group one by one. For example, in the example of fig. 7, the analog signal routers (710, 720) include analog signal ports (IAEE, IAC1E, IAC2E, IAC3E, and IAC4E) corresponding to the cross-chip connection lines (IAE, IAC1, IAC2, IAC3, and IAC4) in the east (E) direction, and analog signal ports (IAEW, IAC1W, IAC2W, IAC3W, and IAC4W) corresponding to the cross-chip connection lines (IAE, IAC1, IAC2, IAC3, and IAC4) in the west (W) direction.

The set of cross-chip connection lines of the analog signal router 710 correspond one-to-one to the cross-chip connection lines of the set of cross-chip connection lines of the analog signal router 720. The cross-chip connection wires of the cross-chip connection wire sets connect analog signal ports (e.g., IAEE, IAC1E, IAC2E, IAC3E and IAC4E, IAEW, IAC1W, IAC2W, IAC3W and IAC4W) of the respective analog signal routers (710, 720). The analog signal router 710 and the analog signal port of the analog signal router 720 are connected by a wire.

Optionally, the analog signal router (710, 720) further includes a cross-chip synchronous clock signal line ICLK and a cross-chip active shield signal line IASH. The cross-chip synchronous clock signal line ICLK is connected with the synchronous clock signal line ACLK, and the cross-chip active shielding signal line IASH is connected with the active shielding signal line ASH.

Referring to fig. 7, by way of example, CDC1 of each analog signal router (710, 720) includes an active shield signal line port (SHD), a launch signal line port (AEC), a mutual capacitance input signal line port (ACC), and a synchronous clock signal line port (CLKC), CDC2 includes the launch signal line port (AEC) and the mutual capacitance input signal line port (ACC), and CDC3 includes the mutual capacitance input signal line port (ACC). Optionally, CDC1 shares an excitation signal line port (AEC) with CDC3 internally. Still alternatively, CDC1-CDC3 internally share a synchronous clock signal line port (CLKC). Through CDC coupling switches (KSH, KAEC1, KAEC2, KACC1, KACC2, KACC3, KCL), excitation signal line AE is connected to CDC1 and excitation signal line port (AEC) of CDC2, mutual capacitance input signal line AC1 is connected to mutual capacitance input signal line port (ACC) of CDC1, mutual capacitance input signal line AC2 is connected to mutual capacitance input signal line port (ACC) of CDC2, mutual capacitance input signal line AC3 is connected to mutual capacitance input signal line port (ACC) of CDC3, synchronous clock signal line CLK is connected to synchronous clock signal line port (CDC CLKC) of CDC1, and active shield signal line (ASH) is connected to active shield signal line port (SHD) of CDC 1.

In the example of FIG. 7, each CDC of a node allows capacitance to be measured using one or more arbitrary capacitive plates in the capacitive sensor network. The capacitive plates used may be located at any node of the capacitive sensor network or a combination of capacitive plates that are multiple nodes.

According to the embodiment of fig. 7, by providing more cross-chip mutual capacitance input signal lines and mutual capacitance input signal lines in the analog signal router, the CDCs of the analog signal router each have an exclusive mutual capacitance input signal line, and the CDCs can independently operate with their mutual capacitance input signal line ports (ACCs). Optionally, a measured capacitance at each CDC time.

In an alternative embodiment, the analog signal router of the node also provides each CDC with its exclusive excitation signal line (AE), so that each CDC can operate independently of the mutual capacitance input signal line port (AEC) with its excitation signal line port (AE).

Still by way of example, the CDC1 connected to the analog signal router 710 outputs a synchronous clock signal that is provided to the CDC1 connected to the analog signal router 720 via the analog signal routers 710 and 720 to indicate the timing of the capacitance measurement by the CDC1 connected to the analog signal router 720. Alternatively or additionally, the synchronous clock signal received by the CDC1 to which the analog signal router 720 is connected through its synchronous clock signal line port (CLKC) also acts on the CDCs 2 and CDC3 to which the analog signal router 720 is connected. Similarly, the synchronous clock signal received by the CDC1 connected to the analog signal router 710 through its synchronous clock line port (CLKC) also acts on the CDC2 and CDC3 connected to the analog signal router 710.

Optionally, the analog signal router illustrated in fig. 7 also optionally includes an analog routing controller.

To reduce costs, one, more or all nodes of the sensor network may not include an analog signal router.

FIG. 8A illustrates a capacitive sensor network according to an embodiment of the present application.

Referring to fig. 8A, a capacitive sensor network includes two nodes (810 and 820). The two nodes (810 and 820) each include a CDC (CDC1 and CDC2) and an analog signal port. Node 810 includes

analog signal ports

812 and 814, and node 820 includes

analog signal ports

822 and 824. The analog signal port 814 is connected to an analog signal port 824. Node 810 also includes a capacitor plate (816) and node 820 also includes a capacitor plate (826).

The excitation signal line port (AEC) of CDC1 of node 810 is connected to capacitor plate 816. By way of example, to simplify node complexity and reduce cost, the excitation signal line port (AEC) of the CDC1 is directly or fixedly connected to the capacitor plate 816 without passing through a switch and capacitor port, which also reduces interference in signal transmission between the capacitor plate 816 to the excitation signal line port (AEC) of the CDC 1. Optionally, an excitation signal line port (AEC) of the CDC1 couples the capacitive plate 816 with another capacitive plate through a selection switch, such that the capacitive plate to which the excitation signal line port (AEC) of the CDC1 is connected may be changed by setting the switch. In a similar manner, a mutual capacitance input signal line port (ACC) of CDC1 is connected to analog signal port 814, while in node 820, analog signal port 824 is connected to capacitor plate 826.

By way of example, the capacitor plate 816 of node 810 serves as one of the capacitor plates (denoted as Cm1-1) of the mutual capacitance (denoted as Cm) being measured, and the capacitor plate 826 of node 820 serves as the other capacitor plate (denoted as Cm1-2) of the mutual capacitance being measured. The CDC1 of node 810 applies an excitation signal (indicated by (1) in fig. 8A) to capacitive plate 816(Cm1-1) through an excitation signal line port (AEC), while CDC1 also receives a response to the excitation signal (indicated by (4) in fig. 8A) from capacitive plate 826(Cm1-2) through its mutual capacitance input signal line port (ACC), thereby calculating or measuring a mutual capacitance Cm (indicated by (5) in fig. 8A) from the excitation signal and corresponding response. The response to the excitation signal generated on the capacitor plate 826 is transmitted in the node 820 to the analog signal port 824 (represented by (2) in fig. 8A), and then the response to the excitation signal is transmitted to the analog signal port 814 through the analog signal port 824 (indicated by (3) in fig. 8A).

In this manner, in the capacitive sensor network illustrated in FIG. 8A, the CDC1 of node 810 measures the mutual capacitance formed by the respective capacitive plates (816 and 826) of the two nodes. While the CDC2 of node 820 is not operational. Optionally, to further reduce costs, node 820 may not include CDC 2.

In the embodiment of FIG. 8A, the stimulus signal generated by the CDC1 is applied to the capacitive plate of the node (810) to which the CDC1 belongs, and the response to the stimulus signal is obtained from the capacitive plates of nodes other than the node (810) to which the CDC1 belongs. Therefore, the capacitance plates applied with the excitation signals and the capacitance plates generating responses can be positioned at different nodes, the distance between the capacitance plates forming the mutual capacitance is increased, the capacitance sensor network can measure the mutual capacitance in a larger spatial range, and the spatial distribution position of the measured capacitance is more possible.

FIG. 8B illustrates a capacitive sensor network according to yet another embodiment of the present application.

Referring to fig. 8B, the capacitive sensor network includes two nodes (830 and 840). The two nodes (830 and 840) each include a CDC (CDC1 and CDC2) and an analog signal port. Node 830 includes

analog signal ports

832 and 834 and node 840 includes

analog signal ports

842 and 844. The analog signal port 832 is connected to the analog signal port 842. The analog signal port 834 is connected to the analog signal port 844. Node 840 also includes capacitor plates (designated as Cm2-1 and Cm2-2, respectively.) in the example of FIG. 8B, CDC1 of node 830 measures the mutual capacitance formed by capacitor plates Cm2-1 and Cm2-2 of node 840 (designated as Cm 2).

The excitation signal line port (AEC) of CDC1 of node 830 is connected to analog signal port 832. The mutual capacitance input signal line port (ACC) of CDC1 of node 830 is connected to analog signal port 834, while in node 840 analog signal port 844 is connected to capacitor plate Cm2-1 and analog signal port 842 is connected to capacitor plate Cm 2-2.

By way of example, the CDC1 of node 830 applies an excitation signal to the analog signal port 832 via the excitation signal line port (AEC) (indicated by (1) in fig. 8B), while CDC1 of node 830 also receives a response to the excitation signal from the analog signal port 834 via its mutual capacitance input signal line port (ACC) (indicated by (6) in fig. 8B), thereby calculating or measuring the mutual capacitance Cm2 (indicated by (7) in fig. 8B) from the excitation signal and the corresponding response. It is to be understood that reference numerals (1) to (7) in fig. 8B also indicate temporal precedence of occurrence of the related events, with the event indicated by (1) occurring earliest and the event indicated by (7) occurring latest.

The excitation signal on the analog signal port 832 is transmitted to the analog signal port 842 (represented by (2) in fig. 8B), and then to the capacitive plate Cm2-1 (indicated by (3) in fig. 8B). In response to the stimulus signal, a response to the stimulus signal is generated at capacitor plate Cm 2-2. Inside node 840, the response is transmitted to analog signal port 844 (indicated by (4) in fig. 8B), and then through analog signal port 844 the response is transmitted to analog signal port 834 (indicated by (5) in fig. 8B) to enter node 830. At node 830, the response is transmitted to the mutual capacitance input signal line port (ACC) of CDC1 (indicated by (6) in fig. 8B).

In this manner, in the capacitive sensor network shown in FIG. 8B, the CDC1 of node 830 measures the mutual capacitance formed by the capacitive plates (Cm2-1 and Cm2-2) of node 840. While CDC2 of node 840 is not operational.

In the embodiment of FIG. 8B, the stimulus signal generated by the CDC1 of node 830 is applied to the capacitive plates of nodes other than the node (830) to which the CDC1 belongs, and the response to the stimulus signal is obtained from the capacitive plates of nodes other than the node (830) to which the CDC1 belongs. Therefore, the CDC of the measured capacitance and the capacitance plates forming the measured capacitance can be positioned at different nodes, so that the capacitance sensor network can measure the mutual capacitance in a larger spatial range, and the spatial distribution position of the measured capacitance is more possible.

FIG. 8C illustrates a capacitive sensor network according to yet another embodiment of the present application.

Referring to fig. 8C, the capacitive sensor network includes two nodes (850 and 860). The two nodes (850 and 860) each include a CDC (CDC1 and CDC2) and an analog signal port. Node 850 includes analog signal ports 852 and 854, and node 860 includes

analog signal ports

862 and 864. The analog signal port 852 is connected to the analog signal port 862. The analog signal port 854 may be unconnected to the analog signal port 864. Node 850 also includes a capacitor plate (denoted as Cm 3-1). Node 860 also includes a capacitor plate (denoted as Cm 3-2). In the example of FIG. 8C, CDC1 at node 850 measures the mutual capacitance (denoted as Cm3) formed by capacitor plate Cm3-1 at node 850 and capacitor plate Cm3-2 at node 860.

An excitation signal line port (AEC) of CDC1 of node 850 is connected to analog signal port 852. The mutual capacitance input signal line port (ACC) of CDC1 at node 850 is connected to capacitor plate Cm3-1, while in node 860, analog signal port 862 is connected to capacitor plate Cm 3-2.

By way of example, the CDC1 of node 850 applies an excitation signal (indicated by (1) in fig. 8C) to the analog signal port 852 through an excitation signal line port (AEC), while CDC1 of node 830 also receives a response to the excitation signal (indicated by (4) in fig. 8C) from capacitive plate Cm3-1 through its mutual capacitance input signal line port (ACC), thereby calculating or measuring a mutual capacitance Cm3 (indicated by (5) in fig. 8C) from the excitation signal and corresponding response.

The excitation signal on analog signal port 852 is transmitted to analog signal port 862 (indicated by (2) in fig. 8C), and then to capacitive plate Cm3-2 (indicated by (3) in fig. 8C). In response to the stimulus signal, a response to the stimulus signal is generated at capacitor plate Cm3-1 at node 850. Inside node 850, a response is transmitted to a mutual capacitance input signal line port (ACC) of CDC1 (indicated by (4) in fig. 8C).

In this manner, in the capacitive sensor network shown in FIG. 8C, the CDC1 of node 850 measures the mutual capacitance Cm3 formed by the capacitance plate Cm3-1 of node 850 and the capacitance plate Cm3-2 of node 860. While CDC2 of node 860 does not operate.

In the embodiment of FIG. 8C, the stimulus signal generated by the CDC1 of node 850 is applied to the capacitive plates of nodes other than the node 850 to which the CDC1 belongs, and the response to the stimulus signal is obtained from the capacitive plates of the node 830 to which the CDC1 belongs. The CDC of the measured capacitance and the capacitive plate making up the measured capacitance may thus be located at different nodes.

According to the capacitive sensor network of the embodiment of the application, one of two electrodes forming the mutual capacitance can be formed by combining a plurality of capacitance plates located at the same or different nodes.

FIG. 9A illustrates a capacitive sensor network according to yet another embodiment of the present application.

Referring to fig. 9A, a capacitive sensor network includes nodes 910 and 920. The two nodes (910 and 920) each include a CDC (CDC1 and CDC2), capacitive ports (914A, 914B, 914C and 914D, 924A, 924B, 924C and 924D), and analog signal ports (912A, 912B and 912C, 922A, 922B and 922C).

Node 910 also includes capacitor plates (Cm1-11, Cm1-12, Cm1-13, and Cm 1-23). Node 920 also includes capacitor plates (denoted as Cm1-21 and Cm 1-22). In the example of FIG. 9, the capacitor plates Cm1-11, Cm1-12 and Cm1-13 are connected together, with equal potential, as one electrode of the capacitance being measured (denoted as Cm 1); the capacitor plates Cm1-21, Cm1-22 and Cm1-23 are connected together, which have equal potential, as the other electrode of the capacitance Cm1 to be measured.

The excitation signal line port (AEC) of CDC1 of node 910 connects capacitance ports 914A and 914B and, in turn, capacitance plates Cm1-11 and Cm1-12, and the excitation signal line port (AEC) of CDC1 also connects analog signal port 912C and, in turn, capacitance plates Cm 1-13. Thus, CDC1 applies an excitation signal to capacitive plates Cm1-11 and Cm1-12 (indicated by (1a) in FIG. 9A), and an excitation signal to capacitive plates Cm1-13 (indicated by (1b) in FIG. 9A). In an embodiment according to the application, the analog signal port may be connected to both the analog signal port of another node and the capacitor plate.

The mutual capacitance input signal line port (ACC) of CDC1 of node 910 is connected to analog signal port 912B to receive a response from node 920. The mutual capacitance input signal line port (ACC) of the CDC1 is also connected to capacitance port 914D, which in turn connects to capacitance plates Cm1-23, to receive responses to excitation signals from capacitance plates Cm1-23 (indicated by (2b) in FIG. 9A).

The

capacitive ports

924A and 924B of node 920 are both connected to analog signal port 922B to transmit the responses received by capacitive plates Cm1-21 and Cm1-22 (indicated by (2a) in fig. 9A) to analog signal port 922B (indicated by (3) in fig. 9A) and then to analog signal port 912B (indicated by (4) in fig. 9A) and then to the mutual capacitance input signal line port (ACC) of CDC1 of node 910 (indicated by (5) in fig. 9A).

The CDC1 of node 910 calculates or measures a mutual capacitance Cm1 (indicated by (6) in fig. 9A) from the excitation signal and corresponding response.

In the embodiment of FIG. 9A, the capacitive plates to which the excitation signal is applied include 2 capacitive plates (Cm1-11 and Cm1-12) at the capacitive port of node 910, 1 capacitive plate (Cm1-13) at the analog signal port; and the capacitive plates that acquire the response signal include two capacitive plates (Cm1-21 and Cm1-22) at the capacitive port of node 920 and 1 capacitive plate (Cm1-23) at the capacitive port of node 910. Thus, multiple capacitive plates can be combined to form the electrodes of the mutual capacitance being measured, and these multiple capacitances can be located at the same or different nodes.

CDC2 of node 920 is not operational.

In an alternative embodiment, the sensor network includes a greater number of nodes, thereby enabling capacitance to be measured over a larger area.

FIG. 9B illustrates a capacitive sensor network according to yet another embodiment of the present application.

Referring to fig. 9B, the capacitive sensor network includes nodes 930, 940, and 950. The three nodes (930, 940, and 950) each include a CDC (CDC1, CDC2, and CDC3), a capacitive port, and an analog signal port. The analog signal ports are indicated by relatively thick-line rectangular boxes located at the boundaries of the rectangular boxes representing nodes, and the capacitive ports are indicated by relatively thin-line rectangular boxes located at the boundaries of the rectangular boxes representing nodes.

The excitation signal line port (AEC) of CDC1 at node 930 is connected to the 2 capacitor ports of node 930, which in turn are connected to capacitor plates Cm2-11 and Cm 2-12. In the embodiment of FIG. 9B, capacitor plates Cm2-11 in combination with Cm2-12 form one electrode of the capacitor under test (designated as Cm2), and capacitor plates Cm2-21, Cm2-22 in combination with Cm2-23 form the other electrode of the capacitor under test (Cm 2).

A mutual capacitance input signal line port (ACC) of CDC1 of node 930 is connected to

analog signal ports

932 and 934. The capacitor plate Cm2-21 of node 940 is coupled to the analog signal port 932 of node 930 via the capacitor port and analog signal port of node 940. The capacitive plates Cm2-22 and Cm2-23 of node 950 are coupled to the analog signal port 934 of node 930 through the capacitive port and analog signal port of node 940.

Thus, in the embodiment of FIG. 9B, the capacitive plates to which the stimulus signal provided by CDC1 is applied are all connected to node 930, while CDC1 receives a response from the capacitive plates to which node 940 and node 950 are coupled. The capacitor Cm2 under test is provided with capacitor plates constituting its electrodes by 2 nodes. It will be appreciated that in other embodiments according to the present application, the electrode of the capacitance being measured may be comprised of a plurality of plates, which may be from one or more nodes, and which may be connected to the capacitance port and/or the analog signal port of the node. Furthermore, the position and the size of the capacitor plate are adjusted by changing the capacitor plate of the electrode forming the measured electrode, so that the capacitor sensor network can measure various capacitances.

The CDCs of nodes 940 and 950 (CDC2 and CDC3) are not active. Optionally, nodes 940 and 950 do not include a CDC.

In other embodiments according to the present application, the capacitive sensor network may include a greater number of nodes. Some of the nodes provide capacitive plates for the capacitance being measured, and some of the nodes serve as channels for analog signal transmission during the measurement of the capacitance without providing capacitive plates.

FIG. 9C illustrates a capacitive sensor network according to yet another embodiment of the present application.

Referring to fig. 9C, the capacitive sensor network includes nodes 960, 970, 980, and 990. The four nodes (960, 970, 980, and 990) each include a CDC (CDC1, CDC2, CDC3, and CDC4), a capacitive port, and an analog signal port.

The excitation signal line port (AEC) of CDC1 of node 960 is connected to the capacitance port of node 960, which in turn is connected to capacitance plate Cm 3-1. In the embodiment of FIG. 9C, capacitor plate Cm3-1 forms one electrode of the capacitor under test (designated as Cm3), and capacitor plates Cm3-21, Cm3-22, in combination with Cm3-23, form the other electrode of the capacitor under test (Cm 3).

The mutual capacitance input signal line port (ACC) of CDC1 of node 960 is connected to analog signal port 962 and in turn to analog signal port 972 of node 970. In the embodiment of fig. 9C, node 970 does not provide a capacitive plate for capacitance Cm3, but rather provides a transmission path for a response to a stimulus signal applied to capacitance Cm 3. Node 970 summarizes the responses to the excitation signals from the plurality of nodes (node 980 and node 990). By node 970, the number of nodes receiving the response is increased, thereby increasing the number of capacitive plates receiving the response and extending the spatial distribution of these capacitive plates.

Analog signal port 972 of node 970 is connected to

analog signal ports

974 and 976. Analog signal port 974 is connected to the analog signal port of node 980, which in turn is connected to capacitor plates Cm3-23 through node 980 for transmitting responses received by capacitor plates 3-23 to analog signal port 962. The analog signal port 976 is connected to the analog signal port of the node 990, which in turn is connected to the capacitor plates Cm3-21 and Cm3-22 through the node 990, to transmit the responses received by the capacitor plates Cm3-21 and Cm3-22 to the analog signal port 962.

Thus, in the embodiment of FIG. 9C, the capacitive plate to which the stimulus signal provided by CDC1 is applied is connected to node 960, while CDC1 receives a response from the capacitive plate to which node 980 and node 990 are coupled. The capacitor Cm2 under test is provided with capacitor plates constituting its electrodes by 2 nodes. Node 970 provides a path for transmitting responses from nodes 980 and 990 and expands the number and spatial distribution of capacitive plates from which responses are received. It will be appreciated that in other embodiments according to the present application, the electrodes of the capacitance being measured may be comprised of other numbers of multiple plates, which may be from one or more nodes, and which may be connected to the capacitance ports and/or analog signal ports of the nodes.

The CDC of nodes 970, 980, and 990 (CDC2, CDC3, and CDC4) do not work. Optionally, nodes 970, 980, and 990 do not include a CDC.

Optionally, in the embodiment of FIG. 9C, CDC1 may also measure self-capacitance through capacitor plate Cm3-1, and self-capacitance through capacitor plates Cm3-21, Cm3-22, and/or Cm 3-23.

FIG. 10 illustrates a capacitive sensor network according to yet another embodiment of the present application.

Referring to fig. 10, a capacitive sensor network includes nodes 1010, 1020, 1030, and 1040. The four nodes (1010, 1020, 1030, and 1040) each include a CDC (CDC1, CDC2, CDC3, and CDC4), a capacitive port, and an analog signal port.

The excitation signal line port (AEC) of the CDC1 of node 1010 is connected to the capacitive port 1012 of node 1010, which in turn is connected to the analog signal port 1022 of node 1020. The analog signal port 1022 of the node 1020 is connected to the

analog signal ports

1024 and 1026 thereof, and is further connected to the analog signal port 1032 of the node 1030 and the analog signal port 1042 of the node 1040. The analog signal port 1022 of node 1020 is also connected to capacitor plate Cm4-11 through the capacitor port of node 1020.

Optionally, an excitation signal line port (AEC) of the CDC1 of node 1010 is also connected to the capacitor plate Cm4-15 local to node 1010 to provide an excitation signal to the capacitor plate Cm 4-15.

In the embodiment of FIG. 10, capacitor plates Cm4-11, Cm4-12, Cm4-13, Cm4-14, and optionally Cm4-15, combine to be one electrode of the capacitance being measured (denoted as Cm4), while capacitor plate Cm4-2 serves as the other electrode of the capacitance Cm. Node 1020 not only provides the capacitance plate Cm4-11 for the capacitance Cm4 being measured, but also provides a transmission path for the excitation signal applied to the capacitance Cm3, which is further distributed to nodes 1030 and 1040. By node 1020, the number of nodes receiving the excitation signal is increased, thereby increasing the number of capacitive plates receiving the excitation signal and extending the spatial distribution of the capacitive plates.

The mutual capacitance input signal line port (ACC) of CDC1 of node 1010 is connected to capacitor plate Cm4-2 through a capacitance port.

Within node 1030, analog signal port 1032 connects capacitor plates Cm4-12 with Cm 4-13; within node 1040, analog signal port 1042 connects capacitor plates Cm4-14 so that excitation signals from CDC1 of node 1010 are applied to capacitor plates Cm4-12, Cm4-13, and Cm 4-14.

Thus, in the embodiment of FIG. 10, the capacitive plates to which the excitation signals provided by CDC1 are applied are located at a plurality of nodes (1010, 1020, 1030, and 1040). Node 1020 provides a path for transmission of the excitation signal from node 1010 and extends the number and spatial distribution of the capacitive plates receiving the excitation signal.

According to some embodiments of the present application, an analog signal router is included within a node of a capacitive sensor. One or more capacitive channels are dynamically created by configuring or programming the analog signal router to connect the CDC with the capacitive plates of the capacitance being measured to meet the diverse capacitance measurement requirements of the application.

FIG. 11A illustrates a capacitive sensor network according to yet another embodiment of the present application.

Referring to fig. 11A, a capacitive sensor network includes nodes 1110 and 1120. The 2 nodes (1110 and 1120) each include a CDC (CDC1 and CDC2) and an analog signal router (analog signal router 1 and analog signal router 2).

In the embodiment of FIG. 11A, the interconnection network of analog signal routers is configured or programmed to connect one or more of the analog signal ports, capacitive ports and CDC ports (AEC, ACC) of the node to which it belongs. Optionally, the analog signal router is an analog signal router according to an embodiment of the present application illustrated in fig. 2-7. Still optionally, the analog signal router includes an interconnection network, a capacitive port, and an analog signal port. In one embodiment, the interconnection network includes a set of connection lines, a set of cross-chip connection lines, and an analog switch matrix.

With continued reference to fig. 11A, within nodes (1110, 1120), the interconnection network of the analog signal router connects the excitation signal line port (AEC) of the CDC with the mutual capacitance input signal line port (ACC). The corresponding analog signal ports of node 1110 and node 1120 are connected by wires.

An excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC) of the CDC are connected to a capacitance port and/or an analog signal port of a node to which the CDC belongs by configuring or programming the analog signal router. Furthermore, the CDC is connected to the analog signal ports of the other nodes through the analog signal ports of the nodes to which the CDC belongs, and further connected to the capacitance ports and the capacitance plates of the other nodes. Alternatively or additionally, the analog signal router also connects the analog signal port of the node to which the router belongs to other analog signal ports and/or capacitance ports of the node. And connecting the analog signal port to the capacitor port, so that the capacitor plate connected with the capacitor port and the analog signal ports of other nodes connected with the analog signal port form an equipotential surface. Still alternatively or additionally, the analog signal router also connects one or more capacitance ports of the node to which the analog signal router belongs and/or one or more analog signal ports together to form an equipotential surface, so that the capacitance plates connected with the capacitance ports/analog signal ports are combined together to serve as electrodes of the capacitor to be measured.

Still alternatively, the analog signal router 1 of the node 1110 and the analog signal router 2 of the node 1120 are each connected to each other by 2 analog signal ports, wherein one analog signal port of a node is used to transmit, for example, an excitation signal and the other analog signal port of the node is used to transmit a response to the excitation signal, so that an excitation and its response can be transmitted simultaneously between the two nodes to measure a mutual capacitance from the excitation and its response.

In embodiments with analog signal routers, the nodes being manufactured may have the same or different configurations.

FIG. 11B illustrates a capacitive sensor network according to yet another embodiment of the present application.

Referring to fig. 11B, the capacitive sensor network includes 4 nodes (1130, 1140, 1150, and 1160). The 4 nodes (1130, 1140, 1150, and 1160) each include an analog signal router (analog signal router 1, analog signal router 2, analog signal router 3, and analog signal router 4) and a digital router (digital router 1, digital router 2, digital router 3, and digital router 4). Nodes 1130 and 1140 each include a CDC (CDC1 and CDC2) and a synchronous clock port (ICLK 1132 and ICLK 1142), while nodes 1140 and 1150 may or may not include a CDC or a synchronous clock port.

In contrast to the embodiment of fig. 11A, in the embodiment of fig. 11B, the digital router receives and/or transmits packets that are used to configure, set, or program the interconnection network or analog switch matrix of the analog signal router. For example, the interconnection network includes a plurality of switches for establishing or disconnecting connections between ports; and the data packets provide data or configuration information for controlling the opening or closing of one or more switches of the interconnection network.

Nodes (1130, 1140, 1150, and 1160) each include network ports (1136 and 1137, 1146 and 1147, 1156 and 1157, and 1166 and 1167). The network ports of the nodes are connected to each other and the digital router is coupled to the digital routers of the other nodes through the network ports. A network port is a port of a network of a shared medium, such as ethernet. Optionally, each node comprises one or more point-to-point ports, the point-to-point ports of the nodes being connected to each other. The digital router exchanges data packets with digital routers of other nodes through the point-to-point ports. The point-to-point interface is, for example, a serial port, an I2C bus interface, or a custom interface that provides point-to-point data transfer.

The synchronous clock port (ICLK) is connected to the clock port (CLK) of the CDC. In one example, a synchronous clock port (ICLK) provides a synchronous clock signal to the CDC to indicate to the CDC a timing to begin operation. For example, the analog signal router has established a capacitive channel, indicating to the CDC that the capacitance measurement process may begin by synchronizing the clock signals. In another example, the CDC outputs a synchronized clock signal and provides the synchronized clock signal to an analog routing controller of an interconnect network or analog signal router to switch the operating state of one or more switches as needed during capacitance measurement by the CDC to assist the CDC in completing the capacitance measurement. Optionally, the synchronous clock ports (ICLK) of the nodes are connected to each other to transmit synchronous clock signals between the nodes.

In an alternative embodiment, the synchronization clock information is carried in data packets transmitted by the digital router. For example, in response to receiving a data packet carrying synchronous clock information, a digital router or other component generates a synchronous clock signal that is provided to the CDC and/or analog signal routers to indicate the timing at which the circuits are to initiate operation.

In an alternative embodiment, the nodes of the capacitive sensor network comprise configuration nodes. The configuration node is one of the nodes of the capacitive sensor network or an arbitrary node. The configuration node provides data packets carrying configuration information and/or synchronization clock information for the analog signal router to one or more nodes of the sensor network. The digital router of the node processes or forwards the data packet according to the specified routing rule. So that data packets sent out by the configuration node can be transferred to any node in the sensor network. The data packet indicates a node to which it is to be configured, and the digital router of that node configures or controls one or more switches in the analog signal router in response to receiving the data packet and providing it to the analog signal router of the node to which it belongs.

In the embodiment of FIG. 11B, the capacitor port of each node is connected to a capacitor plate (A1, A2, B1, B2, C1, C2, D1, and D2). The capacitive plates may be connected together by an analog signal router to form electrodes having capacitances of different locations and areas, and the CDC of one of the nodes measures the self or mutual capacitance of the capacitance formed by the capacitive plates.

In one example, node 1130 acts as a configuration node. For example, capacitor plates a1 and a2 are combined as one electrode of the capacitance Cm5 to be measured, while capacitor plates D1 and D2 are combined as the other electrode of the capacitance Cm5 to be measured. Node 1130 configures its own interconnection network, connecting capacitor plates a1 and a2 to the excitation signal line port (AEC) of its own CDC1, and one of its analog signal ports to the mutual capacitance input signal line port (ACC) of CDC 1. The node 1130, through its digital router 1, sends a data packet to the digital routers of the nodes 1140 and 1160 such that the analog signal port of the node 1130 to which the mutual capacitance input signal line port (ACC) of the CDC1 is connected to the analog signal port of the node 1160 through the analog signal port of the node 1140 (in fig. 11B, the analog signal ports of the node 1140 and the node 1160, which are connected to each other, are not shown) (the interconnection network of the node 1140 is configured such that the analog signal port a of the node 1140 to which the analog signal port of the node 1130 is connected, the analog signal port B of the node 1140 to which the analog signal port of the node 1160 is connected), and further the interconnection network of the node 1160 connects the analog signal port of the node 1160 to the capacitance plates D1 and D2. Node 1130 is a configuration node and provides a configuration data packet to node 1140 and node 1160, which in turn instructs CDC1 to initiate a measurement of capacitance Cm 5. In response, CDC1 outputs an excitation signal through its excitation signal line port (AEC) for measuring capacitance, which is provided by the analog signal router at node 1130 to capacitance plates a1 and a 2; the CDC1 also obtains a response of the capacitance Cm5 to the excitation signal through its mutual capacitance input signal line port (ACC), the response being received from the capacitance plates D1 and D2, transmitted through the analog signal router of node 1160 to the analog signal port (not shown) of node 1160, then transmitted through a lead (not shown) between the nodes to the analog signal port (not shown) of node 1140, then transmitted through the analog signal router of node 1140 to the analog signal port of node 1140 connected to the analog signal port of node 1130, and then transmitted through the analog signal router of node 1130 to the mutual capacitance input signal line port (ACC) of CDC 1.

Optionally, node 1130 may also establish a capacitance path with node 1160 via node 1150 in order to complete the measurement of capacitance Cm 5.

Still alternatively, the configuration node may be different from the CDC node that provides the capacitance measurement. For example, capacitance Cm5 is measured by CDC2 at node 1140, while node 1130 is the configuration node, the excitation signal line port (AEC) of CDC2 is connected to capacitor plates A1 and A2, and the mutual capacitance input signal line port (ACC) of CDC2 is connected to capacitor plates D1 and D2.

Still optionally, one or more nodes in the sensor network do not include an analog signal router (to reduce cost), which may include the CDC, and provide the data packet as a configuration node to one or more nodes in the network to configure or program the analog signal router of the one or more nodes in the network to establish the capacitive channel such that the CDC of the self node measures the circuit in the capacitive sensor network.

Still optionally, one or more nodes in the sensor network comprise a plurality of CDCs. The plurality of CDCs of a node are all connected to the analog signal router of the node. The multiple CDCs of the nodes operate, for example, in a time-sharing manner, with capacitance being measured on different capacitance channels, respectively.

The capacitive sensor network of fig. 12 includes a total of 12 nodes (M1-M12) arranged in rows and columns, including 3 rows and 4 columns, with each row including 4 nodes. Those skilled in the art will appreciate that the number of rows and columns of the capacitive sensor network may be arbitrary, and the number of nodes in each row may be the same or different, and the number of nodes in each column may be the same or different, according to the principles illustrated in fig. 12 for constructing a capacitive sensor network, and thus may cover any area of any shape of area.

To support the construction of a capacitive sensor network in rows and columns, each node in fig. 12 includes a set of analog signal ports in 4 directions. Each set of analog signal ports of the node includes, for example, 2 analog signal ports for coupling an excitation signal line port (AEC) of the CDC with a mutual capacitance input signal line port (ACC), respectively. The 4 analog signal port groups are respectively positioned in the east (E), the west (W), the south (S) and the north (N) of the node, so that when the chip is deployed or installed on a circuit board isoplane, leads are led out from the outside of the chip in all directions of east, west, south and north. Located in the east (E) direction of the node are analog signal ports AEW and ACW. An analog signal port indicated with reference numeral AEx is used for coupling an excitation signal line port (AEC) of the CDC and an analog signal port indicated with reference numeral ACx is used for coupling a mutual capacitance input signal line port (ACC) of the CDC, wherein x indicates the direction. Located in the east (E) direction of the node are analog signal ports AEE and ACE; the analog signal ports AEW and ACW are positioned in the west (W) direction of the node; the node is positioned in the south (S) direction and is provided with an analog signal port AES and an ACS; located in the north (N) direction of the node are analog signal ports AEN and ACN.

In the embodiment of fig. 12, for a certain node, its north (S) south (N) direction is referred to as a portrait, and other nodes are connected in the portrait through analog signal ports in the north (S) south (N) direction (portrait). Similarly, the east (E) west (W) direction of a node is referred to as the transverse direction, and extending in the transverse direction of a node (its east (E) west (W) direction), there may be any number of nodes connected.

For example, nodes M1 through M4 are all located in the same row of the capacitive sensor network, and these nodes are connected laterally, i.e., through analog signal ports in the east (E) west (W) direction of the nodes. Specifically, the east analog signal ports (AEE and ACE (not shown)) of the node M1 are correspondingly connected to the west analog signal ports (AEW and ACW (not shown)) of the node M2, the east analog signal ports (AEE and ACE (not shown)) of the node M2 are correspondingly connected to the west analog signal ports (AEW and ACW (not shown)) of the node M3, and the east analog signal ports (AEE and ACE (not shown)) of the node M3 are correspondingly connected to the west analog signal ports (AEW and ACW (not shown)) of the node M4. Inside the nodes M1-M4, the west analog signal ports (AEW and ACW) and east analog signal ports (AEE and ACE) of each node can be connected correspondingly by configuration or programming. Thus, by configuring or programming nodes M1-M4, analog signals are passed between the west analog signal ports (AEW and ACW) and east analog signal ports (AEE and ACE) of each node.

Also for example, in the longitudinal direction, nodes M2, M6, and M10 are all located in the same column of the capacitive sensor network, and these nodes are connected longitudinally, i.e., through analog signal ports in the north (S) south (N) direction of the nodes. Specifically, the southbound analog signal port (AES and ACS (not shown)) of the node M2 is correspondingly connected to the northbound analog signal port (AEN and ACN (not shown)) of the node M6, and the southbound analog signal port (AES and ACS (not shown)) of the node M6 is correspondingly connected to the northbound analog signal port (AEN and ACN (not shown)) of the node M10. Inside the nodes M2, M6, and M10, the southbound analog signal ports (AES and ACS) and the northbound analog signal ports (AEN and ACN) of each node can be connected correspondingly by configuration or programming. Thus, by configuring or programming the nodes M2, M6, and M10, analog signals are passed between the southbound analog signal ports (AES and ACS) and the northbound analog signal ports (AEN and ACN) of each node.

And it will be appreciated that within each node, its horizontal analog signal port is programmably or configurably connected to the vertical analog signal port, such that within the node, analog signals traveling horizontally become vertically traveling, while analog signals traveling vertically become horizontally traveling. For example, to transfer analog signals from the analog signal port AEW of the node M1 to the analog signal port AES of the node M11, the nodes (M1-M3) of the row of nodes M1-M3 in the horizontal direction are configured or programmed such that the analog signal port AEW of the node M1 is connected to the analog signal port AEW of the node M3, and then the nodes (M3 and M7) of the column of nodes M3 and M7 in the vertical direction are configured or programmed, inside the node M3, the analog signal port AEW is connected to the analog signal port AES, and the analog signal port AES of the node M3 is connected to the analog signal port AES of the node M11.

Thus, in the example of fig. 12, an analog signal transmission path between any two nodes is created, which corresponds to selecting 1 row and 1 column of the nodes of the capacitive sensor network, such that the nodes in the selected row collectively provide a horizontal analog signal path, the nodes in the selected column collectively provide a vertical analog signal path, and the node at the intersection of the selected row and column for converting a horizontally transferred analog signal to a vertically transferred analog signal or vice versa. Further, the configuration or programming of the nodes in the selected row 1 and column 1 is also determined, with the nodes in the selected row configured or programmed such that their east analog signal ports are correspondingly connected to their west analog signal ports, and with the nodes in the selected column programmed or configured such that their south analog signal ports are correspondingly connected to their north analog signal ports. And for the node located at the intersection of the selected 1 row and 1 column, the analog signal port connected to the selected row is correspondingly connected to the analog signal port connected to the selected column. Thereby completing the creation of an analog signal transmission path between any two nodes.

It is to be understood that in the example of fig. 12, the east analog signal port of one node is correspondingly connected to only the west analog signal port of another node; the west-oriented analog signal port of one node is correspondingly connected with the east-oriented analog signal port of the other node; the south analog signal port of one node is correspondingly connected with the north analog signal port of the other node; the north analog signal port of one node is correspondingly connected with the south analog signal port of the other node.

Thus, for each node, its set of 4-way analog signal ports has directional attributes and a variety of connection modes that can be configured or programmed, including landscape (east-west), portrait (north-south), north-east, south-east, north-west, and south-west connections. The direction attribute is used to address the switch to be operated when programming or configuring the analog switch matrix of the node, and the connection mode is used to set the state of the operated switch when programming or configuring the analog switch matrix of the node. Optionally, the node index, the direction attribute and the connection mode are indicated in a data packet transmitted through the digital router. According to the node index, the digital router delivers the data packet to the node described by the node index. And configuring or programming the analog signal router of the node according to the direction attribute and the connection mode.

With continued reference to fig. 12, each node further includes a CDC, an analog signal router including a set of cross-chip connections, a set of connections, an analog switch matrix, and a plurality of capacitive ports, and a digital router (not shown). The capacitor port connects the capacitor plates (shown as A, B, C and D). Taking node M1 as an example, the connection line group includes 2 connection lines (two vertical lines in node M1). The connecting lines of the connecting line set are respectively connected with an excitation signal line port (AEC) of the CDC and a mutual capacitance input signal line port (ACC) through switches (KAEC and KACC). The connection line sets are respectively connected to one of the capacitance ports through a plurality of sub-switch sets (KAE and KAC, KBE and KBC, KCE and KCC, and KDE and KDC). The connecting wires of the connecting wire group are correspondingly connected with the connecting wires of the cross-chip connecting wire group. Each cross-chip connection line of the set of cross-chip connection lines is coupled to the analog signal port by a switch (KIAEN, KIACN, KAEW, KACW, KAEE, KACE, KAES, and KACS).

The CDC, the capacitance channel and the capacitance plate which are dynamically combined form a capacitance measuring unit. In the example of fig. 12, the capacitive sensor network may form a plurality of capacitive measurement cells. The capacitance measuring units can work separately or simultaneously, and can also work in a serial and parallel cooperation mode. Several examples of capacitance measuring cells are provided below, but their mode of operation includes, but is not limited to, the following examples.

In one example, the capacitive plates A, B, C and D of node M1 are both connected to the excitation signal line of the connecting bank through switches (KAE, KBE, KCE and KDE) that close node M1, so that capacitive plates A, B, C and D of node M1 combine into a large capacitive plate (denoted as Cm 1). The capacitive plates A, B, C and D of node M2 are both connected to the mutual capacitance input signal line of the connected bank by switches (KAC, KBC, KCC and KDC) that close node M2, so that capacitive plates A, B, C and D of node M2 combine into a large capacitive plate (denoted as Cm 2). The large capacitor plates Cm1 and Cm2 form a mutual capacitance Cm. The CDC of node M1 is connected to capacitor plates Cm1 and Cm2 through capacitance channels to measure mutual capacitance Cm. The switch KAEC of node M1 closes the excitation signal line port (AEC) of the CDC of node M1 to the excitation signal line of node M1 to apply the excitation signal to the capacitor plate Cm 1; switch KACW of node M2 is closed with switch KACE of node M1 to connect capacitor plate Cm2 to the mutual capacitance input signal line of node M1, and switch KACC of node M1 is closed to connect the mutual capacitance input signal line of node M1 to mutual capacitance input signal line port ACC of the CDC of node M1. In this way, the mutual capacitance cooperative measurement of the M1 cell and the M2 cell can be realized, wherein the CDC of the node M1, the capacitance plates Cm1 and Cm2, and the capacitance channels connecting them constitute a capacitance measurement unit. In a similar manner, a capacitance measuring unit is also formed between adjacent nodes.

In yet another example, to achieve the mutual capacitance measurement of the node M5 cell and the node M7 cell, the node M6 is also made to emulate the lateral connection (east-west connection) provided by the signal port. Therefore, the capacitance measuring unit can be formed between the non-adjacent nodes.

Similarly, in the longitudinal direction, a capacitance measuring unit may be formed between adjacent or non-adjacent nodes. And any node in the capacitance sensor network can form a capacitance measuring unit.

Alternatively or additionally, the capacitance plates of the capacitance measurement unit may be from one or more capacitance plates of the same node, or multiple capacitance plates of multiple nodes may be combined. For example, by simultaneously closing the switches (KAE, KBE, KCE and KDE) of node M1, the capacitive plates A, B, C and D of node M1 are brought to equal potential; and by also simultaneously closing the switches (KAE, KBE, KCE and KDE) of node M3, so that the capacitive plates A, B, C and D of node M3 have equal potential; further, combining multiple capacitive plates of multiple nodes is achieved by closing the switches KAEE of nodes M1 and M3, respectively, and causing the analog signal port of node M2 to provide a lateral connection (closing its switches KAEW and KAEE) such that the capacitive plates A, B, C and D of nodes M1 and M3, respectively, are both at equal potential.

In yet another example, node M8 and M9 cooperate to form a capacitance measuring cell. Capacitor plate A, B and C of node M8 form a large capacitor plate Cm3, and capacitor plate a and D of node M9 form a large capacitor plate Cm 4. The dynamically formed capacitive channel connects the excitation signal port (AEC) of the CDC of node M8 to capacitor plate Cm4 and also connects the mutual capacitance input signal port (ACC) of the CDC of node M8 to capacitor plate Cm 3. The CDC of node M8 thus applies an excitation signal to capacitor plate Cm4 and obtains a response to the excitation signal from capacitor plate Cm3 to measure the mutual capacitance formed by capacitor plate Cm3 and capacitor plate Cm 4. Alternatively, the node providing the CDC and the node providing the capacitive plate of the mutual capacitance may be the same or different.

It will be appreciated that in the capacitive sensor network illustrated in fig. 12, multiple nodes may also cooperatively measure self-capacitance. Configuring or programming one or more of the capacitive plates of the one or more nodes to have equal potentials to form capacitive plates of various areas, positions, and/or shapes, and the self-capacitance of the capacitive plate formed by the CDC measurement of one of the nodes. Alternatively, the node providing the CDC and the node providing the capacitive plate may be the same or different.

In alternative embodiments, the capacitive sensor network includes other numbers of nodes, with the nodes forming any number of rows and/or columns. So that the sensor network can cover a surface of arbitrary shape. Alternatively still, the nodes of the capacitive sensor network may also form only transverse connection ports or longitudinal connections, so that a plurality of cells are connected in a curved (straight) manner to measure capacitance.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A distributed capacitive sensor system comprising a plurality of nodes interconnected;

each node of the plurality of nodes comprises: one or more analog signal ports;

at least one of the plurality of nodes further comprises a capacitive-to-digital converter (CDC);

at least one of the plurality of nodes further comprises one or more capacitive plates;

the analog signal ports of the nodes are used for coupling the analog signal ports of other nodes;

a first node of the plurality of nodes comprises a capacitive-to-digital converter (CDC) and one or more capacitive plates;

the capacitance-to-digital converter of the first node applies a first excitation signal to one or more capacitance plates of the first node and obtains a first response to the first excitation signal from one or more first analog signal ports of the first node, and the capacitance-to-digital converter of the first node generates a mutual capacitance of the first response from the first excitation signal as a function of the first excitation signal and the first response measurement;

wherein the first response is from one or more capacitive plates of one or more second nodes different from the first node.

2. The distributed capacitive sensor system of claim 1, wherein

At least one node of the plurality of nodes further comprises one or more capacitance ports, and the capacitance ports of the nodes are used for coupling capacitance plates of the nodes to which the nodes belong;

the analog signal port of the node is used for coupling the analog signal ports of other nodes or the capacitance plates of the nodes to which the analog signal ports belong.

3. A distributed capacitive sensor system according to claim 1 or 2, wherein

The capacitive-to-digital converter of the first node applies the first excitation signal to one or more capacitive ports and/or one or more second analog signal ports of the first node.

4. A distributed capacitive sensor system according to any of claims 1 to 3, wherein

One or more first analog signal ports of a first node are respectively coupled to a second node different from the first node.

5. A distributed capacitive sensor system according to any of claims 1 to 4, wherein

Wherein the first response is from one or more capacitive plates of the one or more second nodes and also from one or more capacitive plates of the first node.

6. A distributed capacitive sensor system according to any of claims 1 to 5, wherein

The first node further comprises one or more third analog signal ports;

the capacitive-to-digital converter of the first node also applies a first excitation signal to one or more capacitive plates of one or more third nodes different from the first node through one or more third analog signal ports of the first node.

7. A distributed capacitive sensor system according to any of claims 1 to 6, wherein

At least one node of the plurality of nodes further comprises an interconnection network;

the one or more first analog signal ports of the node to which the node belongs are coupled to the one or more second analog signal ports of the node to which the node belongs by setting up an interconnection network.

8. The distributed capacitive sensor system of claim 7, wherein

Coupling one or more first analog signal ports of a node to which the node belongs to one or more capacitive ports of the node to which the node belongs by setting an interconnection network; and/or one or more analog signal ports and/or one or more capacitance ports for coupling the capacitance-to-digital converter of the node to which the interconnection network belongs to the node to which the interconnection network belongs by arranging the interconnection network.

9. The distributed capacitive sensor system of claim 7 or 8, wherein one or more of the plurality of nodes further comprises a digital router, the digital router of a node being coupled to the interconnection network of its own node, the opening or closing of the one or more switches of the interconnection network of its own node being controlled in accordance with a packet received by the digital router, or the setting of configuration information indicating the opening or closing of the one or more switches of the interconnection network of its own node in accordance with a packet received by the digital router.

10. The distributed capacitive sensor system of claim 9, wherein

Each node of the plurality of nodes further comprises a network port and/or a point-to-point port;

the digital routers of two of the plurality of nodes are coupled by a network port or a point-to-point port, the digital router of one of the two nodes providing a data packet to the digital router of the other of the two nodes, the data packet providing data for controlling the opening or closing of one or more switches of the interconnection network or configuration information for indicating the opening or closing of one or more switches of the interconnection network.

11. The distributed capacitive sensor system of one of claims 1-10, wherein the plurality of nodes comprises a second node;

a first analog signal port of the first node is coupled with a first analog signal port of the second node;

the capacitance-to-digital converter of the first node applies a second excitation signal to one or more capacitance plates of the first node and obtains a second response to the second excitation signal from the first analog signal port of the first node;

and the capacitance-to-digital converter of the first node calculates mutual capacitance formed by one or more capacitance plates of the first node and one or more capacitance plates of the second node according to the second excitation signal and the second response.

12. The distributed capacitive sensor system of claim 11, wherein

One or more second analog signal ports and/or one or more capacitive ports of the second node couple one or more capacitive plates of the second node to obtain the second response from the one or more capacitive plates of the second node.

13. A distributed capacitive sensor system according to claim 11 or 12, wherein the second node comprises an interconnection network arranged to couple the first analogue signal port of the second node to one or more second analogue signal ports and/or one or more capacitive ports of the second node.

14. The distributed capacitive sensor system of one of claims 1-13, wherein the plurality of nodes comprises a third node, an intermediate node, and a fourth node;

the first analog signal port of the third node is coupled with the first analog signal port of the intermediate node;

the second analog signal port of the intermediate node is coupled with the first analog signal port of the fourth node;

the capacitance-to-digital converter of the third node applies a third excitation signal to a capacitance plate of the third node and obtains a third response to the third excitation signal from a first analog signal port of the third node;

and the capacitance-to-digital converter of the third node calculates mutual capacitance formed by one or more capacitance plates of the third node and one or more capacitance plates of the fourth node according to the third excitation signal and the third response.

15. The distributed capacitive sensor system of one of claims 1-14, wherein the plurality of nodes comprises a third node, a plurality of intermediate nodes, and a fifth node;

the first analog signal port of the third node is coupled with the first analog signal port of the first intermediate node of the plurality of intermediate nodes;

the second analog signal port of the last intermediate node of the plurality of intermediate nodes is coupled with the first analog signal port of the fifth node;

the second analog signal port of the first intermediate node is coupled with the first analog signal port of the last intermediate node;

the capacitance-to-digital converter of the third node calculates a mutual capacitance formed by the capacitance plate of the third node and the capacitance plate of the fifth node according to the third excitation signal and the third response;

the first analog signal port of the fifth node is coupled to the one or more capacitive plates of the fifth node to obtain a third response from the one or more capacitive plates of the fifth node.

16. The distributed capacitive sensor system of claim 15, wherein

The second analog signal port of the first intermediate node and the first analog signal port of the last intermediate node are divided by the first intermediate node and the intermediate node of the plurality of intermediate nodes

One or more other intermediate nodes outside the second intermediate node.

17. The distributed capacitive sensor system of claim 16, wherein

The first analog signal port of each of the plurality of intermediate nodes is coupled with the second analog signal port to couple the second analog signal port of the first intermediate node with the first analog signal port of the last intermediate node.

18. The distributed capacitive sensor system of one of claims 15-17, wherein the digital router of each of the third node, the plurality of intermediate nodes, and the fifth node receives data packets sent to it by a configuration node; controlling opening or closing of one or more switches of an interconnection network of nodes to which the digital router belongs according to the received data packet to couple the capacitance digitizer of the third node to one or more capacitance plates of the third node and the fifth node;

wherein the configuration node is any one of the plurality of nodes.

19. The distributed capacitive sensor system of one of claims 1-18, wherein the plurality of nodes comprises a plurality of second nodes;

a plurality of first analog signal ports of a first node are coupled with first analog signal ports of a plurality of second nodes;

the capacitance-to-digital converter of the first node applies a fourth excitation signal to one or more capacitance plates of the first node and obtains a fourth response to the fourth excitation signal from a plurality of first analog signal ports of the first node;

the capacitance-to-digital converter of the first node calculates a mutual capacitance from the fourth excitation signal and the fourth response.

20. The distributed capacitive sensor system of one of claims 1-18, wherein the plurality of nodes comprises one or more sixth nodes;

one or more second analog signal ports of the second node are respectively coupled with the first analog signal ports of one or more sixth nodes;

the capacitance-to-digital converter of the first node applies a fifth excitation signal to one or more capacitance plates of the first node and obtains a fifth response to the fifth excitation signal from the first analog signal port of the first node;

and the capacitance-to-digital converter of the first node calculates mutual capacitance formed by one or more capacitance plates of the first node and the one or more capacitance plates of the sixth node according to the fifth excitation signal and the fifth response.

21. The distributed capacitive sensor system of one of claims 1-20, wherein the first excitation signal is provided to one or more first capacitive plates to which one or more nodes of the plurality of nodes are each coupled;

the first response is from one or more second capacitive plates to which one or more nodes of the plurality of nodes are respectively coupled.

22. The distributed capacitive sensor system of claim 21, wherein

The first capacitor plate is different from the second capacitor plate.

23. A distributed capacitive sensor system according to claim 20 or 21, wherein

An interconnection network of each of one or more of the plurality of nodes is configured such that the first excitation signal is provided to one or more first capacitive plates to which each of the one or more of the plurality of nodes is coupled and the first response is from one or more second capacitive plates to which each of the one or more of the plurality of nodes is coupled.

24. The distributed capacitive sensor system of claim 23, wherein

A digital router of each of one or more of the plurality of nodes receives the packet, and an interconnection network of nodes to which the digital router belongs is configured in accordance with the packet received by the digital router such that the first excitation signal is provided to one or more first capacitive plates to which each of the one or more of the plurality of nodes is coupled and the first response is provided from one or more second capacitive plates to which each of the one or more of the plurality of nodes is coupled.

25. The distributed capacitive sensor system of one of claims 21-24, wherein a capacitance-to-digital converter (CDC) of the first node generates the first excitation signal and receives the first response.

26. The distributed capacitance sensor system of one of claims 1-25, wherein the capacitance-to-digital converter of the first node simultaneously applies the first excitation signal to one or more capacitance plates of the first node.

27. The distributed capacitance sensor system of one of claims 1-26, wherein the capacitance-to-digital converter of the first node applies an excitation signal through the one or more capacitive plate ports of the first node to measure the self-capacitance of the one or more capacitive plates of the first node.

28. The distributed capacitive sensor system of one of claims 1-27,

the plurality of nodes comprise a configuration node and a receiving node;

configuring the nodes to respectively send data packets to the digital routers of one or more receiving nodes through the digital router of the node where the node is located;

each receiving node controls the opening or closing of one or more switches of its interconnection network according to a packet received from the transmitting node by its digital router, or sets configuration information indicating the opening or closing of one or more switches of its interconnection network.

29. The distributed capacitive sensor system of claim 28, wherein

The method includes the steps of forming a mutual capacitance in response to one or more capacitive plates of one or more receiving nodes, operating a capacitive digitizer of a first receiving node of the one or more receiving nodes by a configuration node to provide a stimulus signal to the formed mutual capacitance, acquiring a response of the formed mutual capacitance to the provided stimulus signal by the capacitive digitizer of the first receiving node, and measuring the formed mutual capacitance based on the provided stimulus signal and the corresponding response, wherein the configuration node may be the receiving node.

30. The distributed capacitive sensor system of one of claims 1-29, wherein each node of the plurality of nodes further comprises a synchronous clock signal line;

a synchronous clock signal line of the node is coupled with an analog signal port or a synchronous clock port of the node where the synchronous clock signal line is located;

the two interconnected nodes are coupled with respective synchronous clock signal lines through an analog signal port or a synchronous clock port;

and determining the timing of measuring the capacitance by the capacitance-to-digital converter of the node to which the synchronous clock signal line belongs in response to the signal received by the synchronous clock signal line from the analog signal port of the node to which the synchronous clock signal line belongs.

31. The distributed capacitive sensor system of one of claims 1-30, wherein at least one of the plurality of nodes comprises a plurality of capacitance-to-digital converters (CDCs); a first capacitive-to-digital converter (CDC) that includes nodes of a plurality of CDCs measures capacitance simultaneously or time-divisionally with a second capacitive-to-digital converter.

32. The distributed capacitive sensor system of one of claims 1-31, wherein at least one of the plurality of nodes comprises a set of connection lines, a set of cross-chip connection lines, and an analog switch matrix;

the connecting wire group comprises at least a first connecting wire and a second connecting wire;

the cross-chip connecting line group comprises at least a first cross-chip connecting line;

the first cross-chip connecting line is coupled with the second connecting line;

the analog switch matrix is configurable or programmable to couple the set of cross-chip connection lines to the analog signal ports of its node, wherein at any instant in time, the analog switch matrix couples an analog signal port to at most only one connection line of the set of cross-chip connection lines, and the analog switch matrix couples one connection line of the set of cross-chip connection lines to zero, one, or more analog signal ports;

the analog switch matrix also configurably or programmably couples the set of connection lines to a capacitance-to-digital converter of its node.

33. The distributed capacitive sensor system of claim 32, wherein

The node to which the cross-chip connection line group belongs comprises a plurality of analog signal ports for the first cross-chip connection line;

the analog switch matrix is configured to couple at most only one analog signal port for a first cross-chip connection line to the first cross-chip connection line at any one time, coupling the first cross-chip connection line to zero, one, or more analog signal ports for the first cross-chip connection line.

34. A distributed capacitive sensor system according to claim 32 or 33, wherein a capacitive-to-digital converter of a node to which the set of cross-chip connections belongs generates an excitation signal and acquires a response to the excitation signal through an analogue signal port to which the first cross-chip connection is coupled.

35. The distributed capacitive sensor system of claim 32 or 33, wherein the set of cross-chip connection lines further comprises a second cross-chip connection line;

the second cross-chip connecting line is coupled with the first connecting line.

36. The distributed capacitive sensor system of one of claims 32-35, wherein the analog switch matrix configurably or programmably couples the connection line set to the capacitive ports of its own node, wherein at any time the analog switch matrix couples one capacitive port of its own node to at most only one connection line of the connection line set, and the analog switch matrix couples one connection line of the connection line set to zero, one or more capacitive ports of its own node.

37. A distributed capacitance sensor system according to any one of claims 32 to 36, wherein the analogue switch matrix couples a first one of the connection lines to an excitation signal line port of the capacitance-to-digital converter and a second one of the connection lines to a mutual capacitance input signal line port of the capacitance-to-digital converter.

38. A distributed capacitive sensor system comprising a plurality of nodes interconnected;

each node of the plurality of nodes comprises: one or more analog signal ports;

at least one of the plurality of nodes further comprises a capacitive-to-digital converter;

the analog signal port of each node of the plurality of nodes is used for coupling the analog signal ports of other nodes;

a first node of the plurality of nodes comprises a capacitive-to-digital converter;

a capacitance-to-digital converter of a first node applies an excitation signal to one or more first analog signal ports of the first node and obtains a response to the excitation signal from one or more second analog signal ports of the first node, and generates a mutual capacitance of the response from the excitation signal as a function of the excitation signal and the response measurement.

39. The distributed capacitive sensor system of claim 38, wherein

the analog signal port of a node is also used to couple the capacitor plate of the node to which it belongs.

40. The distributed capacitance sensor system of claim 38 or 39, wherein the capacitance-to-digital converter of the first node further applies the excitation signal to one or more first capacitive plates of the first node.

41. The distributed capacitive sensor system of any of claims 38-40, wherein the one or more first analog signal ports of a first node are respectively coupled to one or more second nodes different from the first node.

42. The distributed capacitance sensor system of one of claims 38-41, wherein the response is from one or more second capacitive plates of the first node.

43. The distributed capacitance sensor system of one of claims 38-42, wherein the excitation signal is simultaneously provided to one or more first capacitive plates to which one or more nodes of the plurality of nodes are respectively coupled;

the response is simultaneously from one or more second capacitive plates to which one or more nodes of the plurality of nodes are respectively coupled.

44. The distributed capacitive sensor system of claim 43, wherein

The first capacitor plate is different from the second capacitor plate.

45. The distributed capacitive sensor system of claim 43 or 44, wherein the analog switch matrix of each of the one or more of the plurality of nodes is set such that the first excitation signal is simultaneously provided to the one or more first capacitive plates to which each of the one or more of the plurality of nodes is coupled and the first response is simultaneously from the one or more second capacitive plates to which each of the one or more of the plurality of nodes is coupled.

46. The distributed capacitive sensor system of claim 45, wherein

A digital router of each of one or more of the plurality of nodes receives the packet, sets an analog switch matrix of a node to which the digital router belongs based on the packet received by the digital router such that the first excitation signal is simultaneously provided to one or more first capacitive plates to which each of the one or more of the plurality of nodes is coupled, and the first response is simultaneously from one or more second capacitive plates to which each of the one or more of the plurality of nodes is coupled.

47. The distributed capacitance sensor system of one of claims 38-46, wherein a capacitance-to-digital converter of the first node generates the first excitation signal and receives the first response.

48. The distributed capacitive sensor system of one of claims 38-46, wherein the first node comprises a plurality of capacitive-to-digital converters;

and the first capacitance digital converter and the second capacitance digital converter of the first node measure the capacitance simultaneously or in a time-sharing manner.

49. The distributed capacitive sensor system of one of claims 38-48, wherein the first node comprises a set of connection lines, a set of cross-chip connection lines, and an analog switch matrix;

the analog switch matrix configurably or programmably couples the set of cross-chip connection lines to analog signal ports of a first node, wherein at any instant in time, the analog switch matrix couples an analog signal port to at most only one connection line of the set of cross-chip connection lines, and the analog switch matrix couples one connection line of the set of cross-chip connection lines to zero, one, or more analog signal ports;

the analog switch matrix also configurably or programmably couples the set of connection lines to a capacitive-to-digital converter of the first node.

50. The distributed capacitive sensor system of claim 49, wherein

The first node comprises a plurality of analog signal ports for the first cross-chip connection line;

51. The distributed capacitive sensor system of claim 49 or 50, wherein a capacitive-to-digital converter of the first node generates an excitation signal and acquires a response to the excitation signal through an analog signal port to which the first cross-chip connection line is coupled.

52. The distributed capacitive sensor system of one of claims 49-51, wherein said set of cross-chip connection lines further comprises a second cross-chip connection line;

53. The distributed capacitive sensor system of one of claims 49-52, wherein the analog switch matrix configurably or programmably couples the set of connection lines to the capacitive ports of the first node, wherein at any time the analog switch matrix couples one capacitive port of the first node to at most only one connection line of the set of connection lines, and the analog switch matrix couples one connection line of the set of connection lines to zero, one, or more capacitive ports of the first node.

54. A distributed capacitance sensor system according to any one of claims 49 to 53, wherein the analogue switch matrix couples a first one of the connection lines to an excitation signal line port of the capacitance-to-digital converter and a second one of the connection lines to a mutual capacitance input signal line port of the capacitance-to-digital converter.