CN217386382U - System comprising a plurality of chips - Google Patents

Abstract

A system including a plurality of chips is provided. The provided system comprising a plurality of chips is an R-SpiNNaker system comprising a plurality of chips, one or more of which comprise a digital router, an analog signal router, and one or more network ports or point-to-point ports; a network port or a point-to-point port of a first chip of the plurality of chips is coupled to a network port or a point-to-point port of a second chip of the plurality of chips; the digital router of the first chip receives a data packet through a network port or a point-to-point port of the chip where the digital router is located; setting one or more switches of the analog signal router of the first chip according to data of the data packet carrying configuration information of the analog signal router.

Description

System comprising a plurality of chips

Technical Field

The application relates to an R-SpiNNaker system, which comprises a plurality of R-SpiNNaker chips, wherein a distributed impulse Neural Network (SNN) is constructed and is used for distributed capacitance measurement and object perception.

Background

The original intention of the "Overview of the SpiNNaker System architecture" at IEEE-Journals & Magazines Volume 62, Issue 12, Dec.2013, was to try and simulate how the human brain represents where to process information. SpiNNaker attempts to simulate mammalian brain behavior and does not involve simulating mammalian sensory behavior, and is therefore a massively parallel multi-core, purely digital computing system. It can contain up to 1,036,800 ARM9 cores and 7Tbytes of RAM, distributed across the 57K nodes (chips) of the entire system, each node containing 18 cores, which can simulate the behavior of 10 hundred million neurons.

Fig. 1A is a schematic diagram of a SpiNNaker chip architecture.

The central idea of spin maker is that all computation information is represented by AER (address event representation). The basic principle of AER is well documented in brain neuroscience when a neuron triggers a pulse that is a purely asynchronous event. All information need only include the time at which the pulse was generated and the identity address of the neuron that issued the pulse. In the SpiNNaker system, each node (chip) has an independent clock, and a neuron receiving information only needs to know a source address receiving a pulse and the relative time of an interval between two pulses, so that in the AER system, when a neuron sends a pulse, only the identity address of the neuron needs to be transmitted, and the relative time interval information generated by the pulse is calculated by the node where the neuron is located, and because SpiNNaker needs to simulate 10 hundred million neurons, 4 bytes of 32-bit address space are needed. The key point for realizing SpiNNaker idea is that each node (chip) is provided with an on-chip router, and AER information communication is realized in a multicast routing mode through the on-chip router. Each on-chip router has 24 routing channels, wherein 18 routing channels are used for information communication of 18 cores in a chip, the other 6 routing channels are used for inter-chip communication, as SpiNNaker aims to use 5 thousands of 7 thousands of 18-core chip clusters to form a million-core-level supercomputer to simulate human brain activities, and the 6 inter-chip routing physical channels adopt 7-wire high-speed asynchronous links suitable for short-distance communication. The nodes are realized by exchanging data packets carrying AER information, and the data packets carrying the AER information are called AER packets.

Capacitive based sensors are widely used. Similar to ADC (analog to digital converter), CDC (capacitance to digital converter) measures capacitance values and converts them to digital outputs.

FIG. 1B shows a schematic diagram of a capacitance measurement cell that measures capacitance using CDC. The capacitance measuring unit comprises a CDC, a capacitance polar plate and a connecting wire. The connecting wires connect the capacitive plates to the CDC such that the CDC can apply an excitation or receive response to the capacitive plates to measure capacitance.

The CDC includes an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC). Optionally, the CDC further includes a self-capacitance signal line port (SCA), an actively shielded signal line port (SHD), and/or a synchronous clock port (CLK). EXC stands for excitation source, e.g. a square wave signal source.

In one mode of operation, the two plates of the capacitor (Cm) being measured are connected to a stimulus signal line port (AEC) and a mutual capacitance input signal line port (ACC), respectively, to form a mutual capacitance measurement loop. The CDC applies an excitation signal to the plate of the capacitor (Cm) via its excitation signal line port (AEC), and collects a response to the excitation signal obtained from the plate of the capacitor (Cm) via its mutual capacitance input signal line port (ACC), and measures the capacitance value of the capacitor (Cm) in dependence on the response. Since both plates of the capacitor (Cm) are connected to the CDC, the capacitor (Cm) is referred to as a mutual capacitance.

In a further operating mode, one plate of the capacitance (Cs) to be measured is connected to the self-capacitance signal line port (SCA), largely as the other plate of the capacitance (Cs) to be measured, and the self-capacitance measuring circuit is formed via the ground terminal (AGND) of the CDC. The capacitance (Cs) is referred to as the self-capacitance. The CDC applies a stimulus to the capacitance (Cs) through the self-capacitance signal line port (SCA) and obtains a response to measure its capacitance value.

The CDC may apply a variety of capacitance measurement principles. As an example, for a mutual capacitance (Cm), the CDC charges the capacitance (Cm) through its excitation signal line port (AEC), acquires the charged voltage value of the capacitance (Cm) through the mutual capacitance input signal line port (ACC), and accesses the sigma-delta modulator, after low-pass filtering, outputs a digital quantity representative of the voltage value of the capacitance (Cm) to be measured. As yet another example, an excitation signal source (denoted as EXC) within the CDC is dynamically connected to the self-capacitance signal line port (SCA) while disconnecting the self-capacitance signal line port (SCA) to, for example, a delta-sigma modulator within the CDC to charge the self-capacitance (Cs), and at a subsequent time, disconnecting the excitation signal source (EXC) from the self-capacitance signal line port (SCA) and turning on the self-capacitance signal line port (SCA) with the delta-sigma modulator to convert a voltage value of the capacitance (Cs) to a digital quantity representative of a capacitance value thereof.

In some cases, the self-capacitance signal line port (SCA) of the CDC is replaced with a launch signal line port (AEC) or a mutual capacitance input signal line port (ACC), such that the CDC does not provide a separate self-capacitance signal line port (SCA). To replace the self-capacitance signal line port (SCA) with either the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), a switch is provided internally to the CDC. When a mutual capacitance is measured by an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC), the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) are disconnected with a circuit for measuring self capacitance; and when the self-capacitance is measured by replacing the self-capacitance signal line port (SCA) with the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), connecting a circuit for measuring the self-capacitance (including an excitation source EXC) to the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC), and disconnecting the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) from the circuit for measuring the mutual capacitance.

In still other cases, the CDC includes an actively shielded signal line port (SHD). For example, within the CDC, the excitation signal provided to the excitation signal line port (AEC) is provided to the active shield signal line port (SHD) through a follower. The output signal of the actively shielded signal line port (SHD) thus follows the output of the exciter signal line port (AEC). The active shielding signal line port (SHD) is used for coupling a shielding electrode, and the shielding electrode is adjacent to, covers or wraps a lead connecting the excitation signal line port (AEC) and the capacitor plate, so that signals transmitted on the lead connecting the excitation signal line port (AEC) and the capacitor plate are the same as the amplitude of signals transmitted by the active shielding signal line port (SHD) and have higher driving capability and lower internal impedance. The shielding electrode can reduce parasitic capacitance interference generated by a lead wire connected with a capacitance plate, avoid overlarge reference capacitance value and reduce the resolution of capacitance measurement.

Still by way of example, within the CDC, the active shield signal line port (SHD) is connected to the self-capacitance signal line port (SCA) via a follower, such that the output signal of the active shield signal line port (SHD) follows the signal output from the self-capacitance signal line port (SCA). And an active shielding signal provided by an active shielding signal line port (SHD) for coupling with the shielding electrode. The shielding electrode is adjacent to, covers or wraps a lead connecting the self-capacitance signal line port (SCA) and the capacitance plate, the electrode and the ground or between the electrode and a surrounding electric conductor, so that signals transmitted on the lead connecting the self-capacitance signal line port (SCA) and the capacitance plate are the same as the amplitude of signals transmitted by the active shielding signal line port (SHD), and the shielding electrode has larger driving capability and lower internal impedance. The shielding electrode reduces the parasitic capacitance interference generated by the lead wire connected with the capacitance plate and the periphery of the plate, and avoids or reduces the influence on the resolution of capacitance measurement caused by overlarge reference capacitance value.

Optionally, the CDC also includes a synchronous clock port (CLK). In one example, a synchronous clock port (CLK) serves as an input port to provide a clock signal to the CDC. A clock signal provided from the CDC port is used to indicate the timing of switching within the CDC to enable measurement of mutual and/or self capacitance through multiple stages. In yet another example, a synchronous clock port (CLK) provides a clock signal to the outside as an output port of the CDC. The CDCs synchronize their own timing with the operation of other circuits by outputting a clock signal externally, e.g., so that they perform measurement processes concurrently with one or more other CDCs.

SUMMERY OF THE UTILITY MODEL

In contact and/or non-contact tactile applications such as capacitive robot e-skin, geo-e-skin, capacitance tomography and various appliances like elevator keys, a node is required which carries a capacitance measuring cell or a component thereof. In addition to measuring capacitance, to obtain the "perception" capability of contact and/or non-contact, it is also necessary for the nodes to be provided with computing power to integrate the physical quantities measured and to obtain the "perception" result to the outside world. For ease of industrial manufacturing and deployment in the context of the internet of things, it is also desirable to provide nodes that are convenient for mass production and deployment in the field. The plurality of nodes are respectively arranged at the designated positions of the space, and the existence, the movement and the change of the surface, the nearby and internal substances and the objects of the space are measured and sensed.

To achieve the above object, an R-SpiNNaker chip is provided according to an embodiment of the present application. The R-SpiNNaker chip is an analog-to-digital hybrid chip. In the digital part, the SpiNNaker chip architecture is used for reference, so that the SNN system suitable for contact and/or non-contact 'perception' is constructed. An analog quantity sensor is provided in the analog part, and a trigger pulse (also simply referred to as "pulse") for a neuron of the SNN is generated based on the measured analog quantity and supplied to the SNN for "perception" processing.

The network system formed by the R-SpiNNaker chips is called an R-SpiNNaker system. The R-SpiNNaker system is designed primarily for solving the problems of modular analog-to-digital conversion, transmission and calculation of tactile characteristic signals of large-area electronic skin analog tactile signals, and only needs to consider the analog signal problem of contact tactile sensation for general electronic skins such as resistive or piezoelectric skins, but needs to consider the analog signals of contact tactile sensation and non-contact tactile sensation for some electronic skins such as capacitive skins. The contact touch sense mainly realizes single-point 3-dimensional force sensing, multipoint cooperative shape, surface texture and hardness sensing, and the non-contact touch sense can realize approach sensing, material sensing and structure sensing.

An important technical reason why the development of machine touch is far behind that of machine vision is that machine vision can use a general-purpose CPU or GPU chip to perform centralized signal processing, and in a machine touch scene, a sensor array needs to be spread over the electronic skin of the whole body of a robot, and due to the crosstalk problem caused by a large number of leads and long-line transmission of a large number of weak analog signals, it is almost impossible to perform centralized signal processing using a general-purpose chip.

The most reasonable approach is to convert the analog signal into a digital signal and perform distributed signal processing nearby using a dedicated haptic chip. In contrast to a centralized signal processing chip requiring a CPU or GPU with powerful computing power, a single haptic chip core only needs to have limited computing power but has powerful network communication power, and can form a neuron computing network with powerful computing power by a plurality of haptic chips distributed on an electronic skin.

The industrial production of large-area electronic skins requires that the nodes of the electronic skins must be modularized, standardized and spliceable. The large-area electronic skin is formed by splicing standardized electronic skin nodes. The splicing among the nodes comprises physical splicing, analog signal splicing and digital neuron network splicing, and the R-SpiNNaker system is mainly designed to realize the dynamic splicing of analog signals and a digital neuron network. The splicing problem to be solved by the R-SpiNNaker system includes the connection problem of analog and digital signals between chips.

The R-SpiNNaker node needs to support time-sharing measurement of capacitance over several to tens of capacitance channels. Capacitance resolution reaches the femtofarad (ff, 1F — 1e15 ff), which requires integrating the CDC within a node and allowing the CDC to measure capacitance on multiple capacitance channels in time division. There is also a need to address the problem of interference between multiple channels and reduce chip area and cost.

Human beings do not have the function of non-contact touch sense, but machine touch sense can have the function of non-contact touch sense, and the non-contact touch sense of the capacitive touch sensor can realize the following two functions: the method senses the approaching, moving and material conditions of external objects and senses the internal structures of contact objects.

Through the capacitance change of the electric fields at different spatial positions, the approaching speed and material classification of the object can be judged. Based on the principle that the capacitance value is in direct proportion to the electrode area, the larger the area of the capacitor plate is, the longer the detection distance of the capacitive sensor is. Thus, there is a need for an R-SpiNNaker node or R-SpiNNaker system that can change the position and/or area of a capacitive plate to sense changes in the position, movement, and/or material of an object relative to the capacitive plate.

And (3) carrying out internal structure analysis perception on the object through Electric Capacitance Tomography (ECT).

Based on the result of the perception, it is also desirable to perform a corresponding action. Execution is also desirably distributed, with one or more nodes being able to base their decision and act accordingly. For example, when the manipulator is contacted with high temperature or sharp objects, or is accidentally contacted with a human body, the hand needs to be retracted immediately for avoiding.

To meet one or more of the above-mentioned needs, embodiments according to the present application provide an R-spin maker chip and an R-spin maker system.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1A shows a schematic diagram of a SpiNNaker chip architecture;

FIG. 1B illustrates a schematic diagram of a capacitance measurement unit that measures capacitance using CDC;

FIG. 2 shows a schematic diagram of an R-SpiNNaker chip architecture according to an embodiment of the present application;

FIG. 3 shows a schematic diagram of an R-SpiNNaker chip architecture according to yet another embodiment of the present application;

FIG. 4A illustrates a schematic diagram of an R-SpiNNaker system according to an embodiment of the present application;

FIG. 4B illustrates a schematic diagram of an R-SpiNNaker system according to yet another embodiment of the present application;

FIG. 4C illustrates a schematic diagram of an R-SpiNNaker system according to yet another embodiment of the present application;

FIG. 5A illustrates a block diagram of an analog signal router according to an embodiment of the present application;

FIG. 5B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 5C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 6A illustrates a block diagram of an analog signal router, according to yet another embodiment of the present application;

FIG. 6B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 6C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 7A illustrates a schematic diagram of a capacitive channel according to an embodiment of the present application;

FIG. 7B illustrates a schematic diagram of a capacitive channel according to yet another embodiment of the present application;

FIG. 8A illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 8B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application;

FIG. 9 illustrates an R-SpiNNaker system according to an embodiment of the present application;

FIG. 10 illustrates an R-SpiNNaker system according to yet another embodiment of the present application;

FIG. 11 illustrates an R-SpiNNaker system according to yet another embodiment of the present application;

FIG. 12A shows a schematic diagram of an R-SpiNNaker chip architecture according to yet another embodiment of the present application;

FIG. 12B shows a schematic diagram of an R-SpiNNaker chip architecture according to yet another embodiment of the present application;

fig. 13A shows a schematic diagram of SNN unit construction SNN according to an embodiment of the present application;

fig. 13B shows a schematic diagram of SNN construction by a SNN unit according to yet another embodiment of the present application;

FIG. 14 shows a schematic diagram of an R-SpiNNaker chip architecture according to yet another embodiment of the present application;

FIG. 15 illustrates an R-SpiNNaker system according to yet another embodiment of the present application;

FIG. 16A shows a schematic diagram of a SNN constructed in the R-SpiNNaker system according to an embodiment of the present application; and

FIG. 16B shows a schematic diagram of a SNN constructed in the R-SpiNNaker system according to yet another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 2 shows a schematic diagram of an R-SpiNNaker chip architecture according to an embodiment of the present application.

The R-SpiNNaker chip shown in fig. 2 includes a computing unit, a digital router, and an SNN (impulse neural network) unit.

The calculation unit generates an AER packet and provides it to the digital router, which in turn provides the AER packet to one or more neurons in the SNN. The calculation unit is, for example, a CPU core or a hardware circuit. The calculation unit generates an AER package according to a specified rule, for example, according to collected external data, measurement values of sensors, time, results generated by other calculations. Optionally, the AER packet carries the address of the computing unit that generated the AER packet or the node to which the computing unit belongs. Still alternatively or additionally, the computing unit generates the AER package at a specified time or according to specified rules, e.g., immediately in response to receiving the collected external data, or triggered by a size of an accumulated value of the external data exceeding a threshold.

Optionally, the computing unit includes an activation function unit and an encoder. The activation function unit realizes the activation function of the SNN neuron, the measured value of the analog quantity is used as the input of the activation function unit, and the output of the activation function unit represents the pulse output by the SNN neuron. The encoder encodes the pulses into AER packets and provides them to the digital router.

The R-SpiNNaker chip also includes point-to-point ports or network ports. For purposes of clarity, ports connecting to a shared media network such as Ethernet are referred to as network ports, and ports connecting to point-to-point links such as I2C are referred to as point-to-point ports. In deployment, the use of point-to-point ports helps to reduce the cost of the R-SpiNNaker chip compared to the use of network ports. Embodiments that use point-to-point ports to connect adjacent R-SpiNNaker nodes and form a R-SpiNNaker system are also described below. Alternatively, the digital routers of the R-SpiNNaker chip may communicate with each other in a wireless manner (e.g., via 5G DTD (Device-To-Device), bluetooth, etc.).

The digital router of the R-SpiNNaker node exchanges AER packets with other R-SpiNNaker nodes through point-to-point ports or network ports. The digital router receives the AER packet from the computing unit without sending the AER packet to the computing unit. The digital router receives AER packets from the SNN unit and also sends AER packets to the SNN unit.

In one embodiment, the computing unit is directly connected to the digital router, without going through an on-chip bus, thereby further reducing the cost of the R-spin maker chip. The SNN unit is also directly connected to the digital router. The digital router is directly connected to a point-to-point port or a network port. Optionally, the computation unit of R-SpiNNaker, the digital router and the SNN unit are connected to each other by an on-chip bus. The computing unit and the SNN unit are not directly connected with the point-to-point port or the network port, and only exchange data packets through the digital router to communicate with other R-SpiNNaker nodes.

Optionally, the digital router unicasts, multicasts, or broadcasts the AER packet. For example, the digital router determines the destination to forward a received AER packet based on the address carried by the AER packet or the source from which the AER packet was received. AER packet forwarding is targeted to one or more SNN neurons, and/or point-to-point ports or network ports.

The SNN unit includes a plurality of SNN neurons. The SNN neuron receives a neural pulse (pulse for short) and outputs the pulse. The AER packet represents a pulse. The reception of the AER packet by the SNN neuron represents the received pulse, and the output of the AER packet by the SNN neuron represents the output pulse. The SNN neuron receives an AER packet from the digital router and outputs the AER packet to the digital router. Computational models of SNN neurons are state of the art, and SNN neuron models that may occur in the future are also utilized in accordance with embodiments of the present application. For example, the SNN unit is a CPU core, and the SNN neuron is implemented by a program or thread running on the CPU core.

A plurality of SNN neurons constitute SNNs (impulse neural networks). In the present specification, SNNs have a prescribed topology and meaningful functions as compared with SNN units, and each SNN neuron constituting the SNNs has prescribed parameters. The SNN is created. The SNNs in the SNN units are created or adjusted by configuring or programming the digital routers, e.g., updating routing tables of the digital routers. So that the SNN neurons of a SNN unit can be used to construct different SNNs at different times. A plurality of SNNs may exist simultaneously in the SNN unit.

The topology of the SNN and the number of SNN neurons are known for a given application or processing function. For example, the designated function is to identify one of a plurality of keys that a user's finger is approaching or touching from the capacitance values collected by the capacitance sensor. As another example, the specified function is to detect an object in which an abnormality occurs in the space.

The SNN neurons in the SNN have a unidirectional connection relationship. The SNN neurons in the SNN receive AER packets sent by zero, one or more SNN neurons, and output AER packets to one SNN neuron. According to an embodiment of the application, the connection relationships of the SNN's neurons are embodied by a routing table maintained by the digital router for AER packets. The routing table of the digital router records one or more destination SNN neurons, or point-to-point ports or network ports, to which addresses in the received AER packet are to be routed.

Optionally, the SNN includes input layer neurons, intermediate layer neurons, and output layer neurons. The input layer neurons receive input to the SNN, and the output of the input layer neurons is provided to the intermediate layer neurons. The output of the intermediate layer neurons is provided to the intermediate layer neurons or to the output layer neurons. The output of the output layer neuron is taken as the output of the SNN where the neuron is located. It will be appreciated that according to embodiments of the present application, both the input and output of the SNN neuron are processed by a digital router. Physically, the output of the SNN neuron is an AER packet provided to the digital router, and the digital router determines the destination neuron to forward to based on the address of the SNN neuron carried in the AER packet that generated the AER packet. And the SNN neurons determine the time for outputting the AER packet according to the parameters of the SNN neurons according to the AER packet received by the SNN neurons from one or more SNN neurons.

The R-SpiNNaker chip shown in fig. 2 is a pure digital chip and may not include analog circuits such as the CDC. Compared with an analog-digital hybrid circuit, the pure digital capacitor is lower in manufacturing cost and lower in noise or interference sensitivity.

Fig. 3 shows a schematic diagram of an R-SpiNNaker chip architecture according to yet another embodiment of the present application.

The R-SpiNNaker chip shown in FIG. 3 is further integrated with CDC and ADC (analog to digital converter) on the basis of the R-SpiNNaker chip of the embodiment shown in FIG. 2. Therefore, the single R-SpiNNaker chip not only has the ability of constructing the SNN network and sensing, but also can collect and measure external analog quantity. Although the cost is increased, the integration level of the chip is improved, the chip has more abundant functions, and the measurement and the perception of analog signals can be independently completed.

Referring to fig. 3, the CDC and the ADC of the R-SpiNNaker chip are each connected to a computing unit, the respective inputs of the CDC and the ADC are provided as inputs to the computing unit, and the computing unit generates an AER packet representing the neural impulses from the measured values of the outputs of the CDC and/or the ADC.

In fig. 3, the CDC includes an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC). The R-SpiNNaker chip also includes a capacitive port. And the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) are respectively coupled with the capacitance port of the R-SpiNNaker chip. Whereby the CDC measures self-capacitance and/or mutual capacitance through the capacitive port. The ADC is used to convert analog signals such as voltage, current into digital values and provide them to the computing unit. Optionally, the R-SpiNNaker chip further includes a port (not shown) for providing an analog signal to the ADC. Still optionally, the ADC is connected to a capacitive port to acquire an analog signal.

The CDC/ADC measures and outputs either capacitance or an analog signal at any time, periodically, or in response to an operating command. Whereas SNN derives from the measured values a characteristic of the perceived measured object, e.g. recognising an accidental approach of a finger intentionally approaching a key instead of a satchel/clothing or the like. With existing or future arising techniques, the SNN may be trained or configured to provide the ability to perceive the measured object.

FIG. 4A shows a schematic diagram of an R-SpiNNaker system according to an embodiment of the present application.

In FIG. 4A, the R-SpiNNaker system includes 2R-SpiNNaker chips (410 and 420) as shown in FIG. 3. The R-SpiNNaker chip 410 is connected to the digital router (via a network port or point-to-point port) of the R-SpiNNaker chip 420 and exchanges AER packets. Thus AER packets (pulses) emitted by the SNN neurons of the SNN unit of R-SpiNNaker chip 410 can be forwarded by the digital routers of the two R-SpiNNaker chips (410 and 420) to the SNN neurons of the SNN unit of R-SpiNNaker chip 420. Thereby, the SNN neurons of the two R-SpiNNaker chips can be used for constructing the SNN. And a plurality of SNNs can exist in the R-SpiNNaker chip consisting of two R-SpiNNaker chips at the same time, and the SNNs respectively and/or cooperatively sense/process the analog quantity measured by the ADC/CDC.

In the digital router of the R-SpiNNaker chip, the AER packet is forwarded to a network port or a point-to-point port through a configuration routing table so as to forward the AER packet between the two R-SpiNNaker chips. The routing table also records the destination (e.g., the designated SNN neuron or neurons) to which AER packets received from a network port or point-to-point port are forwarded. To support multicast or broadcast, multiple forwarding targets may be recorded in the routing table.

FIG. 4B shows a schematic diagram of an R-SpiNNaker system according to yet another embodiment of the present application.

In FIG. 4B, the R-SpiNNaker system includes 2R-SpiNNaker chips (430 and 450). The R-SpiNNaker chip 430 is connected to the digital router (via a network port or point-to-point port) of the R-SpiNNaker chip 450 and exchanges AER packets.

The R-spin maker chip 430 and the R-spin maker chip 450 each further include an analog signal router and a plurality of capacitive ports. The capacitor port is connected with a capacitor plate outside the R-SpiNNaker chip. The analog signal router connects the capacitive port to an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC) of the CDC. The CDC may thus measure capacitance using any combination of capacitive plates to which multiple capacitive ports are connected.

The analog signal router is configured or programmed to form different capacitive channels. The capacitive channel couples the CDC to one or more capacitive plates forming the capacitance being measured.

In the embodiment of fig. 4B, the digital router of the R-spin maker chip is further coupled to an analog signal router, the digital router forwards a data packet carrying configuration information or programming information of the analog signal router to the analog signal router, and the analog signal router obtains the configuration information or programming information from the data packet and sets the opening or closing of one or more switches of the analog signal router to form a capacitive channel. Thus, the digital routers exchange at least 2 data packets, AER packets with data packets carrying configuration information or programming information for the analog signal routers. Data packets carrying configuration information or programming information for an analog signal router include, for example, an address indicating the destination R-SpiNNaker chip, so that the digital router forwards such data packets according to the address. One or both of the R-spin maker chip 430 and the R-spin maker chip 450 serve as configuration chips to provide data packets carrying configuration information or programming information of the analog signal routers to the analog signal routers of the two chips. Such data packets are optionally provided to the R-SpiNNaker chips 430 and 450 by an external device.

A specific implementation of the analog signal router will also be described below.

Optionally, each of the R-spin maker chip 430 and the R-spin maker chip 450 further includes an analog signal port. In fig. 4B, ports (432, 434, 452, and 454) where a dotted line connection exists between the R-spin maker chip 430 and the R-spin maker chip 450 are analog signal ports. The R-SpiNNaker chip 430 is correspondingly connected with the analog signal port of the R-SpiNNaker chip 450 to transmit analog signals between the R-SpiNNaker chip 430 and the R-SpiNNaker chip 450, so that the CDC of the chip 430 can measure the capacitance by using the capacitive plate of the chip 450, and conversely, the CDC of the chip 450 can measure the capacitance by using the capacitive plate of the chip 430.

In the embodiment of FIG. 4B, the R-SpiNNaker chip 430 is the same as the R-SpiNNaker chip 450. Alternatively, the R-SpiNNaker chips of the R-SpiNNaker system may be the same or different.

In an alternative embodiment, the ADC is also connected to an analog signal router and acquires the analog signal to be measured or converted from the analog signal router.

FIG. 4C shows a schematic diagram of an R-SpiNNaker system according to yet another embodiment of the present application.

In FIG. 4C, the R-SpiNNaker system includes 4R-SpiNNaker chips (460, 470, 480, and 490). The 4R-SpiNNaker chips are different.

Each R-spin router chip of the R-spin router system includes digital routers and point-to-point ports (462, 464, 466, and 468, 472, 474, 476, and 478, 482, 484, 486, and 488, 492, 494, 496, and 498) for exchanging AER packets. The point-to-point port 464 of the R-SpiNNaker chip 460 is connected with the point-to-point port 478 of the R-SpiNNaker chip 470, the point-to-point port 466 of the R-SpiNNaker chip 460 is connected with the point-to-point port 482 of the R-SpiNNaker chip 480, the point-to-point port 484 of the R-SpiNNaker chip 480 is connected with the point-to-point port 498 of the R-SpiNNaker chip 490, and the point-to-point port 476 of the R-SpiNNaker chip 470 is connected with the point-to-point port 492 of the R-SpiNNaker chip 490, so that data packets can be randomly forwarded between the digital routers between the R-SpiNNaker chips of the R-SpiNNaker system.

For ease of deploying the R-spin maker system and configuring the routing tables of the digital router, the point-to-point ports of the R-spin maker chip carry directional attributes (e.g., east (E), west (W), south (S), and north (S)). In the routing table, a designated point-to-point port, such as an east-side point-to-point port, may serve as a destination address for the configured forwarded packet. When the R-SpiNNaker chip is deployed, the R-SpiNNaker chips in the R-SpiNNaker system are arranged in rows and/or columns. Adjacent R-SpiNNaker chips belonging to the same row are connected with each other through respective east/west point-to-point ports; adjacent R-SpiNNaker chips belonging to the same column are connected to each other through respective south/north point-to-point ports. Therefore, each R-SpiNNaker chip only comprises 4 point-to-point ports, and the random communication among the digital routers of the R-SpiNNaker chips of the R-SpiNNaker system can be realized. This also reduces the cost of the R-SpiNNaker chip. The cost of a point-to-point port is also significantly lower than a network port of a shared medium such as ethernet.

Although the R-SpiNNaker system of FIG. 4C includes 4R-SpiNNaker chips. It is understood that the R-spin maker system may include any number of R-spin maker chips to cover different areas of the region to be inspected and to provide more SNN units to construct SNNs of different sizes and different computing capabilities.

The R-SpiNNaker chip 480 optionally includes a CDC to measure and output a measured capacitance value. The R-SpiNNaker chip 480 also includes a calculation unit to generate AER packets according to the capacitance values output by its CDC for supply to the digital router.

The R-spin maker chips 460, 480, and 490 each include an analog signal router, a capacitance port (not shown), and an analog signal port (not shown). The analog signal router will form capacitive channels between the R-spin pick chips 460, 480, and 490 such that the CDC of the R-spin pick chip 460 can measure capacitance using the capacitive plates connected to any one or more of the R-spin pick chips 460, 480, and 490. The digital routers of the R-spin routers 460, 480, and 490 forward packets to the analog signal routers of the respective nodes to configure or program the analog signal routers.

The R-SpiNNaker chips 470 and 490 each include SNN cells. The SNN is constructed by the SNN units of the R-spin chips 470 and 490 to perceive the external object using the CDC such as the R-spin chip 480.

Optionally, the R-SpiNNaker chip 470 is a purely digital circuit and does not include an analog signal router and/or CDC. So that the R-SpiNNaker chip 470 can have a lower cost.

Fig. 5A illustrates a block diagram of an analog signal router according to an embodiment of the present application.

The analog signal router is used to dynamically establish a capacitive channel between the CDC and the capacitive plates such that the CDC may measure capacitance using one or more capacitive plates. The capacitance measured by the CDC may include, for example, one capacitive electrode (self-capacitance) or 2 capacitive electrodes (mutual capacitance). The analog signal router also causes the capacitive electrode of the measured capacitance to be comprised of one or more capacitive plates.

In fig. 5A, the CDC includes a self-capacitance signal line port (SCA). Accordingly, the analog signal router includes, for example, a self-capacitance signal line ASC (511), a plurality of switches (KAS1-KAS4, also referred to as capacitive port coupled switches), and a plurality of capacitive ports (510, 512, 514, and 516) for connecting the capacitive plates. The plurality of capacitive ports may be identical to each other.

As an example, the capacitive port coupling switches are in one-to-one correspondence with the capacitive ports, and each capacitive port is connected to the self-capacitance signal line ASC through the corresponding capacitive port coupling switch (511). Thus, by closing a capacitive port coupling switch (e.g., KAS1), its corresponding capacitive port (510) is coupled to self-capacitance signal line ASC (511), and thus to the self-capacitance signal line port (SCA) of the CDC. It is to be understood that the capacitive port to self-capacitance signal line ASC (511) may be directly connected or indirectly connected via one or more components and/or leads, and the term "coupled" is used to express various connection modes including direct connection and indirect connection, and the application is not intended to limit the implementation thereof. Such that a signal applied by the CDC to its self-capacitance signal line port (SCA) is passed to a capacitance port (e.g., 510) corresponding to a capacitance port coupling switch (e.g., KAS1), which in turn acts on a capacitance plate coupled to the capacitance port (510). And optionally, signals received from the capacitive port (e.g., 510) are also transmitted to the self-capacitance signal line port (SCA) of the CDC through the capacitive port coupling switch (e.g., KAS1), and then the self-capacitance signal line ASC (511). It will be appreciated that the capacitive plates and the CDC may not be part of an analog signal router according to embodiments of the present application, but rather the capacitive plates are externally connected to the analog signal router capacitive ports, and one or more ports of the CDC (e.g., self-capacitance signal line port (SCA)) are externally connected to the analog signal router (e.g., via the CDC coupling switch KSC). The analog signal router is thus adaptable to capacitive plates of various shapes, sizes, and/or materials, and CDCs of various specifications.

With continued reference to FIG. 5A, when the plurality of switches (e.g., KAS1-KAS4) are closed simultaneously, self-capacitance signal line ASC (511) is connected to the plurality of capacitance ports (510, 512, 514, and 516) such that the stimulus signal provided by CDC from capacitance signal line port (SCA) is simultaneously provided to the capacitance plates coupled to the plurality of capacitance ports (510, 512, 514, and 516). In this way, the capacitor plates coupled to the capacitor ports respectively have equal potential, so that the capacitor plates coupled to the capacitor ports respectively are spliced to form a capacitor plate with a larger area (or different shape) as the electrode of the measured capacitance. The larger capacitor plate facilitates measuring the effect of objects further from the capacitor plate on the capacitance formed by the capacitor plate. In a similar manner, by closing a plurality of switches of different numbers, the capacitor plates respectively coupled to the capacitor ports of different numbers are spliced to form capacitor plates of different areas (or different shapes).

According to the embodiment of the application, the analog signal router is further used for CDC time-sharing measurement of the capacitance formed by the capacitor plates connected with the same or different capacitor ports. Such that a single CDC and the capacitive plates coupled to multiple capacitive ports form multiple identical or different capacitive measurement cells at different times. For example, at time T1, switch KAS1 is closed, while the other switches (KAS2-KAS4) are open, and the CDC and the capacitive plate coupled to capacitive port 510 form a capacitive measurement cell; at time T2, switch KAS2 is closed, while the other switches (KAS1, KAS3, KAS4) are open, and the CDC and the capacitive plate coupled to capacitive port 512 form a capacitive measurement cell. Optionally, the CDC forms a capacitance measurement unit with the same or different capacitive plates in sequence at a plurality of times, continuous or discontinuous.

In some cases, the CDC measures self-capacitance through its self-capacitance signal line port (SCA). By coupling the self-capacitance signal line port (SCA) of the CDC to, for example, capacitance ports KAS3 and KAS4, the CDC measures the self-capacitance with respect to ground of the capacitive plates formed by the splicing together of the capacitive plates to which capacitance ports KAS3 and KAS4 are respectively connected.

For simplicity, all switches (KAE1, KAE2, KAE3, KAE4, and optionally KAEC) in an analog signal router are also referred to as an analog switch matrix.

In the example of fig. 5A, the CDC includes a single port (self-capacitance signal line port (SCA)), such that the analog signal router routes the analog signal for the CDC through only a single self-capacitance signal line ASC (511). Alternatively, if the CDC includes an excitation signal line port (AEC), the analog signal router routes the analog signal for the CDC through the excitation signal line, accordingly. Still alternatively or additionally, the CDC includes a mutual capacitance input signal line port (ACC), and accordingly the analog signal router routes the analog signal for the CDC through the mutual capacitance input signal line.

FIG. 5B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

The analog signal router of the embodiment of fig. 5B includes an excitation signal line (AE), a mutual capacitance input signal line (AC), an optional self-capacitance signal line (ASC), a plurality of switches (KAE1-KAE5, KAC1-KAC5, KAS1-KAS5, also referred to as capacitive port coupled switches), and a plurality of capacitive ports (510, 512, 514, 516, and 518) for connecting the capacitive plates. In the embodiment of fig. 5B, a plurality of CDC coupled switches (KAEC, KACC and optionally KSC) are also included. The CDC includes an excitation signal line port (AEC), a mutual capacitance input signal line port (ACC), and an optional self capacitance signal line port (SCA).

The combination of excitation signal lines (AE), mutual capacitance input signal lines (AC) and optional self-capacitance signal lines (ASC) is called a set of connection lines. Each connection line in the connection bank (excitation signal line (AE), mutual capacitance input signal line (AC) and optional self-capacitance signal line (ASC) is connected in the same manner as the capacitance port and the CDC.

The connection lines of the connection line set are connected with the ports of the CDC in a one-to-one mode. The number of the CDC coupling switches is the same as the number of the connection lines of the connection line set and also as the number of the ports of the CDC, such that each CDC coupling switch couples the connection line of its corresponding connection line set to the corresponding port of the CDC. For example, the excitation signal line (AE) is connected to the excitation signal line port (AEC) through a CDC coupling switch (KAEC), the mutual capacitance input signal line (AC) is connected to the mutual capacitance input signal line port (ACC) through a CDC coupling switch (KACC), and the self capacitance signal line (ASC) is connected to the self capacitance signal line port (SCA) through a CDC coupling switch (KSC). The connection lines of the connection banks are thus connected only to ports of the CDC corresponding thereto and are not connected to other ports of the CDC. Optionally, to adapt a CDC having a different port configuration, a connection line number of the connection bank of the analog signal router is no less than a port number of the CDC such that each port of the CDC is connected to one of the connection lines of the connection bank and two or more ports of the CDC are prevented from being connected to the same connection line.

Each connection line of the set of connection lines (excitation signal line (AE), mutual capacitance input signal line (AC) and optional self-capacitance signal line (ASC)) is coupled to one of the capacitive ports via a set of capacitive port coupling switches (referred to as a sub-switch set). These sub-switch groups also form part of the analog switch matrix. The number of the switches in the sub-switch group is the same as the number of the connecting lines of the connecting line group.

In fig. 5B, the connection line group includes 3 connection lines, and thus each sub-switch group includes 3 switches. For example, capacitive port 510 is coupled to (each connection line of) the set of connection lines through a set of sub-switches (KAE1, KAC1, KAS1), and capacitive port 512 is coupled to the set of connection lines through a set of sub-switches (KAE2, KAC2, KAS 2). With such an arrangement, each capacitive port is enabled to be connected to any of the connection lines of the set of connection lines, thereby enabling the capacitive port to be coupled to any one of the ports (AEC, ACC or SCA) of the CDC.

According to an embodiment of the application, at most only one switch of the plurality of switches of the sub-switch group is closed at any time, while the other switches of the sub-switch group are open, so that the capacitive port is coupled to at most only one connection line of the connection line group at any time. So that each sub-switch group also avoids coupling two or more connection lines of a connection line group. It is allowed that all switches of the group of sub-switches are open at a certain time.

At some point, it is permissible for the plurality of sub-switch groups to have their respective corresponding capacitive ports all coupled to one of the connection lines of the connection line group, so as to simultaneously couple a certain connection line of the connection line group to the plurality of capacitive ports. By connecting a plurality of capacitive ports to the same connecting line, the capacitive ports have equal potential, so that the capacitive plates connected to the capacitive ports respectively are combined into one or integral capacitive plate. For example, the sub-switch group (KAE1, KAC1, and KAS1, with KAC1 closed) couples capacitive port 510 to the mutual capacitive input signal line AC, and the sub-switch group (KAE2, KAC2, with KAS2, with KAC2 closed) couples capacitive port 512 to the mutual capacitive input signal line AC, thereby coupling the mutual capacitive input signal line AC to the plurality of capacitive ports (510 and 512) at that time, and thus simultaneously coupling the respective capacitive plates of the plurality of capacitive ports (510 and 512). Thereby enlarging the area of the capacitor plate coupled to the mutual capacitance input signal line AC or changing the shape of the capacitor plate.

The analog signal router according to the embodiment of fig. 5B is further adapted to different modes of operation of the CDC. When the CDC is operating in a mode for measuring mutual capacitance, the CDC applies an excitation signal to the measured capacitance through an excitation signal line port (AEC) of the CDC, and acquires a response of the measured capacitance to the excitation signal through a mutual capacitance input signal port (ACC) of the CDC. By way of example, one plate of the mutual capacitance being measured is connected to capacitance port 510, while the other plate is connected to capacitance 512. When the CDC is operating and an excitation signal is output through an excitation signal line port (AEC), connecting the excitation signal line port (AEC) of the CDC to an excitation signal line AE of the connected bank by closing the CDC coupling switch KAEC, connecting the excitation signal line AE to the capacitive port 510 by closing the switch KAE1 (and opening the switches KAC1 and KAS1), thereby applying the excitation signal output by the excitation signal line port (AEC) of the CDC to a capacitive plate coupled to the capacitive port 510; and simultaneously closing switch KACC and switch KAC2 to couple capacitive port 512 to a mutual capacitance input signal line port (ACC) of the CDC and opening switches KAE2, KAS2 and KSC, whereby the CDC receives through its mutual capacitance input signal line port (ACC) a response of a capacitive plate coupled to capacitive port 512 to the aforementioned stimulus signal.

When the CDC operates in a measured self-capacitance mode, the CDC applies a stimulus to the measured capacitance through its self-capacitance signal line port (SCA) and acquires a response. By way of example, the capacitive plate of the measured self-capacitance is connected to capacitive port 516. The capacitor plate to which capacitive port 516 is connected forms self-capacitance Cs with ground. In operation of the CDC, capacitive port coupling switch KAS4 is closed (switch KAE4 is open from switch KAC4) and switch KSC is closed to connect a self-capacitance signal line port (ASC) of the CDC to self-capacitance signal line ASC and thus to the capacitive plate of coupling capacitive port 216.

In a further optional mode of operation, the CDC measures the self-capacitance through its self-capacitance signal line port (SCA) while also measuring the mutual capacitance through its excitation signal line port (AEC) and mutual capacitance input signal line port (ACC). For example, CDC coupling switches KAEC and KACC are closed, and switches KAE1 and KAC2 are closed (switches KAC1, KAS1, KAE2 and KAS2 are opened), CDC coupling switches KSC and switches KAS4 are closed (switches KAE4 and KAC4 are opened), thereby simultaneously measuring the mutual capacitance formed by the capacitive plates connected to capacitive ports 510 and 512, and the self-capacitance of the capacitive plate connected to capacitive port 516.

According to yet another embodiment of the present application, the CDC includes only the excitation signal line port (AEC) and the mutual capacitance input signal line port (ACC) and does not include the self capacitance signal line port (SCA), but replaces the function of the self capacitance signal line port (SCA) by the excitation signal line port (AEC) or the mutual capacitance input signal line port (ACC). In this case, the connection line set of the analog signal router according to the embodiment of the present application includes the excitation signal line (AE) and the mutual capacitance input signal line (AC), and may not include the self capacitance signal line (ASC). Accordingly, switches (KAS1-KAS5, and KSC) for connecting self-capacitance signal lines (ASCs) are not included in the analog switch matrix.

As yet another example, the area, position, and/or shape of the capacitive plates of the capacitive measurement cell formed by the CDC and the capacitive plates is adjusted by opening or closing a plurality of capacitive port coupling switches corresponding to the same connection line of the connected line group. For example, a plurality of capacitive port coupled switches (KAE1-KAE5) corresponding to an excitation signal line (AE) are selectively opened and closed (forming a capacitive plate having a given area, position and/or shape) such that an excitation signal line port (AEC) of the CDC forms an excitation path with the capacitive plate to which each of the plurality of capacitive port coupled switches is coupled; a plurality of capacitive port coupling switches (KAC1-KAC5) corresponding to the mutual capacitance input signal line (AC) are selectively opened and closed (forming capacitive plates having a given area, position and/or shape) such that a CDC mutual capacitance input signal line port (ACC) forms a responsive path with the capacitive plates to which the plurality of capacitive port coupling switches are respectively coupled. Thus, two capacitor plates with given areas are connected with the CDC in such a way, a complete mutual capacitance measuring unit can be formed, and the mutual capacitance can be measured. And various capacitor plate combination modes are provided, and the capacitor plate combination mode corresponds to various mutual capacitance measuring units. Different mutual capacitance measuring units can be constructed at different moments through time-sharing control over the analog switch matrix, and time-sharing mutual capacitance measurement is carried out. When the self-capacitance measurement is performed, self-capacitance plates with different areas are formed by different combinations of the self-capacitance signal line (ASC) and the switches KAS1-KAS5, and the self-capacitance plates are connected to the CDC through the opening and closing of the self-capacitance signal line (ASC) and the CDC coupling switch KSC, so that different self-capacitance measurement units are formed, and the self-capacitance measurement is performed. Different self-capacitance measuring units can be constructed at different moments through time-sharing control over the analog switch matrix, and time-sharing self-capacitance measurement is carried out.

As another example, the capacitor unit for a circular touch key includes 4 sectors forming a circle and respectively connected to the capacitor ports 510, 512, 514 and 516, and the capacitor unit further includes a same plate a disposed opposite to the 4 sectors, the plate a being connected to the capacitor port 518. Plate A forms a mutual capacitance with each of the 4 sector plates (denoted A1, A2, A3, and A4). According to the analog signal router of the embodiment of the present application, the CDC is connected to each of the 4 mutual capacitances (a1, a2, A3, and a4) at different times to measure each mutual capacitance. At yet another time, switches KAE1-KAE4 are all closed to connect capacitive ports 510, 512, 514 and 516 to excitation signal line AE and to combine the 4 sector electrodes into one integral plate by forming an equipotential surface through the excitation signal line, the combined 4 sector electrodes forming a mutual capacitance with plate A, and the mutual capacitance being measured by CDC. Therefore, through the analog signal router, the fact that multiple capacitors are measured in a time-sharing mode through a single CDC and a plurality of fixed capacitor ports is achieved.

Fig. 5C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

As yet another example, the CDC also includes a synchronized clock signal line port (CLK) and an actively shielded signal line port (SHD), the analog signal router of the embodiment of fig. 5C also including an actively shielded signal line (ASH) and a synchronized clock signal line (ACLK) as compared to the analog signal router illustrated in fig. 5B.

Alternatively, the actively shielded signal line (ASH) is coupled to the capacitive port in the same way as the other connection lines of the connection line set, i.e. by the switch coupling of the sub-switch sets, one capacitive port is coupled to only one connection line of the connection line set at the same time, whereas the actively shielded signal line (ASH) may be coupled to a plurality of capacitive ports simultaneously. At this time, the active shield signal line (ASH) becomes one of the connection lines of the connection line group. In an example where the connection line group includes 4 connection lines (excitation signal line (AE), mutual capacitance input signal line (AC), self capacitance signal line (ASC), and active shield signal line (ASH)), each sub-switch group includes a corresponding 4 switches. In the example of fig. 5C, a capacitive port coupling switch (KASH1-KASH4) is also included for coupling the capacitive port with an actively shielded signal line (ASH).

In operation, if an actively shielded signal line (ASH) is connected to the shield electrode (230) through a capacitive port (e.g., 514) and an excitation signal line (AE) is connected to the capacitive plate through a capacitive port (516), then the switch (KASH3) is closed concurrently with switch KAE4 to provide an actively shielded signal to the shield electrode (530) concurrently with the excitation signal to the capacitive plate connected to the capacitive port (516).

Optionally or further, the analog signal router further comprises an actively shielded signal port (560), and the actively shielded signal line (ASH) is connected to the actively shielded signal port (560). The actively shielded signal port (560) is dedicated to connecting actively shielded signal lines (ASH) without connecting to other connection lines of the set of connection lines. At this time, the analog switch matrix of the analog signal router may not include switches (KASH1-KASH 4). In some cases, the CDC provides an actively shielded signal having a greater amplitude (voltage and/or current) than the excitation signal, and accordingly the actively shielded signal line ASH and/or the actively shielded signal port (560) is adapted to transmit the actively shielded signal. Since the actively shielded signal port (560) does not need to be connected to other connection lines of the connection line set, the actively shielded signal port is connected to the actively shielded signal line (ASH) only through a switch (not shown) or directly without a switch. In operation, if an actively shielded signal line is connected to the shielding electrode (532) through the actively shielded signal port (560) and an excitation signal line AE is connected to the capacitive plate through the capacitive port (510), the switch (KAE1) is closed accordingly to provide an actively shielded signal to the shielding electrode (532) at the same time as the excitation signal is provided to the capacitive plate connected to the capacitive port (510).

Alternatively, the CDC does not provide an actively shielded signal port, but rather an actively shielded signal is generated by an analog signal router according to embodiments of the present application. For this purpose, the analog signal router includes a follower (not shown in fig. 5C) connecting the excitation signal line (AE) and the actively shielded signal line (ASH) to apply the excitation signal obtained by the excitation signal line from the CDC to the actively shielded signal line (ASH). Still alternatively, a switch is further provided between the excitation signal line (AE) and the active shield signal line (ASH) to open or close the connection therebetween.

Optionally, the analog signal router further comprises a synchronous clock signal line (ACLK) and a synchronous clock port (562). The synchronous clock port 562 may optionally be the same or different from the capacitive port. The synchronous clock signal line (ACLK) does not belong to a connection bank. An optional switch is included between the synchronous clock signal line (ACLK) and the synchronous clock port (562) to open or close the connection between the two. The synchronous clock signal line (ACLK) is coupled to the synchronous clock signal line port (CLK) of the CDC.

The CDC coupled switch of the analog signal router further includes a switch KSH and a switch KCL, an active shield signal port (SHD) for connecting the active shield signal line (ASH) and the CDC, and a synchronous clock signal line port (CLK) for the synchronous clock signal line (ACLK) and the CDC, respectively.

In one embodiment, the synchronized clock port (562) receives a synchronized clock signal from outside the analog signal router, and the synchronized clock signal line (ACLK) provides the synchronized clock signal obtained from the synchronized clock port (562) to the synchronized clock signal line port (CLK) of the CDC through the CDC coupled switch KCL. The synchronized clock signal indicates the timing at which the CDC initiates the capacitance measurement. Optionally, the synchronized clock signal also indicates a plurality of operational phases of the CDC measurement capacitance.

FIG. 6A illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

In the example of fig. 6A, the capacitance measurement unit includes multiple CDCs (CDC1 and CDC2 are shown). Multiple CDCs may be operated simultaneously to measure multiple capacitances simultaneously.

Referring to fig. 6A, the set of connection lines of the analog signal router includes an excitation signal line (AE), a mutual capacitance input signal line (AC), and a self capacitance signal line (ASC). The CDC1 and the CDC2 are connected to the connection line set through respective CDC coupling switches. By way of example, the CDC1 corresponding CDC coupling switches (KAEC1 and KACC1) are closed (and switches KAE1 and KAC2 are closed) such that CDC1 measures the mutual capacitance formed by the capacitive plates connected to capacitive ports (610 and 612) through capacitive ports (610 and 612). At the same time or at different times when the mutual capacitance is measured by the CDC1, the CDC coupled switch (KSC2) corresponding to the CDC2 is closed (and switch KAS4 is closed), so that the CDC2 measures the self-capacitance through the capacitive port (614).

In the embodiment shown in FIG. 6A, each connection of the set of connections is shared by CDC1 and CDC 2. The same connection line cannot be used simultaneously from slave CDC1 and CDC2 to avoid collisions. Thus, if the CDC coupling switch KAEC1 is closed, switch KAEC2 should be open to avoid connecting connection line AE to both the excitation signal line ports (AEC) of CDC1 and CDC 2. The CDC1 and CDC2 share the connection lines of the connected banks in a time-sharing manner. For example, CDC1 is connected to the mutual capacitance input signal line AC at time T1, whereas CDC2 is not connected to the mutual capacitance input signal line AC at time T1 but is connected to the mutual capacitance input signal line AC at a time different from T1.

According to the embodiment of fig. 6A, an analog signal router connects a plurality of CDCs through sets of CDC coupling switches (KAEC1, KACC1 and KSC1, and KAEC2, KACC2 and KSC2), each set of CDC coupling switches for connecting a set of connection lines to one of the CDCs. And the CDCs use the same connection line of the connection line group in time division. At any time, at most one connection line of the set of connection lines is connected to one CDC.

FIG. 6B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

In contrast to the embodiment of fig. 6A, the analog signal router of the embodiment of fig. 6B provides a shared excitation signal line AE for multiple CDCs, while providing each CDC its exclusive mutual capacitance input signal line (AC1, AC2, and AC 3). The capacitance ports are respectively connected with the corresponding sub-switch groups (KAE1, KAC11, KAC21 and KAC31, KAE 31, KAC31 and KAC31, KBE 31, KBC31 and KBC31, KBE 31, KCE 31 and KCC31, KCC31 and KCC31, KCE 31, KCC31 and KCC31, KCC31 and KCC31,

) Connected to the excitation signal line AE and the mutual capacitance input signal lines (AC1, AC2, and AC 3).

In the example of fig. 6B, the capacitance measurement unit includes multiple CDCs (CDC1, CDC2, and CDC3 are shown). Multiple CDCs may operate simultaneously to measure multiple capacitances simultaneously. CDC1 and CDC2 each include an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC), CDC3 includes only a mutual capacitance input signal line port (ACC). By way of example, the excitation signal line ports of CDC1 and CDC2 are independent of each other, so that CDC1 and CDC2 may output different excitation signals simultaneously. Whereas CDC3 does not have an excitation line port, but instead borrows the excitation line port (AEC) of CDC1 or CDC 2. Taking the example that CDC3 borrows the excitation signal line port (AEC) of CDC1, when measuring mutual capacitance, a excitation signal is provided to the measured capacitance through the excitation signal line port (AEC) of CDC1, and the response of the measured capacitance to the excitation signal is received from the mutual capacitance input signal line port (ACC) of CDC 3. Optionally, each CDC also measures a self-capacitance. When the self-capacitance is measured by CDC1 or CDC2, a mutual capacitance input signal line port (ACC) thereof applies a stimulus to a plate of the measured capacitance in a time-sharing manner and acquires a response, and the applied stimulus is generated by a stimulus signal source of CDC1 or CDC2 itself. CDC3 measures self capacitance with its mutual capacitance input signal line port (ACC) time-divisionally applying a stimulus, generated by a stimulus signal source such as CDC1, to the plates of the measured capacitance and acquiring a response. Within each CDC, the excitation signal source of CDC1 is coupled to CDC 3.

According to the embodiment of fig. 6B, the analog signal router includes a plurality of CDC-coupled switch sets (KAEC1 and KACC1, KAEC2 and KACC2, and KACC3), each CDC-coupled switch set corresponding to one of the CDCs, the CDC-coupled switch sets for coupling its corresponding CDC to the set of connection lines. Optionally, the number of switches of the CDC-coupled switch bank is the same as the number of ports of the corresponding CDC. The CDCs use the same connection line of the connected bank in a time-sharing manner. At any time, a connection line of the connection line set is connected to at most one CDC.

To adapt to the change in the CDC quantity, in the embodiment shown in fig. 6B, the group in which the excitation signal line (AE) is located is referred to as a connection line group, and the group in which one of the mutual capacitance input signal lines (AC1, AC2, or AC3) is located is referred to as a capacitance channel connection line group. In FIG. 6B, the sets of connection lines include only excitation signal lines (AE), and each set of capacitive channel connection lines includes one of the mutual capacitance input signal lines. The connecting wire of the capacitor channel connecting wire group is also connected with the capacitor port through the capacitor port coupling switch. Correspondingly, the capacitor ports are coupled with each connecting line of the connecting line group and all the capacitor channel connecting line groups through the sub-switch groups, so that the switch number of the sub-switch groups is the same as the sum of the number of all the connecting lines of the connecting line group and all the capacitor channel connecting line groups, and the sub-switch groups are in one-to-one correspondence with the connecting line groups. For a sub-switch group, the switches of the sub-switch group are at most only one switch closed at any time, and the other switches are all open, so that the capacitive port is at most only coupled to one of all the connection lines connecting the group of lines and all the groups of capacitive channel connection lines at any time.

At some point, it is permissible for the plurality of sub-switch groups to have their respective corresponding capacitive ports all coupled to one of the connection lines of the connection line group or the capacitive via connection line group, so as to simultaneously couple a certain connection line of the connection line group or the capacitive via connection line group to the plurality of capacitive ports.

The capacitor channel connection line sets correspond to the CDC one by one. Therefore, if the number of CDCs needing coupling is increased, the capacitance channel connection line set is only required to be increased according to the number of CDCs. While the set of connection lines provides only one in the analog signal router. In one example, a single set of connection lines is connected to all CDCs through a CDC coupling switch. In another example, the set of connection lines is coupled to one of the CDCs, while the excitation signal source is shared within the plurality of CDCs.

Fig. 6C illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

In contrast to the embodiment of fig. 6B, the connection line set in the embodiment of fig. 6C further includes an active shield signal line (ASH) and/or a synchronous clock signal line (ACLK). The active shield signal line (ASH) corresponds to the excitation signal line (AE). An actively shielded signal line (ASH) is coupled to the CDC through a CDC coupling switch. Optionally, each CDC shares an actively shielded signal line (ASH), such that the actively shielded signal line (ASH) is coupled to one of the CDCs through one CDC coupled switch.

Optionally, the synchronous clock signal line (ACLK) does not belong to a connection line of the connection line group. Still alternatively, the CDCs share a synchronous clock signal line (ACLK)

In the embodiment of fig. 6C, each sub-switch group further includes a switch (KASH1, KASH2 … … KCSH4) for connecting the active shield signal line (ASH) to the capacitive port corresponding to the sub-switch group. The analog signal router further comprises a CDC coupling switch KCL for connecting the synchronous clock signal line (ACLK) to the synchronous clock signal line port (CLK) of the CDC.

In the example of fig. 6C, the set of connection lines is shared by all CDCs, and the set of capacitance-channel connection lines correspond one-to-one to the CDCs. In order to adapt to the increase of CDC, capacitance channel connection line sets are added in the same quantity as that of CDC, CDC coupling switch sets are added and used for connecting the newly added capacitance channel connection line sets and the newly added CDC, and capacitance port coupling switches are added for each sub-switch set and used for coupling capacitance ports corresponding to the sub-switch set where the sub-switch set is located to the newly added capacitance channel connection line sets.

According to the analog signal router of the embodiments of the present application, different paths are formed by opening or closing of the switches of the analog switch matrix, through which the CDC measures different capacitances coupled to the different paths. The path formed by the analog signal router for measuring capacitance for the CDC is referred to as a capacitance channel. The capacitive channel is used to couple the CDC and the capacitive plate such that the CDC measures the capacitance formed by the capacitive plate. The capacitive path is dynamic and can be changed as the open or closed state of the switch changes. The capacitive channels are simultaneously correlated and, over time, are created, changed or released.

According to embodiments of the present application, a capacitive channel is, in general, a path formed by an analog switch matrix coupling a set of connection lines to at least one capacitive port and a capacitive-to-digital converter at a given moment. The capacitive channel includes a path for an electrical signal formed by one or more connection lines of the set of connection lines, one or more capacitive ports, and one or more switches of the analog switch matrix having a specified state. Typically, for a single CDC, at the same time, an analog signal router provides only a single capacitive channel to the CDC, such that the CDC measures capacitance through the single capacitive channel. And changing a switch state of the analog signal router to provide another capacitive channel to the CDC such that the CDC measures capacitance through the other capacitive channel as the capacitance measurement is completed or changes over time.

The capacitive channels have designated resources provided by the analog signal router, including one or more connection lines connecting the bank/bank of capacitive channels, one or more capacitive ports, and one or more switches of the analog switch matrix having designated states. At the same time, the resource is exclusively occupied by the capacitance channel. At different times, each capacitive channel may share resources.

For multiple CDCs, at the same time, the analog signal router may provide a respective capacitive channel to each CDC. The capacitive channels provided for each CDC have different resources from each other to avoid interference among the capacitive channels.

The capacitance channels include self-capacitance channels and mutual capacitance channels. The CDC measures the self-capacitance through a self-capacitance channel and the mutual capacitance through a mutual capacitance channel.

FIG. 7A shows a schematic diagram of a capacitive channel according to an embodiment of the present application.

In fig. 7A, bold lines indicate mutual capacitance channels for measuring mutual capacitance a 1; the dashed line indicates the self-capacitance channel for measuring the mutual capacitance Cs. In FIG. 7A, the mutual capacitance path includes resources including an excitation signal line (AE), a mutual capacitance input signal line (AC), capacitance ports (710 and 712), switches KAE1, KAC2, KAEC and KACC.

In a capacitive path for measuring mutual capacitance A1, by setting states of a plurality of switches of an analog signal router, an excitation signal line port (AEC) of a CDC is connected to an excitation signal line (AE) through a switch KAEC, a mutual capacitance input signal line port (ACC) of the CDC is connected to a mutual capacitance input signal line (AC) through a switch KACC, a capacitive port (710) is connected to the excitation signal line (AE) through a switch KAE1, and a capacitive port (712) is connected to the mutual capacitance input signal line (AC) through a switch KAC 2. The capacitor plates connected to the respective capacitor ports 710, 712 form a mutual capacitance A1. When the mutual capacitance measurement is performed, the switches KAE1, KAC2, KAEC and KACC are closed and the remaining switches of the analog switch matrix of the analog signal router remain open, so that the excitation signal line port (AEC) of the CDC, the mutual capacitance a1 and the mutual capacitance input signal line port (ACC) and the corresponding connection lines constitute a path for measuring the mutual capacitance a1, on which the CDC measures the mutual capacitance a 1.

In fig. 7A, the resources of the self-capacitance channel include a self-capacitance signal line (ASC), capacitance ports (720 and 722, respectively coupling capacitance plates A3 and a4), switches KAS3, KAS4, and KSC. In the example of fig. 7A, the self-capacitance signal line port (ASC) of the CDC is connected to the self-capacitance signal line (ASC) through switch KSC, capacitor plate A3 is connected to the self-capacitance signal line (ASC) through switch KAS3, and capacitor plate a4 is connected to the self-capacitance signal line (ASC) through switch KAS 4. Capacitor plates A3 and a4 constitute the plates of self-capacitance Cs. When a self-capacitance measurement is made, switches KAS3, KAS4 and KSC are closed, the other switches of the analog switch matrix are open, and capacitor plates A3 and a4 are at equal potential, so that capacitor plates A3 and a4 combine to form one plate of the self-capacitance Cs being measured. The ground acts as the other plate of the self-capacitance Cs. The self-capacitance Cs, the self-capacitance signal line (ASC), the ground and the connecting lines therebetween constitute a path for measuring the self-capacitance Cs, and the CDC measures the self-capacitance Cs on the path.

Further, by closing the switches (e.g., KAS1, KAS2 … …) connecting the self-capacitance signal line (ASC) with other capacitance ports, a further capacitance path is formed which connects the capacitance plate for measuring the self-capacitance to more capacitance ports, so that the capacitance plate of the self-capacitance can have a larger area and a different shape. Thus, according to embodiments of the application, different capacitive channels are formed by configuring the opening or closing of the switches of the analog signal router, such that the CDC allows different capacitances to be measured through the different capacitive channels without changing the deployed hardware.

FIG. 7B shows a schematic diagram of a capacitive channel according to yet another embodiment of the present application.

The example of fig. 7B shows two capacitive paths existing simultaneously, one being a mutual capacitive path (indicated by the bold line) and the other being a self capacitive path (indicated by the dashed line). CDC1 measures the mutual capacitance Cm through a mutual capacitance channel and CDC2 measures the self-capacitance Cs through a self-capacitance channel. Optionally, CDC1 performs respective capacitance measurements simultaneously or time-divisionally with CDC 2.

In the mutual capacitance path, switches KAE1, KAC2 and switches KAEC, KACC corresponding to CDC1 are closed such that the excitation signal line (AE), the mutual capacitance input signal line (AC), the capacitance ports (730, 732), and the switches (KAE1, KAC2, KAEC, and KACC) form a mutual capacitance path.

In the self-capacitance channel, switches KBS3, KBS4 and switch KSC2 corresponding to CDC2 are closed, so that the self-capacitance signal line (ASC), the capacitance ports (740 and 742) and the switches (KBS3, KBS4 and KSC2) form the self-capacitance channel. The reason for closing switches KBS3 and KBS4 at the same time is to enlarge the area of the capacitor plate of the self-capacitance.

In the analog switch matrix, the switches other than switches KAE1, KAC2, KAEC, KACC, KBS3, KBS4, and KSC2 are kept off.

Thus, a plurality of capacitive channels are formed simultaneously by the analog signal router such that a plurality of CDCs simultaneously perform measurements of a plurality of capacitances through respective capacitive channels in parallel.

In an alternative embodiment, CDC1 shares the drive signal source internally with CDC2, and CDC2 utilizes the drive signal line port (AEC) of CDC 1. In this case, CDC1 and CDC2 cannot operate simultaneously. Accordingly, in fig. 4C. The mutual capacitance channel and the self-capacitance channel provided by the analog signal router can not work at the same time, but work in a time-sharing mode. For example, at time T1, CDC1 measures the mutual capacitance Cm through the mutual capacitance channel, while at a later or different time T2, CDC2 measures the self-capacitance Cs through the self-capacitance channel.

FIG. 8A illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

In contrast to the analog signal router shown in fig. 7A, the analog signal router of fig. 8A also includes an analog routing controller. The analog routing controller couples to and controls opening or closing of one or more switches of an analog switch matrix of the analog signal router. By arranging the analog routing controller, the capacitance channel provided by the analog signal router can be changed in a working site. It will be appreciated that an analog routing controller is not necessary. The opening or closing of the switches of the analog switch matrix can be set in a prior art manner on the production line and/or on the work site of the analog router. While the analog routing controller takes over control of the switches of the analog switch matrix and may build a higher description level, e.g. abstracting the control objects as capacitive channels instead of switches. The external part thus for example instructs the analog routing controller to create, release the specified capacitive channel, without the external part having to be concerned with the state of the individual switches required for building the capacitive channel.

As an example, the analog routing controller in fig. 8A records states of all switches of the analog switch matrix of the analog signal router, the analog routing controller is connected to a control terminal of each switch of the analog switch matrix, and the control terminals of the switches determine actions and/or states of the switches according to a control signal received from the analog routing controller. The analog routing controller also receives external configuration information to change the state of one or more switches of its recorded analog switch matrix. And the configuration information further indicates an opportunity for the analog routing controller to apply the recorded state of the one or more switches to the control terminals of the one or more switches.

Again by way of example. The analog routing controller is operated by an internal component such as a CPU or an external component as a control interface of the analog signal router. The CPU or a program memory accessed by the CPU may be programmed to set the manner in which the CPU operates the analog signal router. By operating or configuring the analog routing controller, the internal or external components control the analog signal routers to form capacitive channels.

As yet another example, the analog routing controller includes a memory. The state of one or more switches of the analog switch matrix, recorded by the memory, is set by programming the memory, or is simulated at different times.

Fig. 8A shows an example in which the analog routing controller includes a matrix control register set, a sequence state controller, and a selector.

The matrix control register set includes a plurality of registers, the registers of the matrix control register set including a plurality of bits, each bit corresponding to state information of one of the switches of the analog switch matrix. In one example, the number of bits of the register of the matrix control register set is the same as the number of switches of the analog switch matrix, so that each bit of the register corresponds to one switch of the analog switch matrix. In yet another example, the number of bits of the register of the matrix control register set is smaller than the number of switches of the analog switch matrix, e.g., the register is a 32-bit register. So that the plurality of registers of the matrix control register set collectively store state information for all switches of the analog switch matrix.

The matrix control register sets have recorded therein state information for the switches of an analog switch matrix, e.g., for various capacitive channels. For example, each register of the matrix control register set corresponds to state information of a switch of the analog switch matrix required to construct one of the capacitive channels. In yet another example, multiple (but not all) registers of the matrix control register bank correspond to state information for switches of an analog switch matrix required to construct one of the capacitive channels. The sequential state controller successively selects a plurality of registers required for constructing a certain capacitance channel, and the state of a plurality of switches in the analog switch matrix is set by using the value of each bit of the registers.

A sequential state controller is a sequencer, state machine, or microprocessor that outputs a specified value or sequence of specified values corresponding to an input. The value output by the sequence state controller is used to indicate the selection of one of the registers in the matrix control register set. Optionally, the matrix control register bank is coupled to a selector, which selects one of the registers of the matrix control register bank as an output according to an output of the sequence state controller and provides the output to the plurality of switches of the analog switch matrix.

In one example, the number of bits in the registers of the matrix control register bank is the same as the number of switches in the analog switch matrix, and accordingly, to create a capacitance channel, the sequential state controller selects a single register of the matrix control register bank to set the state of each switch of the analog switch matrix. In yet another example, the number of bits of the registers of the matrix control register set is less than the number of switches of the analog switch matrix, and accordingly, to create one capacitance channel, the sequential state controller sets the states of the plurality of switches of the analog switch matrix by selecting the plurality of registers of the matrix control register set by a sequence of values.

The selector outputs each bit of the register of the currently selected matrix control register group to the control port of the switch corresponding to the analog switch matrix so as to control the opening or closing of the corresponding switch.

The matrix control register set may be configured to write thereto control information for controlling the switches of the analog switch matrix. The values of the registers of the matrix control register set are updated, for example, by an external configuration port or processor.

FIG. 8B illustrates a block diagram of an analog signal router according to yet another embodiment of the present application.

Fig. 8B illustrates an example in which the analog routing controller includes a register 810. The number of bits of the register 810 is, for example, the same as the number of switches of the analog switch matrix, the bits of the register 810 correspond to the switches of the analog switch matrix of the analog routing controller one to one, and each bit of the register 810 of the analog routing controller is coupled to one of the switches of the analog switch matrix of the analog routing controller, and the bits of the register 810 are used for controlling the opening or closing of the corresponding switch. For example, an analog switch matrix has 128 switches, and accordingly the width of the register 810 of the analog routing controller is 128 bits.

According to the embodiment of fig. 8B, the value of register 810 of the analog routing controller corresponds to one or more capacitive channels provided by the analog signal router at a time. When the value of register 810 corresponds to multiple capacitive channels, these capacitive channels exist simultaneously. In response to an update of the value of the register 810 of the analog routing controller, one or more switches of the analog switch matrix of the analog signal router (corresponding to the changed bits of the register) are reset to an operational state, and accordingly, the capacitive path provided by the analog signal router also changes.

In an alternative embodiment, the registers 810 of the analog routing controller of FIG. 8B correspond to a plurality of bus addresses. For example, a register is 128 bits wide, corresponding to 4 addresses of a 32-bit bus (e.g., a 0-A3), and the 32 bits of the register are accessed by each bus address. An external component, such as a CPU, also coupled to the bus, sets the registers by accessing the bus addresses (a 0-A3) to update the capacitive channels provided by the analog signal router at runtime.

In the example shown in fig. 8B, the analog routing controller further includes a matrix control register set 820 and a selector.

The selector selects one of the matrix control register groups 820 as an output according to an instruction of an external component such as a CPU, and sets the register 810 with the selected output. The selector selects the output bits of the register to be respectively coupled to one of the switches of the analog switch matrix of the analog signal router to control the open or closed state of the corresponding switch.

In some cases, the width of the bus (such as 32 bits) is much smaller than the number of switches of the analog switch matrix. By setting the matrix control register group, an external component such as a CPU is enabled to output all state information necessary for setting the analog switch matrix through a single bus access, thereby setting all switches of the analog switch matrix at the same time.

Alternatively, the control ports of the switches of the analog switch matrix are provided with bus addresses, so that an external component can directly set the switches of the analog switch matrix in a manner of accessing the bus. Although the number of switches set at a time is smaller than the bus width, the state update of all the switches of the analog switch matrix is completed by a plurality of bus cycles. And in some cases, only some of the switches of the analog switch matrix change state between two adjacent capacitance measurements, so that only the states of these switches need to be updated.

The R-SpiNNaker system includes a plurality of nodes and can be deployed over a wider range. By measuring the capacitance(s) that may be present anywhere in space, the characteristics of objects in space are sensed. The R-SpiNNaker system includes a plurality of R-SpiNNaker chips distributed at different locations. Each R-SpiNNaker chip includes one or more CDCs and is connected to one or more capacitive plates. And the CDC and the capacitor plate are dynamically combined into a capacitance measuring unit. Besides changing the area of the capacitor plate to adapt to the target to be detected with different distances, shapes and materials, the capacitor plates at different positions can be cooperated in space/time to obtain the space/time perception of the target to be detected, such as distinguishing/tracking.

FIG. 9 illustrates an R-SpiNNaker system according to an embodiment of the present application.

Referring to FIG. 9, the R-SpiNNaker system includes two R-SpiNNaker chips (900 and 950). The two R-SpiNNaker chips have, for example, the same configuration. All chips of the R-SpiNNaker system have the same configuration, and large-scale production and deployment of the R-SpiNNaker chips are facilitated. Optionally, each R-SpiNNaker chip of the R-SpiNNaker system has a different configuration, e.g., some nodes include the CDC and some nodes do not include the CDC, to further reduce costs.

The two R-SpiNNaker chips (900 and 950) each include an analog signal router (910 and 960) and CDC (CDC1 and CDC 2). Analog signal router 910 is connected to CDC1, and analog signal router 960 is connected to CDC 2. By way of example, the CDC includes a shared port (ACC/SCA) that functions as both a mutual capacitance input signal line port (ACC) and a self capacitance signal line port (SCA).

An analog signal router (e.g., 910 or 960) includes a mutual capacitance input signal line AC, a cross-chip mutual capacitance input signal line IAC, a plurality of switches (KIACE, KIACW, KIACS, and KIACN, also referred to as analog signal port coupled switches). The combination of multiple switches of an analog signal router is referred to as an analog switch matrix. The mutual capacitance input signal line AC and the trans-chip mutual capacitance input signal line IAC are corresponding and connected to each other. The mutual capacitance input signal line AC is connected to a port (ACC/SCA) of the CDC. The cross-chip mutual capacitance input signal line IAC is coupled to the analog signal ports (IACE, IACW, IACs, and IACN) of the R-SpiNNaker chip through switches (KIACE, KIACW, KIACS, and KIACN), respectively. The switches (KIACE, KIACW, KIACS, and KIACN) are in one-to-one correspondence with the analog signal ports (IACE, IACW, IACS, and IACN) so as to couple the cross-chip mutual capacitance input signal line IAC to one or more analog signal ports, and an analog signal port (e.g., IACW912) can only be connected to the cross-chip mutual capacitance input signal line IAC through the switch (KIACW) corresponding thereto.

As an example, the four analog signal ports (IACE, IACW, IACS, and IACN) of the analog signal router 910 are all analog signal ports for inputting the signal line IAC across the mutual capacitance of the chip, and are respectively located in the east (E), west (W), south (S), and north (N) directions of the chip (the chip where the node is located) to which the analog signal router belongs, so that when the chip is disposed or mounted on the plane of the circuit board, leads are led out to the outside of the chip in the east, west, south, and north directions. In fig. 9, although for simplicity of drawing, and/or for the sake of planar topology, switch KIACS is shown directly connected to mutual capacitance input signal line AC, in an alternative embodiment, mutual capacitance input signal line AC is not directly connected to switch kiac, but rather extends the cross-chip mutual capacitance input signal line IAC through another wiring layer of the chip to the other end (south end) of the chip and connects switch KIACS. Alternatively, the mutual capacitance input signal line AC is directly connected to the switch KIACS. It is understood that the analog signal ports (IACW (912), IACN (914), IACE and IACS (916)) are also analog signal ports of the R-spin maker chip 900.

The analog signal port and the cross-chip connection line are adapted to connect to the outside of the chip and further to connect to another chip housing a node comprising an analog signal router (e.g., 960) according to embodiments of the application, such that the analog signal port and the cross-chip connection line may have different electrical characteristics than the mutual capacitance input signal line AC. Optionally, the analog signal port is also used to connect the capacitive plates.

In the example of fig. 9, analog signal port IACW (912) of analog signal router 910 is connected to a capacitive plate that forms a self-capacitance with respect to ground (Cs 1). CDC1 applies a stimulus to the capacitive plate connected analog signal port IACW (612) through mutual capacitance input signal line AC of analog signal router 910, cross-chip mutual capacitance input signal line IAC, switch KIACW, and measures its self-capacitance. An analog signal port (IACS) (916) is connected to an analog signal port (IACN) (974) of the analog signal router 920 via lead 915.

The R-spin router chip 900 includes four point-to-point ports (942, 944, 946, and 948), which are respectively located in the east (E) west (W) south (S) north (N) direction of the chip (chip where the node is located) to which the analog signal router belongs, so that when the chip is disposed or mounted on a circuit board isoplane, leads are led out in the east, west, south, and north directions outside the chip to connect the point-to-point ports of other R-spin routers chips and the digital router. The digital router forwards the received configuration or programming data packets to the analog signal router. For example, an analog routing controller of an analog signal router receives configuration or programming packets from which configuration or programming information for an analog switch matrix is obtained. In the example of fig. 9, point-to-point port 946 of R-spin maker chip 900 is connected to point-to-point port 992 of R-spin maker chip 950, so that the digital router of R-spin maker chip 900 exchanges packets with point-to-point port 992 and the digital router of R-spin maker chip 950 through point-to-point port 946, where the exchanged packets include configuration or programming packets and/or AER packets.

Analog signal router 960 is connected to CDC 2. Analog signal router 960 also includes analog signal ports (IACW (972), IACN (974), IACE, and IACS (976)). The analog signal port IACW (972) of the analog signal router 960 is connected to a capacitive plate that forms a self-capacitance (Cs2) with respect to ground. It is understood that the analog signal ports (IACW (972), IACN (974), IACE and IACS (976)) are also analog signal ports of the R-spin pick chip 950.

According to embodiments of the application, the analog signal routers may 910 and 960 work in concert to enable CDC1 to measure capacitance using capacitive plates connected to either of the R-SpiNNaker chips (900 and 950). Similarly, CDC2 can also measure capacitance using a capacitive plate connected to either of the R-SpiNNaker chips (900 and 950). By way of example, switch KIACS of analog signal router 910, switches KIACN and KIACW of analog signal router 960 are closed such that the port (ACC/SCA) of CDC1 is connected to the capacitive plate (and other switches are opened) through mutual capacitance input signal line AC of analog signal router 910, cross-chip mutual capacitance input signal line IAC (connection of mutual capacitance input signal line AC and cross-chip mutual capacitance input signal line IAC on the south side of analog signal router 910 is not shown in fig. 9), switches KIACS and analog signal port IACs (916), via lead 915, and further through analog signal port IACN (974), switch KIACN, cross-chip mutual capacitance input signal line IAC, switch KIACW, and analog signal port IACW (972) of analog signal router 960, such that CDC1 is able to measure self-capacitance Cs2 formed by the capacitive plate that is not in the same node as the CDC 1.

As yet another example, switch KIACN of analog signal router 960, switches KIACS and KIACW of analog signal router 910 are closed such that port (ACC/SCA) of CDC2 is connected to the capacitive plate (and other switches are opened) via lead 915 through mutual capacitance input signal line AC, cross-chip mutual capacitance input signal line IAC, switch KIACN and analog signal port IACN (974) of analog signal router 970, and further through analog signal port IACs (916), switch KIACS, cross-chip mutual capacitance input signal line IAC (cross-chip mutual capacitance input signal line IAC connected to switch KIACS, not shown in fig. 9), switch KIACW and analog signal port IACW (912) of analog signal router 910, thereby enabling self-capacitance Cs1 to be measured at CDC 2.

The R-SpiNNaker chips (900 and 950) or their analog signal routers (910 and 960) also include one or more capacitive ports (934, 984). The capacitor port is used for connecting a capacitor plate of the R-SpiNNaker chip. The analog signal routers (910 and 960) of the R-SpiNNaker chip also include capacitive port coupling switches (KAC1, KAC2, KAC3 and KAC4) corresponding to the capacitive ports one to one. The capacitive port coupling switch is used to connect or disconnect its corresponding capacitive port to a mutual capacitive input signal line (AC). The mutual capacitance input signal lines (AC) are simultaneously connected to the plurality of capacitance ports by simultaneously closing the plurality of capacitance port coupling switches, and further, the capacitance plates connected with the capacitance ports are connected. The analog signal router (e.g., 910 or 960) also includes a CDC coupled switch (KACC) for controlling the connection or disconnection of the mutual capacitance input signal line (AC) to the CDC port (ACC/SCA). The CDC of a node is disconnected from the analog signal router to reduce interference generated by the CDC, which is beneficial for the analog signal router of the node to provide signals for other nodes.

CDC1/CDC2 may be configurably coupled to one or more of the capacitive plates of each of the two R-SpiNNaker chips through analog signal router 910 and/or analog signal router 960, and the self-capacitance of these capacitive plates to ground may be measured. The capacitor plates of the R-SpiNNaker chip comprise capacitor plates connected through a capacitor port and/or capacitor plates connected through an analog signal port.

Fig. 10 illustrates an R-SpiNNaker system according to yet another embodiment of the present application.

In the example of fig. 10, the two R-spin akers constituting the R-spin aker system each include an analog signal router (1010 and 1050), and a CDC (CDC1 and CDC 2). Analog signal router 1010 is connected to CDC1, while analog signal router 1050 is connected to CDC 2. The CDC (CDC1 and CDC2) includes an excitation signal line port (AEC) and a mutual capacitance input signal line port (ACC). The CDC measures the mutual capacitance through an excitation signal line port (AEC), with a mutual capacitance input signal line port (ACC), and the self-capacitance through one of its ports.

In contrast to the R-spin maker chip shown in fig. 9, the analog signal router (e.g., 1010) of the R-spin maker chip in fig. 10 further includes an excitation signal line (AE) and a cross-chip excitation signal line (IAE) connecting the excitation signal line (AE), a capacitive port coupled switch (KAE1-KAE4) and corresponding capacitive port, analog signal ports (IAEE, IAEW, IAEs, IAEN), and CDC coupled switch (KAEC). The analog signal router (e.g., 1010) also includes an optional synchronous clock signal line port (CLK), a CDC coupled switch (KCL), a synchronous clock signal line (ACLK), a switch (KCLK), and a synchronous clock port ICLK.

The across-chip excitation signal lines (IAE) are respectively coupled with corresponding analog signal ports (IAEE, IAEW, IAES and IAEN) through switches (KIAEE, KIAEW, KIAES and KIAEN). The switches (KIAEE, KIAEW, KIAES and KIAEN) correspond to the analog signal ports (IAEE, IAEW, IAES and IAEN) one by one. Although the excitation signal line (AE) is shown in fig. 10 as being connected to the analog signal port (IAES) through a switch, it will be appreciated that in alternative embodiments, the excitation signal line (AE) is not directly connected to the analog signal port (IAES) through the switch, but rather is reconnected to the analog signal port (IAES) through the cross-chip excitation signal line IAE.

The capacitive port coupling switches (KAE1-KAE4) correspond to the capacitive ports one to one. Capacitive port coupling switches (KAE1-KAE4) are used to connect the respective capacitive ports to an excitation signal line (AE). A CDC coupled switch (KAEC) connects excitation signal line AE to an excitation signal line port (AEC) of the CDC.

The combination of the excitation signal line AE and the mutual capacitance input signal line AC is referred to as a connection line group. The combination of the cross-chip excitation signal line IAE and the cross-chip mutual capacitance input signal line IAC is referred to as a cross-chip connection line group.

A plurality of (e.g., two) capacitive port coupled switches (e.g., KAE1 and KAC1, KAE2 and KAC2) that connect the same capacitive port to respective connection lines of a group of connection lines, respectively, are referred to as a sub-switch group. At the same time, a plurality of (two) switches of the sub-switch group, at most only one, are closed, so that the capacitive port is connected at any time to at most one connection line of the connection line group. And through the arrangement of the sub-switch groups, the capacitance ports can be connected to any connecting line of the connecting lines at different moments. While switches (e.g., KAE1-KAE4) connecting multiple capacitive ports to one of the connecting lines of the connected bank may be closed at the same time to connect the connecting line to multiple capacitive ports at the same time.

In the embodiment of fig. 10, the analog signal port is connectable inside the analog signal router to only one of the cross-chip connection lines of the set of cross-chip connection lines. For example, the analog signal port IAEN of the analog signal router 1010 can only be connected to the cross-chip excitation signal line IAE, while the analog signal port IACN can only be connected to the cross-chip mutual capacitance input signal line IAC. So that for one analog signal port it is connected to a set of cross-chip connection lines (and thus only one of the cross-chip connection lines of the set of cross-chip connection lines) by only one switch. And for one capacitor port, the capacitor port is connected to the connecting line group through a sub-switch group comprising a plurality of switches, wherein the number of the plurality of switches of the sub-switch group is the same as that of the connecting lines of the connecting line group, and the switches of the sub-switch group correspond to the connecting lines of the connecting line group one by one.

By such an arrangement, the number of switches required by the analog signal router 1010 is reduced to reduce cost and complexity, and interference of the switches on transmitted signals when analog signals are transmitted over long distances is also reduced. For example, the analog signal port IACN is connected to the excitation signal line AC through only 1 switch (KIACN), while the capacitive port (e.g., 654) is connected to the mutual capacitance input signal line IAC through 2 switches. And also reserves sufficient analog signal ports and cross-chip connection line resources for transferring analog signals between chips. For example, the stimulus signal and the response to the stimulus signal may be transmitted simultaneously between two nodes.

Further, a plurality of analog signal ports (IAEE, IAEW, IAEs, IAEN) are connected across a chip connection line (e.g., IAE) through a plurality of switches (e.g., KIAEE, KIAEW, KIAES, KIAEN), respectively. By closing these switches simultaneously, the cross-chip connection lines are connected to multiple analog signal ports simultaneously to connect the cross-chip connection lines to multiple nodes and/or capacitive plates simultaneously.

A CDC coupled switch (KCL) of the analog signal router connects a synchronous clock signal line (ACLK) to a synchronous clock signal line port (CLK) of the CDC. The synchronous clock signal line (ACLK) is also connected to the synchronous clock port (ICLK) through a switch (KCLK). The switch (KCLK) is not necessary. Alternatively, the synchronous clock port ICLK is directly connected to the synchronous clock signal line (ACLK) without passing through the switch (KCLK).

Optionally, the synchronous clock port is replaced with an analog signal port, accordingly, the cross-chip connection set further comprises a cross-chip synchronous clock signal line (not shown) connected with the synchronous clock connection line, and the switch couples the cross-chip synchronous clock signal line to the analog signal port.

Continuing with FIG. 10, as an example, the mutual capacitance Cm formed by the capacitive plates connected to capacitive port 1014 and capacitive port 1054, respectively, is measured using CDC 2. The capacitor ports 1014 and 1054 are respectively located on two R-spin reader chips, so that the capacitor plates connected with the capacitor ports 1014 and 1054 form mutual capacitance in a larger space range. Further, the R-SpiNNaker system according to the embodiment of the present disclosure can detect objects appearing in the spatial range corresponding to the capacitor plates connected to the capacitor ports 1014 and 1054. The mutual capacitance input signal line port (ACC) of CDC2 is connected to capacitance port 1054 by closing switches KACC, KAC1 of analog signal router 1050. And closing switches KAEC, KIAEN of analog signal router 1050, closing switch kies and switch KAE3 of analog signal router 1010, connecting the excitation signal line input port (AEC) of CDC2 to capacitive port 1014. The CDC2 applies an excitation signal to the capacitive plate to which capacitive port 1014 is connected and obtains a response to the excitation signal from the capacitive plate to which capacitive port 1054 is connected and measures the mutual capacitance Cm.

In the example of fig. 10, switch KAEC, actuation signal line AE, cross-chip actuation signal line IAE, switch KIAEN, analog signal port IAEN, lead lines connecting analog signal port IAEN (1052) with analog signal port IAEs (1012) of analog switch matrix 1050, analog signal port IAEs (1012) of analog switch matrix 1010, cross-chip actuation connection line IAEC, switch kiase, actuation signal line AE, switch KAE3 with capacitive port 1014, and switch KACC, mutual capacitance input signal line AC and switch KAC1 of analog switch matrix 1050 form a capacitive channel for measuring mutual capacitance Cm. By changing the state of the switches of the switch matrix of analog switch matrix 1010 and/or analog switch matrix 1050, different capacitive channels are created such that CDC1 and/or CDC2 measure capacitance through the capacitive channels. The capacitive channel is dynamic. The capacitive plates to which the capacitive channels are connected and the CDC form a capacitance measuring cell.

Still by way of example, the capacitor plates to which the capacitor ports 1014 and 1016 are respectively connected form a mutual capacitance Cm 1; and the capacitor plates to which the capacitor ports 1056 and 1058 are respectively connected form a mutual capacitance Cm 2. Both CDC1 and CDC2 may measure mutual capacitances Cm1 or Cm2 through analog signal router 1010 and/or analog signal router 1050. As another example, switches KAEC, KACC, KAE3 of analog signal router 1010 are closed (other switches are open) with KAC4 such that CDC1 applies a stimulus signal to the capacitive plate connected to capacitive port 1014 through a stimulus signal line port (AEC), and obtains the response of mutual capacitance Cm1 to the stimulus signal from the capacitive plate connected to capacitive port 1016 through a mutual capacitance input signal line port (ACC). Thereby enabling measurement of mutual capacitance Cm1 with CDC 1.

By way of further example, switches KAEC and kias of analog signal router 1010 are closed and switches KIAEN and KAE3 of analog signal router 10500 are closed such that CDC1 applies an excitation signal through excitation signal line port (AEC) to the capacitive plates connected to capacitive port 1056; and switches KACC and KIACS of analog signal router 1010 are closed and switches KIACN and KAC4 of analog signal router 1050 are closed, such that CDC1 obtains the response of mutual capacitance Cm2 to the stimulus signal from the capacitive plate connected capacitive port 1058 through mutual capacitance input signal line port (ACC). The remaining switches are not mentioned to remain open. Thereby enabling measurement of mutual capacitance Cm2 with CDC 1.

Other embodiments, such as parallel measurement of two self capacitances or one self capacitance and one mutual capacitance, etc., switch configurations that cooperatively measure capacitance across a chip may likewise be switched as desired.

In order to facilitate the deployment, the R-SpiNNaker system can easily cover various or arbitrarily-shaped areas to be measured, and analog signal ports are arranged in different directions of a chip. For example, the analog signal ports are arranged in two orthogonal directions of the R-SpiNNaker chip, so that the R-SpiNNaker chip can be connected to other R-SpiNNaker chips in two directions, thereby forming an R-SpiNNaker system with a mesh topology.

Optionally, the CDC in the R-SpiNNaker chip further includes an actively shielded signal line port (SHD) (not shown in fig. 10), and accordingly, the analog signal router includes an actively shielded signal line, and a switch connecting the actively shielded signal line and the actively shielded signal line port. The connecting active shielding signal line is also connected to a capacitance port or an analog signal port through a switch.

Referring also to fig. 6B and 6C, to adapt the embodiment where the R-SpiNNaker chip includes multiple CDCs, in an alternative embodiment, a set of connection lines of the analog signal router and a set of capacitive channel connection lines. The connection line set is shared by a plurality of CDCs, and the capacitance channel connection line set is connected with the CDCs in a one-to-one correspondence manner, so that a corresponding capacitance channel connection line set is provided for each CDC. And the sub-switch group corresponding to each capacitance port comprises switches which are in one-to-one correspondence with the connection line groups and the connection lines of all the capacitance channel connection line groups. Optionally, the analog signal router provides a greater number of sets of capacitance channel connection lines to support more CDC when deployed. And optionally one or more sets of capacitance channel connection lines are not connected to the CDC, i.e. these sets of capacitance channel connection lines are not operational. Therefore, when the optical fiber is deployed, the analog signal router and the CDC can be provided separately without being configured together in advance, and the flexibility of deployment is improved. The analog signal router also comprises a cross-chip connecting wire group, wherein the cross-chip connecting wire group comprises cross-chip connecting wires which are in one-to-one correspondence with the connecting wires of the connecting wire group and all the capacitance channel connecting wire groups. The analog signal ports of the analog signal router in each direction of east (E), west (W), south (S) and north (N) correspond to cross-chip connecting lines of the cross-chip connecting line group one by one. For example, the cross-chip connection wire set includes 5 connection wires, and accordingly, the analog signal router includes 5 analog signal ports in each direction of east (E), west (W), south (S), north (N), respectively, for connecting corresponding connection wires of the cross-chip connection wire set. The two R-SpiNNaker chips are correspondingly connected through an analog signal port. For example, 5 analog signal ports of one R-SpiNNaker chip in east (E) direction are correspondingly connected with 5 analog signal ports of the other R-SpiNNaker chip in west (W) direction.

FIG. 11 illustrates an R-SpiNNaker system according to yet another embodiment of the present application.

In the example of FIG. 11, the R-SpiNNaker system includes 4R-SpiNNaker chips (1100, 1120, 1140, and 1160). The four chips each include an analog signal router (1110, 1130, 1150, and 1170) and CDC (CDC1, CDC2, CDC3, and CDC 4).

By networking multiple (e.g., four) chips, capacitive plates can be arranged in a wider range and capacitance and other analog quantities can be measured, the size of the SNN unit is enlarged, and a SNN with stronger calculation power and/or a larger number of SNNs can be constructed to meet various calculation requirements.

In the example of fig. 11, each R-spin pick chip includes 2 analog signal ports and 1 point-to-point port in each of the four east (E) west (W) south (S) north (N) (bottom right and top left). In the R-SpiNNaker system, the R-SpiNNaker chips are arranged in rows and/or columns. The R-SpiNNaker chips belonging to the same row are connected to each other through ports in east (E) west (W) direction. For example, referring to fig. 11, the R-spin maker chips 1100 and 1120 belong to the same row, and the analog signal ports (IACE and IAEE) toward east (E) of the R-spin maker chip 1100 and the point-to-point ports are correspondingly connected to the analog signal ports (IACW and IAEW) toward west (W) of the R-spin maker chip 1120 and the point-to-point ports. Thus, the digital routers of the R-spin maker chips 1100 and 1120, respectively, can exchange data packets, while the analog signal routers, respectively, can establish analog signal paths through both chips and capacitive channels. For another example, the R-spin maker chips 1100 and 1140 belong to the same column, and the south (S) analog signal ports (IACS and IAES) of the R-spin maker chip 1100 are connected to the point-to-point ports, and the north (N) analog signal ports (IACN and IAEN) of the R-spin maker chip 1140 are connected to the point-to-point ports. Thus, the respective digital routers of the R-SpiNNaker chips 1100 and 1140 can exchange data packets, while the respective analog signal routers can establish analog signal paths through both chips and capacitive channels. Furthermore, the R-spin maker chip 1100 serves as a relay, so that data packets can be exchanged between the R-spin maker chips 1120 and 1140, and a capacitive channel can be established.

In the example of fig. 11, when a plurality of R-spin chips form an R-spin maker system on a plane, each chip (not located at the boundary of a network) is connected to other chips in four directions, i.e., east, west, south, and north. In this way, the deployment of a larger number of R-SpiNNaker chips into an R-SpiNNaker system is simplified, and the number of nodes is not limited. And some chips connect 1, 2 or 3 other chips based on the location of the R-SpiNNaker chips in the network topology.

The leads connecting the R-SpiNNaker chips may have any shape, so that the arrangement of the plurality of R-SpiNNaker chips is not limited to a planar structure but may form a curved line or a curved surface.

Although the R-spin maker system illustrated in fig. 11 includes 2 nodes per row and 2 nodes per column, it will be appreciated that in alternative embodiments, the number of nodes included in the R-spin maker system may be arbitrary and not limited. The number of rows and columns of the R-SpiNNaker system is also arbitrary.

Alternatively, for a certain R-spin maker chip, the north (S) and south (N) directions thereof are referred to as the longitudinal direction, and other R-spin maker chips are connected in the longitudinal direction through analog signal ports/point-to-point ports in the north (S) and north (N) directions (the longitudinal direction), and further connected through other connected R-spin maker chips, so that the connected R-spin maker chips may have any number in the longitudinal extension. Similarly, the connected R-SpiNNaker chips can have any number in the lateral (east (E) west (W) direction) extension. Therefore, the requirements of various capacitance plate combinations in different shapes of regions to be measured, the requirements of motion measurement and calculation near nodes and the like are met.

The R-SpiNNaker chips are connected through the analog signal ports/point-to-point ports located in the designated direction of the R-SpiNNaker chips, and the configuration or programming of the analog switch matrix and the digital router of the analog signal router of each R-SpiNNaker chip is facilitated. For example, an east analog signal port/point-to-point port of one R-spin maker chip is correspondingly connected with only a west analog signal port/point-to-point port of another R-spin maker chip (while an east, south or north analog signal port/point-to-point port of the other R-spin maker chip is connected); the west-oriented analog signal port/point-to-point port of one R-SpiNNaker chip is correspondingly connected with the east-oriented analog signal port/point-to-point port of the other R-SpiNNaker chip; the south analog signal port/point-to-point port of one R-SpiNNaker chip is correspondingly connected with the north analog signal port/point-to-point port of another R-SpiNNaker chip (while the south, east or west analog signal port/point-to-point port of another R-SpiNNaker chip is connected); the north direction analog signal port/point-to-point port of one R-SpiNNaker chip is correspondingly connected with the south direction analog signal port/point-to-point port of the other R-SpiNNaker chip.

Thus, the analog signal port/point-to-point port of the chip has directional attributes in addition to corresponding designated cross-chip connection lines, and the switches connecting the analog signal port to the cross-chip connection lines also have the same directional attributes. The direction attribute is used to address the switch to be operated when programming or configuring the analog switch matrix and is also used to describe the point-to-point port to which the packet is to be forwarded in the routing table of the digital router.

Further, the analog signal ports/point-to-point ports of a node have row/column attributes (row or column number) in addition to directional attributes, and the switches connecting the analog signal ports to the cross-chip connections also have the same row/column attributes. The row/column attributes are used to address a set of switches to be operated upon when programming or configuring the analog switch matrix, and also to describe a set of point-to-point ports when setting up the routing table. Each chip of the R-spin maker system is thus addressable, further simplifying the configuration or programming of the analog switch matrix for each analog signal router, and slowing down the setup of the routing tables.

The R-SpiNNaker system of fig. 11 forms a capacitive sensor network. The CDC of one of the R-SpiNNaker chips allows the capacitance to be measured using the capacitive plates coupled to each of the R-SpiNNaker chips in the sensor network. For example, CDC1 measures a mutual capacitance through capacitance plates 1112 and 1114, a mutual capacitance through capacitance plates 1132 and 1134, a mutual capacitance through capacitance plates 1152 and 1154, and a mutual capacitance through capacitance plates 1172 and 1174. CDC1 also enables the measurement of mutual capacitance by capacitive plates 1112 and 1134, by combining (equipotential) capacitive plates 1112 and 1114, and combining (equipotential) capacitive plates 1132 and 1134 to measure the mutual capacitance formed by the two combined capacitive plates. The CDC1 can also measure the self-capacitance of a capacitive plate or a combination (equipotential) of multiple capacitive plates relative to earth. CDC1 also enables the sequential measurement of multiple capacitances, e.g., the sequential measurement of the mutual capacitance formed by capacitor plates 1112 and 1114, the mutual capacitance formed by capacitor plates 1132 and 1134, the mutual capacitance formed by capacitor plates 1152 and 1154, and the mutual capacitance formed by capacitor plates 1172 and 1174, at a desired timing sequence, e.g., to identify a change in position of an object relative to each node.

In e.g. electronic skin applications, functions similar to human conditioned and unconditioned reflexes, which are congenital reflexes that are inherent to humans, are required. It is a relatively low-level nerve activity, and can be completed by the participation of nerve centers (such as brainstem and spinal cord) below cerebral cortex. The unconditional reflex comprises a knee jerk reflex, a blink reflex, a hand contraction reflex, a sucking reflex of an infant, a urination reflex and the like, the conditioned reflex is an acquired reflex which is gradually formed in the life process of a human after birth, is completed under the participation of cerebral cortex through a certain process on the basis of the unconditional reflex, is a high-level neural activity and is a basic mode of the high-level neural activity. In the modularized electronic skin application, each basic unit of the electronic skin is provided with an R-SpiNNaker chip, when the basic unit of the electronic skin is subjected to certain external stimulation, the basic unit of the electronic skin can make a quick response decision and action (for example, when a manipulator contacts a high-temperature or sharp object, or accidentally contacts a human body, hand retraction and avoidance are needed immediately) similar to the condition or unconditional reflection of a human body without the participation of the brain of the robot or only the participation of partial areas of the brain of the distributed robot, so each R-SpiNNaker chip needs a control unit, and can make a decision of a local action and drive a local action actuator to execute a necessary action only in the chip or in cooperation with an adjacent chip. The local decision and control execution can be completed independently in the control unit, can be completed under the participation of the calculation unit and the SNN unit, and can be completed under the cooperation of the SNN unit and the control unit of a plurality of related chips.

Fig. 12A shows a schematic diagram of an R-SpiNNaker chip architecture according to yet another embodiment of the present application.

Fig. 12A shows an R-spin maker chip, which is integrated with a control unit and a GPIO unit on the basis of the R-spin maker chip of the embodiment of fig. 3. The GPIO unit provides a chip pin that drives an external execution unit. The output of the control unit is connected to the GPIO unit, and the control unit provides driving information for the execution unit through the GPIO unit. The execution unit is, for example, a motor, a switch, or the like, and causes the robot to perform an operation such as retracting the hand to avoid. The control unit is provided by software executed by a CPU core, or is implemented by a hardware circuit.

The control unit receives the data packet forwarded by the digital router. The data packets forwarded by the digital router to the control unit are AER packets or data packets dedicated to the control unit. The control unit extracts the action to be performed from the received data packet and drives the execution unit through the GPIO unit. Optionally, the control unit further comprises SNN neurons, which constitute SNNs, receive as output the AER packet provided by the digital router, and output the control signal provided to the GPIO unit. Still alternatively, the SNN neuron of the control unit and the SNN neuron of the SNN unit together constitute an SNN, and output a control signal supplied to the GPIO unit.

In the embodiment shown in fig. 12A, optionally, some or all of the chip pins required for the capacitive port/analog signal port are also provided by the GPIO unit. The control unit, the analog signal port and/or the capacitance port are connected to the pins provided by the GPIO unit through a configuration or programming mode. So that the chip pins are shared by the control unit, the analog signal ports and/or the capacitive ports. In some applications or one or more R-spin pick chips in an R-spin pick system, the pins provided by the GPIO are used for the capacitance port and the analog signal port to acquire an analog signal and/or measure capacitance, while in other R-spin pick chips, the pins provided by the GPIO are used as drive execution units. The pin count of a chip is limited and positively correlated to the cost of the chip. The produced R-SpiNNaker chip comprises a plurality of pins provided by the GPIO unit. After the application field is deployed, each pin of each chip is set to a designated purpose through configuration or programming, so that the chip with a limited number of pins can be suitable for more application scenes or purposes. So that some pins of the chip can be used both for capacitive ports, analog signal ports, and for driving the execution unit. Optionally, the chip provides multiple types of pins. For example, a pin with relatively stronger drive capability, a pin with relatively lower noise. Pins with stronger drive capability are suitable for driving the execution units or providing, for example, active masking signals, pins with lower noise are suitable for connecting capacitor plates or providing a capacitive channel across the chip.

Optionally, the control unit further transmits the analog or digital input signal of the GPIO to the computing unit through the digital router for filtering or function model processing, and encodes the signal provided by the control unit into an AER packet in the computing unit. Alternatively or additionally, the control unit also manages each component or each processor core of the R-SpiNNaker chip, for example: and loading codes for each processor core when the R-SpiNNaker chip is powered on, initializing each part, constructing the SNN by setting a routing table of the digital router, setting parameters of each SNN neuron and the like.

The R-SpiNNaker pursues low-cost multi-chip distributed cooperative application, does not pursue single-chip large computational power, but multi-chip cooperation can also form large computational power, and the R-SpiNNaker single-chip only needs a logic 4 core (can be a physical 4 core or a physical single-core multi-thread simulation logic four core) design idea is more suitable for the industrial application of low-cost large-area electronic skin and electronic geographic skin.

Fig. 12B shows a schematic diagram of an R-SpiNNaker chip architecture according to another embodiment of the present application.

Based on the R-SpiNNaker chip shown in FIG. 12B, the R-SpiNNaker chip shown in FIG. 12B includes local SNN units and shared SNN units. The local SNN unit and the shared SNN unit can be respectively realized by a CPU (central processing unit) core or a hardware circuit, and can also be respectively realized in a single CPU core through different threads or processes. The local SNN unit and the shared SNN unit are respectively connected with the digital router. Alternatively, the local SNN unit and the shared SNN unit are not directly connected to each other, and thus the R-spin maker chip does not adopt a symmetric Multi-Processing (SMP) structure, but provides that respective CPU cores of the local SNN unit and the shared SNN unit each have a memory and are both connected to a digital router, exchanging AER packets with the digital router. When the SNN neurons in the local SNN unit need to send the AER packet to the SNN neurons of the shared SNN unit, the AER packet needs to be sent to the digital router, and the digital router forwards the AER packet to the SNN neurons in the shared SNN unit according to the information of the routing table.

The purpose of setting the local SNN unit is two, the first is to carry out local quick decision, for example, when the R-SpiNNaker chip where the local SNN unit is located contacts local high temperature or local pressure exceeds an upper threshold, the event needs to be sensed and bottom layer decision is made; and secondly, extracting local bottom layer characteristic parameters, for example, identifying the type of the local material of the contacted or to-be-contacted external object by the R-SpiNNaker chip where the local SNN unit is located, identifying the approaching speed of the external object, the three-dimensional force vector of the local contact, whether the local contact has vibration, the amplitude and frequency of the vibration, whether the local contact has the sliding direction and speed, and the like.

According to the embodiment of the application, the received AER packet of the local SNN unit is only originated from the computing unit and/or the control unit of the chip where the AER packet is located, and the AER packet output by the local SNN unit can be forwarded to the shared SNN unit and/or the chip where the local SNN unit is located by the digital router. The multiple SNN neurons of the local SNN unit may construct one or more SNNs, the constructed SNNs may undergo modular, standardized independent learning training, and the neurons of the SNN of the local SNN unit, except for their output layers, are not visible to SNNs sharing the SNN unit or other R-SpiNNaker chips. In other words, in the neurons of the local SNN unit, the AER packets output by other SNN neurons, except for the neurons that are the output layer of the SNN, are not forwarded by the digital router to the shared SNN unit or other R-spin maker chips.

Alternatively, even if a plurality of SNN neurons included in the SNN unit are implemented by, for example, the same CPU, the transfer of AER packets between the SNN neurons within the SNN unit is relayed by the digital router for simplicity of design and programming model.

The primary purpose of sharing the SNN unit is to construct the inter-chip SNN for multi-chip (multi-CPU core) coordinated computations, similar to the spin baker system. Large scale SNNs can be distributed over multiple chips for coordinated computation. In contrast, the SNN of each shared SNN unit may have a local output layer, which aims to issue a local control instruction to the control unit based on the result of the overall network coordination calculation. The shared SNN unit may also be configured as a local SNN unit through a routing table of the digital router in case of monolithic application.

Fig. 13A shows a schematic diagram of SNN unit construction SNN according to an embodiment of the present application.

The SNN is composed of a plurality of SNN neurons interconnected. The SNN unit includes a plurality of SNN neurons used to construct the SNN. The routing table of the digital router records the connection relationship between the SNN neurons. For example, the routing table records one or more AER packets (denoted S2) to which an AER packet (denoted S1) issued by a certain SNN neuron should be forwarded (thereby indicating that in SNN, the output of SNN neuron S1 is connected to the input of SNN neuron S2, and there may be multiple neurons S2), point-to-point ports/network ports, control unit.

The SNN has a designated function, for example, recognizing the approach of a finger, detecting the material of an object, recognizing the speed/moving direction of a target, and the like. SNNs include, for example, three layers, an input layer, an intermediate layer, and an output layer. Each layer is composed of SNN neurons. SNN neurons constituting the input layer are referred to as input layer neurons, SNN neurons constituting the output layer are referred to as output layer neurons, and SNN neurons constituting the intermediate layer are referred to as intermediate layer neurons.

The input received by the SNN is a neural impulse. The time, number, etc. of occurrence of the nerve impulses represent the information to be identified by the SNN. In fig. 13A, the vertical lines between the digital router and the input layer neurons represent the neural impulses (also representing AER packets), and the position of the vertical lines in the horizontal direction represents the time of occurrence of the neural impulses, with closer to the right representing earlier times of occurrence.

In an alternative embodiment, the input layer neurons only receive AER packages provided by output layer neurons, e.g., from a compute unit or other SNNs. AER packets determined to be forwarded to input layer neurons may come from a compute unit or other output layer neurons of the SNN, but not from intermediate layer neurons, through routing rules set in the routing tables of the digital router. The intermediate layer neurons only receive the AER package from the input layer neurons of their SNNs or the intermediate layer neuron outputs of their SNNs, and the outputs of the intermediate layer neurons are only provided to the output layer neurons of their SNNs. The output layer neurons of the SNN receive only AER packets output by the intermediate layer neurons of the SNN in which they reside. AER packets output by output layer neurons of an SNN may be provided to a control unit and/or to input layer neurons of other SNNs.

The output of the SNN is a neural impulse. The time, number, etc. of occurrence of the nerve impulses are also representative of the results of the SNN process. In fig. 13A, the neural impulses output by the output layer neurons of the SNN are provided to a digital router (represented by the dashed line). The digital router also forwards the received AER packets (representing neural impulses) to the control unit and/or other input layer neurons of the SNN according to the routing table. Although fig. 13A shows 2 digital routers, for the sake of clarity, in the R-spin router chip, only a single digital router is provided, which provides AER packets to the SNN, to which AER packets output by the SNN are also provided.

In fig. 13A, the communication connection between the SNN neurons (nodes represented by circles) of the SNN and the digital router is also shown. The AER packet output by the SNN neuron is sent to the digital router firstly, and then is sent to another designated SNN neuron by the digital router. In this way, the information path between the SNN unit and the digital router is simplified. SNN cells or SNNs may include a large number of SNN neurons, and it is difficult to provide information for each SNN neuron to be specific to a digital router. And the SNN unit has an information path with the digital router, which is shared by all SNN neurons of the SNN unit to exchange AER packets with the digital router.

It is understood that the SNN neurons of the SNN unit may not be distinguished from each other, but are routing rules provided by a routing table of the digital router, describing layers (input layer, intermediate layer, output layer) to which the SNN neurons belong, and connection relationships between the SNN neurons.

Fig. 13B shows a schematic diagram of SNN construction by a SNN unit according to still another embodiment of the present application.

In the example of fig. 13B, the R-SpiNNaker chip includes a local SNN unit and a shared SNN unit, each of which is provided by a CPU core. A plurality of SNN neurons of the local SNN unit constitute the SNN. A plurality of SNN neurons sharing an SNN unit constitute the SNN. Forwarding targets of AER packets output by input layer neurons and intermediate layer neurons of the SNN in the local SNN unit are both SNN neurons of the local SNN. Only AER packets output by the output layer neurons may be forwarded out of the local SNN unit. Optionally, AER packets output by SNN neurons of the local SNN unit are not forwarded out of the R-spin maker chip to which the AER packets belong, so that the computation resources of the local SNN unit are not shared among multiple R-spin maker chips. AER packets received by input layer neurons of an SNN in a local SNN unit come from the compute unit of the R-SpiNNaker chip to which they belong, or other SNNs in the local SNN unit.

Forwarding targets of AER packets output by input layer neurons and intermediate layer neurons of the SNN in the shared SNN unit are both SNN neurons of the shared SNN. The AER packets output by only the output layer neurons may be forwarded outside the shared SNN unit, including other SNN neurons in the shared SNN unit that do not belong to the SNN, local SNN units of the R-spin maker chip to which the shared SNN unit belongs, and/or other R-spin maker chips outside the R-spin maker chip to which the shared SNN unit belongs. AER packets received by input layer neurons of an SNN in a shared SNN unit come from a local SNN unit of a chip to which the shared SNN unit belongs, other neurons of the shared SNN unit, or other R-SpiNNaker chips.

In an alternative embodiment, the shared SNN units of the multiple R-SpiNNaker chips of the R-SpiNNaker system cooperate to construct the SNN. The shared SNN unit of each of the multiple R-SpiNNaker chips provides one or more SNN neurons for the constructed SNN. The respective digital routers of these R-SpiNNaker chips collectively define the topology of the SNN neurons for the constructed SNN, and distribute AER packages for the SNN neurons. Alternatively, the shared SNN units of the respective R-SpiNNaker chips cooperate to construct the SNN, the input layer neurons, the intermediate layer neurons, and the output layer neurons of the constructed SNN may be provided by any shared SNN unit, the AER packets output by the input layer neurons, the intermediate layer neurons, and the output layer neurons may also be transmitted to any shared SNN unit that provides the neurons for the SNN, and the AER packets output by the output layer neurons may also be provided to the control unit of the R-SpiNNaker chip where any shared SNN unit that provides the neurons for the SNN is located.

Fig. 14 shows a schematic diagram of an R-SpiNNaker chip architecture according to yet another embodiment of the present application.

The R-spin maker chip shown in fig. 14 includes 4 CPU cores (1420, 1422, 1424, and 1426), a digital router, an analog signal router, a CDC, point-to-point ports, GPIO units, and optional analog signal ports.

The CPU core 1420 provides a computational unit. The calculation unit comprises a SNN neuron calculation model represented by a function f (x) and an encoder. CPU core 1420 implements a function f (x) for calculating the timing of the output neural pulse based on one or more capacitance measurements (of one or more times) provided by the CDC, the encoder encoding the pulse as an AER packet and sending it to the digital router.

The 4 CPU cores are respectively and directly connected with the digital router, or the digital router is used as a device of an on-chip bus of the chip, and each CPU core is connected with the digital router through the on-chip bus.

The CPU core 1422 provides a local SNN unit. The CPU core 1426 provides a shared SNN unit. The CPU core 1424 provides a control unit that drives external settings to perform specified actions in response to receiving AER packets or other data packets from the digital router. The external device does not, for example, belong to an integral part of the R-SpiNNaker chip, but is connected to the R-SpiNNaker chip through a GPIO.

The digital router is connected with 4 point-to-point connection ports located in the east, west, south and north directions of the R-SpiNNaker chip. The point-to-point ports are used for being connected with the point-to-point ports of other R-SpiNNaker chips and transmitting AER packets. The point-to-point ports comprise, for example, 2 wires, and the point-to-point ports communicate with each other through, for example, 2 wires. Optionally, the CPU core 1424 also provides a digital router.

The analog signal router establishes a capacitive channel between the CDC and the GPIO and/or analog signal ports. The GPIO is connected to the capacitive port, or a portion of the pins of the GPIO are configured to provide the capacitive port. The analog signal router is connected with 4 groups of analog signal ports positioned in the east, west, south and north directions of the R-SpiNNaker chip. The analog signal port is used for being connected with analog signal ports of other R-SpiNNaker chips and transmitting analog signals. Each set of analog signal ports includes, for example, a cross-chip excitation signal line port, a cross-chip mutual capacitance input signal line port, and a cross-chip synchronous clock signal line, so that one set of analog signal ports is connected with one set of analog signal ports of another chip through 3 leads.

The analog signal router may be configured or programmed. For example, a digital router forwards packets to an analog signal router to provide information for configuration or programming. Also for example, the CPU core 1424 acts as a control unit to configure or program the analog signal router.

It will be appreciated that in other embodiments, the R-SpiNNaker chip may include a greater or lesser number of CPU cores, a greater number of CDCs, a greater or lesser number of analog signal ports/point-to-point ports. Alternatively, the point-to-point interface is replaced by a network port, or the R-SpiNNaker chip includes both network and point-to-point ports.

Still optionally, the R-spin maker chip comprises a plurality of capacitive ports, each group of capacitive ports comprising 4 or 5 capacitive ports, so as to adapt the capacitive units.

Optionally, the R-SpiNNaker chip further comprises a configuration port. The configuration port is used for providing configuration information for the computing unit, the digital router, the CDC, the analog signal router, the nerve unit and/or the control unit, and optionally debugging the R-SpiNNaker chip or outputting the state information of the R-SpiNNaker chip through the configuration port.

FIG. 15 illustrates an R-SpiNNaker system according to yet another embodiment of the present application.

In the example of FIG. 15, the R-SpiNNaker system includes 4R-SpiNNaker chips (1510, 1520, 1530, and 1540). The R-SpiNNaker chip 1510 has multiple CPU cores and CDCs. And the R-SpiNNaker chips 1520, 1530, and 1540 are different from the R-SpiNNaker chip 1510. Optionally, the R-spin maker chips 1520, 1530, and 1540 include digital routers, analog signal ports, capacitive ports, and point-to-point ports for providing capacitive plates, passing analog signals, and forwarding AER packets in the R-spin maker system. The R-SpiNNaker chip 1510 is a fully functional R-SpiNNaker chip, and is capable of measuring capacitance and constructing SNN. The R-SpiNNaker chip 1510 can measure capacitance using capacitance plates connected to all capacitance ports/analog signal ports in the R-SpiNNaker system, and configure the digital router and analog signal router of each R-SpiNNaker chip of the R-SpiNNaker system to form a capacitance channel.

Optionally, the R-spin maker chips 1520, 1530, and 1540 include a processor core and provide an SNN unit (without including the CDC). The SNN units of the 4R-spin maker chips (1510, 1520, 1530, and 1540) provide SNN neurons and construct one or more SNNs in the R-spin maker system.

As an example, the capacitance port of the R-SpiNNaker chip is connected with a capacitance unit. The capacitor unit comprises, for example, 4 sector electrodes and 1 multifunctional electrode forming a circle. The R-SpiNNaker chip is connected with a capacitor unit through a group of 5 capacitor ports. In the example of fig. 15, 2 capacitor units are connected to each R-SpiNNaker chip. Each R-SpiNNaker chip also comprises 4 analog signal ports and 4 point-to-point ports, which are respectively positioned in four directions of east, west, south and north of the chip. The analog signal port and the point-to-point port on the east side of the R-SpiNNaker chip 1510 are correspondingly connected with the analog signal port and the point-to-point port on the west side of the R-SpiNNaker chip 1520. The analog signal port and the point-to-point port on the east side of the R-spin pick chip 1530 are correspondingly connected to the analog signal port and the point-to-point port on the west side of the R-spin pick chip 1540. The south analog signal port and the point-to-point port of the R-spin leak chip 1510 are correspondingly connected to the north analog signal port and the point-to-point port of the R-spin leak chip 1530. The south side analog signal port and the point-to-point port of the R-spin pick chip 1520 are correspondingly connected to the north side analog signal port and the point-to-point port of the R-spin pick chip 1540.

The digital routers of the R-SpiNNaker chips are connected through point-to-point ports and interact with data packets. The exchanged data packets include, for example, AER packets carrying pulses of SNN neurons, data packets for configuring analog signal routers, data packets for synchronizing operations of CDCs of the respective R-spin neckers chips, and the like.

FIG. 16A shows a schematic diagram of a SNN constructed in the R-SpiNNaker system according to an embodiment of the present application.

In FIG. 16A, the R-SpiNNaker system includes 2R-SpiNNaker chips (1610 and 1620). The shared SNN cells of the two chips provide SNN neurons to build SNN (impulse neural network) 1630. The input layer neurons of SNN 1630 come from the shared SNN unit of R-SpiNNaker chip 1610, the middle layer neurons of SNN 1630 come from the shared SNN unit of R-SpiNNaker chip 1620, and the output layer neurons of SNN 1630 come from the shared SNN unit of both R-SpiNNaker chips 1610 and 1620. It is to be understood that the source of SNN neurons for SNN 1630 are shown in fig. 16A for exemplary purposes, and in various embodiments, the SNN neurons of the SNN cooperatively constructed by the R-spin naker systems of the R-spin naker system may be from (shared SNN units of) any R-spin naker chip of the R-spin naker system.

The topology of the SNN neurons of SNN 1630 is defined by the routing tables of the digital routers of the R-SpiNNaker chips (1610 and 1620). One SNN neuron of SNN 1630, in order to provide an outgoing AER packet to another SNN neuron to which it is connected, needs to provide the outgoing AER packet to the digital router of the chip (e.g., 1610) to which it belongs, which forwards the AER packet to the other SNN neuron. The digital router also forwards the AER packet through a digital router of another R-spin maker chip (e.g., 1620) to provide the AER packet to SNN neurons located on another R-spin maker chip, if needed.

In the example of FIG. 16A, the local neural units of the 2R-SpiNNaker chips (1610 and 1620) do not participate in the construction of SNN 1630, so as to reserve the computational resources needed for the R-SpiNNaker chips themselves to perform sensing or other applications.

FIG. 16B shows a diagram of SNN constructed in the R-SpiNNaker system according to yet another embodiment of the present application.

In FIG. 16B, the R-SpiNNaker system includes 9R-SpiNNaker chips (1650, 1652, 1654, 1660, 1662, 1664, 1670, 1672, and 1674) arranged in 3 rows and 3 columns. These R-SpiNNaker chips constructed 6 SNNs (1651, 1653, 1655, 1661, 1663, and 1671). Each of these SNNs is an independently working and completing SNN, which in turn co-process tasks through a hierarchical structure. For example, SNN1651 is constructed by SNN neurons provided by local SNN units of R-spin maker chip 1650, and AER packets transmitted between neurons inside SNN1651 are only passed through their digital routers inside spin maker chip 1650, and are not forwarded outside spin maker chip 1650, and thus do not affect communication bandwidth between other chips of the R-spin maker system of fig. 16B. SNN1651 is used to sense specific/definite physical quantities such as appearance, moving speed, material, and the like of an object detected by a capacitance value output from the CDC of the SpiNNaker chip 1650 or a capacitance plate connected to the SpiNNaker chip 1650. Similarly, SNN1653 is built from SNN neurons provided by local SNN units of R-spin maker chip 1652, and AER packets transmitted between neurons inside SNN1653 are only passed through their digital routers inside spin maker chip 1652. SNN1655 is built from SNN neurons provided by local SNN units of R-spin maker chip 1654, and AER packets transmitted between neurons inside SNN1655 are only passed through their digital routers inside spin maker chip 1654.

The SNN1661 is constructed from SNN neurons provided by shared SNN units of the R-SpiNNaker chip 1660, and AER packets transmitted between neurons inside the SNN1661 are only passed through their digital routers inside the SpiNNaker chip 1660. The SNN1663 is constructed from SNN neurons provided by shared SNN units of both R-SpiNNaker chips 1662 and 1664, and AER packets transmitted between neurons inside the SNN1663 are passed by digital routers of both SpiNNaker chips 1662 and 1664. SNN1671 is constructed from SNN neurons provided by shared SNN units of the R-SpiNNaker chip 1670.

Alternatively, the SNN constructed by the R-SpiNNaker system may be comprised of SNN neurons provided by shared SNN units from one or more R-SpiNNaker chips.

In the embodiment of fig. 16B, SNNs (1651, 1653, 1655) are bottom SNNs, SNNs (1661 and 1663) are middle SNNs, and SNNs (1671) are upper SNNs. Each SNN can be trained independently and output a result with a definite physical meaning as input information of the next layer. In the example of fig. 16B, the middle SNN layer is the next layer with respect to the bottommost SNN layer, and the upper SNN layer is the next layer with respect to the middle SNN layer.

A plurality of SNNs with similar functions or equivalent logics are arranged at the same layer, and the physical results output by the SNNs are used as the input of the SNNs (complete independent SNNs) at higher abstraction layers according to different abstraction requirements or generalization requirements. The neural networks of each partition of each layer are trained independently and reasoned independently.

Taking the robot armored electronic skin feel as an example, the feel of each part of the right hand (e.g., palm, back of hand, and wrist) corresponds to one SNN (1651, 1653, and 1655), respectively. Each SNN outputs a distinct tactile characteristic such as touch or slide. The tactile characteristics of the back, palm and wrist of the right hand are integrated into the tactile characteristics of the entire right hand, represented by SNN 1663. The outputs of the SNNs (1651, 1653, and 1655) are provided to the SNN1663 as inputs. SNN1671 represents the tactile features of the right torso of the robot, which receives input from SNN 1663. By combining abstractions in sequence, the tactile perception of the whole robot is formed. The maximum advantage of the hierarchical computation is that the data communication bandwidth requirement of each layer and each region of the neural network is reduced, and the transmission characteristics save more data communication traffic than the original data.

Alternatively, the higher the SNN, the higher the abstraction level, and correspondingly the lower the number of required computing resources (e.g., R-SpiNNaker chips).

Still alternatively or additionally, the transfer of AER packets between layers SNN is unidirectional, towards the direction of abstraction level promotion. For example, AER packages representing the output of the underlying SNN1651 are provided to the middle SNN1663, whereas AER packages output by the middle SNN1663 are not provided to the underlying SNN.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (30)

1. A system comprising a plurality of chips, wherein one or more of said plurality of chips comprises a digital router, an analog signal router, and one or more network ports or point-to-point ports;

a network port or a point-to-point port of a first chip of the plurality of chips is coupled to a network port or a point-to-point port of a second chip of the plurality of chips;

the digital router of the first chip receives a data packet through a network port or a point-to-point port of the chip where the digital router is located, wherein the data packet carries configuration information of the analog signal router;

the analog signal router comprises an analog routing controller and an analog switch matrix, wherein the analog routing controller is coupled with a plurality of switches of the analog switch matrix and controls the plurality of switches of the analog switch matrix to be opened or closed.

2. The system of claim 1, wherein

And the digital router of the first chip sends a data packet carrying configuration information of the analog signal router to one or more of the plurality of chips through a network port or a point-to-point port of the digital router.

3. The system of claim 2, wherein

And the digital router of the first chip forwards the received data packet carrying the configuration information of the analog signal router to the analog signal router of the chip where the digital router is located, so as to set one or more switches of the analog signal router of the first chip according to the data of the received data packet carrying the configuration information of the analog signal router.

4. System according to one of claims 1-3, wherein

The first one of the plurality of chips is further coupled to the network ports or point-to-point ports of the other ones of the plurality of chips through other network ports or point-to-point ports.

5. System according to one of claims 1 to 4, wherein

The data packets carrying configuration information for the analog signal router include data corresponding to the open or closed state of one or more switches of the analog signal router.

6. System according to one of claims 1 to 5, wherein

One or more of the plurality of chips further comprises a neural unit coupled to the digital router;

the neural unit comprises a plurality of neurons;

the digital router forwards received packets of a first type indicating a trigger pulse to one or more neurons of a neuron to one or more neurons of the neuron or outside the chip.

7. The system of claim 6, wherein

And the neurons of the neural unit generate a first type of data packet and send the first type of data packet to the digital router.

8. A system according to claim 6 or 7, wherein

The plurality of neurons of the neural unit form a spiking neural network.

9. System according to one of claims 6 to 8, wherein

The nerve unit comprises a first nerve unit and a second nerve unit;

the first neural unit comprises a plurality of neurons;

the second neural unit comprises a plurality of neurons;

the first and second neural units are each coupled to a digital router of a chip to which they belong;

one or more neurons of the first neural unit form a first neural meridian;

one or more neurons of the second neural unit form a second neural network.

10. The system of claim 9, wherein

One or more neurons of a second neural unit of one or more of the plurality of chips collectively form a third neural network.

11. The system of claim 9, wherein

Routing a first class of data packets sent by the neurons of the first neuron to one or more neurons of the first neuron and/or one or more neurons of the second neuron by a digital router of a chip to which the neurons belong;

the digital router of the chip to which the nerve unit belongs routes the first class data packets sent out by the neurons of the second nerve unit to one or more neurons of the second nerve unit and/or to the outside of the chip, and not to any neuron of the first nerve unit.

12. The system of one of claims 6-11,

the first type of packet includes an identification of the chip that generated the packet and/or an identification of the neuron.

13. The system of one of claims 6-12,

the generated first type of data packet of the first neuron is provided to a digital router;

and the digital router forwards the first class data packets to a second neuron according to the address and the routing table carried in the received first class data packets, wherein the first neuron and the second neuron have a connection relation in the pulse neural network.

14. System according to one of claims 9-13, wherein

The neurons of the first neural unit construct one or more neural networks;

the neurons of the second neural unit construct one or more neural networks;

the routing table of the digital router defines the topology of the constructed neural network.

15. System according to one of claims 6-14, wherein

The neural unit is provided by a processor core;

and the processor core providing the neural unit is coupled with the digital router of the chip to receive the first type of data packets provided by the digital router and/or send the first type of data packets to the digital router.

16. The system of any of claims 1-15, wherein

One or more of the plurality of chips further comprises a capacitive-to-digital converter;

the capacitance-to-digital converter is coupled with the analog signal router of the chip where the capacitance-to-digital converter is located, and the capacitance is measured through the analog signal router of the chip where the capacitance-to-digital converter is located.

17. The system of claim 16, wherein

The analog signal routers of one or more of the plurality of chips cooperate to form a capacitive channel through which a capacitance-to-digital converter measures capacitance.

18. The system of one of claims 1 to 17, wherein

One or more of the plurality of chips further comprises one or more analog signal ports; the analog signal port is used for coupling a capacitor plate positioned outside the chip or an analog signal port of other chips.

19. The system of claim 18, wherein

One or more of the plurality of chips further comprises one or more capacitive ports;

the capacitive port is only used to couple the capacitive plate located outside the chip.

20. The system of claim 18 or 19, wherein

The analog signal router couples at least one analog signal port and/or at least one capacitance port of its own chip with the capacitance-to-digital converter of its own chip, so that the capacitance-to-digital converter of its own chip measures capacitance through at least one analog signal port and/or at least one capacitance port of one or more chips of the system.

21. The system of claim 20, wherein

The analog signal router comprises a connection wire group and an analog switch matrix;

the connecting line group comprises at least a first connecting line and/or a second connecting line;

the analog switch matrix couples the connection line set to the capacitance ports of its own chip, wherein at any instant, the analog switch matrix couples a capacitance port to at most only one connection line of the connection line set, and the analog switch matrix couples one connection line of the connection line set to zero, one, or more capacitance ports;

the analog switch matrix also couples the set of connection lines to the capacitance-to-digital converter.

22. The system of claim 21, wherein

The analog switch matrix couples the first connecting line to a first capacitance port of a chip to which the analog switch matrix belongs, couples the second connecting line to a second capacitance port of the chip to which the analog switch matrix belongs, and couples the first connecting line and the second connecting line to a capacitance-to-digital converter of the chip to which the analog switch matrix belongs, so that the capacitance-to-digital converter of the chip to which the analog switch matrix belongs measures mutual capacitance formed by a capacitance plate coupled to the first capacitance port and a capacitance plate coupled to the second capacitance port.

23. The system of claim 21 or 22, wherein

The analog signal router of one or more of the plurality of chips further comprises a cross-chip connection set;

the cross-chip connecting line group comprises at least a first cross-chip connecting line; the first cross-chip connecting line is coupled with the first connecting line of the analog signal router to which the first cross-chip connecting line belongs; the analog switch matrix of the analog signal router to which the cross-chip connection wire group belongs couples the cross-chip connection wire group to the analog signal port of the chip to which the cross-chip connection wire group belongs, wherein at any moment, the analog switch matrix of the analog signal router to which the cross-chip connection wire group belongs couples one analog signal port of the chip to which the cross-chip connection wire group belongs to at most only one connection wire of the cross-chip connection wire group, and the analog switch matrix of the analog signal router to which the cross-chip connection wire group belongs couples one connection wire of the cross-chip connection wire group to zero, one or more analog signal ports of the chip to which the cross-chip connection wire group belongs.

24. The system of claim 23, wherein

The cross-chip connecting line group comprises a first cross-chip connecting line and a second cross-chip connecting line;

the analog switch matrix of the analog signal router to which the cross-chip connecting line group belongs respectively couples the first cross-chip connecting line and the second cross-chip connecting line of the chip to the analog signal port of the chip to which the cross-chip connecting line group belongs;

wherein at any one time, the analog switch matrix couples one analog signal port to at most only one connection line of the cross-chip connection line set of its affiliated analog signal router, and the analog switch matrix couples one connection line of the cross-chip connection line set of its affiliated analog signal router to zero, one, or more analog signal ports of its affiliated chip.

25. The system of claim 24, wherein

The analog signal ports of one or more of the plurality of chips comprise one or more analog signal ports for a first cross-chip connection line of the chip to which the chip belongs and one or more analog signal ports for a second cross-chip connection line of the chip to which the chip belongs;

the analog switch matrix is configured to couple at any time one analog signal port of its own chip for a first cross-chip connection line to at most only a first cross-chip connection line of its own chip, one analog signal port of its own chip for a second cross-chip connection line to at most only a second cross-chip connection line of its own chip, couple the first cross-chip connection line of its own chip to zero, one or more analog signal ports for the first cross-chip connection line, and couple the second cross-chip connection line of its own chip to zero, one or more analog signal ports for the second cross-chip connection line.

26. The system according to one of claims 23-25, wherein

The cross-chip connection line group also comprises a cross-chip synchronous clock signal line;

and the cross-chip synchronous clock signal line is coupled with the analog signal port of the chip to which the cross-chip synchronous clock signal line belongs.

27. The system of any of claims 1-26, wherein

One or more of the plurality of chips further comprises a control unit;

the control unit is coupled with the digital router of the chip to which the control unit belongs;

the control unit applies a driving signal to a device outside the chip to which the control unit belongs through a General Purpose Input Output (GPIO) unit.

28. The system of one of claims 1 to 27, wherein

The first analog signal port of the first chip is coupled with the second analog signal port of the second chip;

the digital router of the second chip receives a data packet carrying configuration information of the analog signal router through a network port or a point-to-point port of the digital router;

the first chip sets an analog switch matrix of the first chip according to data of a data packet carrying configuration information of an analog signal router, and couples a first cross-chip connecting line (IAE) or a second cross-chip connecting line (IAC) of the first chip with a first analog signal port of the first chip;

the second chip sets an analog switch matrix of the second chip according to data of a data packet carrying configuration information of an analog signal router, and couples a first cross-chip connecting line (IAE) or a second cross-chip connecting line (IAC) of the second chip with a second analog signal port of the second chip;

and correspondingly coupling the first cross-chip connecting line (IAE) or the second cross-chip connecting line (IAC) of the first chip with the first cross-chip connecting line (IAE) or the second cross-chip connecting line (IAC) of the second chip.

29. The system of any of claims 1-28, wherein

One or more chips of a first plurality of the plurality of chips are each coupled to other one or more chips of the first plurality of chips through their analog signal ports; the digital router of each of a first plurality of chips of the plurality of chips receives a data packet carrying configuration information of an analog signal router, and an analog switch matrix of the digital router is set according to the received data packet carrying the configuration information of the analog signal router to couple a first cross-chip connecting line (IAE) or a second cross-chip connecting line (IAC) of the digital router with an analog signal port of a chip to which the digital router belongs, so that the first cross-chip connecting line (IAE) or the second cross-chip connecting line (IAC) of each of the first plurality of chips is correspondingly coupled with the first cross-chip connecting line (IAE) or the second cross-chip connecting line (IAC) of the other one or more chips of the first plurality of chips.

30. The system of claim 29, wherein

The simulation routing controller comprises a register set of a simulation routing controller, a sequence state controller and a selector;

the register bank comprises a plurality of registers, wherein a value of each bit of each register of the plurality of registers indicates an opening or closing of one of the switches of the analog switch matrix;

the output of the sequence state controller controls the selector to select one of the plurality of registers as the output of the analog routing controller;

in response to receiving a data packet carrying configuration information for the analog signal router, a register set and a sequence state controller of the analog routing controller are set according to data of the data packet carrying configuration information for the analog signal router.

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