CN113767571B - FET control device and method - Google Patents

FET control device and method Download PDF

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Publication number
CN113767571B
CN113767571B CN202080032429.2A CN202080032429A CN113767571B CN 113767571 B CN113767571 B CN 113767571B CN 202080032429 A CN202080032429 A CN 202080032429A CN 113767571 B CN113767571 B CN 113767571B
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China
Prior art keywords
voltage
capacitor
fet
switch
source terminal
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CN202080032429.2A
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CN113767571A (en
Inventor
安洋洙
李相镇
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LG Energy Solution Ltd
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LG Energy Solution Ltd
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)
  • Electronic Switches (AREA)

Abstract

The present disclosure relates to a FET control apparatus and method, and aims to provide a FET control apparatus and method for adaptively adjusting a voltage applied to a FET to correspond to a voltage of a source terminal of the FET to accurately control an operation state of the FET. According to an aspect of the present invention, the voltage applied to the gate terminal may be adaptively controlled according to the voltage of the source terminal using a capacitor. Therefore, even when the source terminal is not connected to the ground but to an external load, there is an advantage in that the operation state of the FET can be smoothly and accurately controlled. Furthermore, according to an aspect of the present invention, there is an advantage in that a voltage in a specific range can be applied to the gate terminal of the FET.

Description

FET control device and method
Technical Field
The present application claims priority from korean patent application No.10-2019-0153701 filed in korea at 11.26 of 2019, the disclosure of which is incorporated herein by reference.
The present disclosure relates to a FET control apparatus and method, and more particularly, to a FET control apparatus and method for accurately controlling an operation state of a FET.
Background
Recently, demand for portable electronic products such as notebook computers, video cameras, and portable telephones has sharply increased, and electric vehicles, energy storage batteries, robots, satellites, and the like have been seriously developed. Therefore, high-performance batteries allowing repeated charge and discharge are being actively studied.
Currently commercially available batteries include nickel-cadmium batteries, nickel-hydrogen batteries, nickel-zinc batteries, lithium batteries, and the like. Among them, lithium batteries are attracting attention because they have little memory effect and have very low self-discharge rate and high energy density compared to nickel-based batteries.
Meanwhile, if such a battery is provided to the battery pack, a main relay through which a current output from the battery or a current flowing into the battery flows may be provided on a main charge/discharge path of the battery pack.
For example, if an N-channel MOSFET including a drain terminal, a source terminal, and a gate terminal is applied to the main relay, the drain terminal and the source terminal may be electrically connected only when a voltage difference between the source terminal and the gate terminal is equal to or greater than a certain level. In this case, if the source terminal and the gate terminal are connected to the common ground, the operation state of the FET can be controlled by adjusting the voltage applied to the gate terminal. However, if the source terminal and the gate terminal are not connected to the common ground, there is a problem in that the operation state of the FET cannot be controlled regardless of the voltage applied to the source terminal. That is, in order to accurately control the operation state of the FET, it is necessary to adaptively adjust the voltage applied to the gate terminal to correspond to the voltage applied to the source terminal.
Disclosure of Invention
Technical problem
The present disclosure is designed to solve the problems of the prior art, and therefore the present disclosure is directed to providing an FET control apparatus and method for accurately controlling an operation state of an FET by adaptively adjusting a voltage applied to the FET to correspond to a voltage of a source terminal of the FET.
These and other objects and advantages of the present disclosure will be understood from the following detailed description and will become more fully apparent from the exemplary embodiments of the present disclosure. In addition, it will be readily understood that the objects and advantages of the present disclosure may be realized by the means and combinations thereof as indicated in the appended claims.
Technical proposal
In one aspect of the present disclosure, there is provided an FET control apparatus for controlling an operation state of an FET including a drain terminal, a gate terminal, and a source terminal, the FET control apparatus including: a capacitor configured to be connected in parallel with the FET between the gate terminal and the source terminal through a discharge line; a voltage source configured to be electrically connected to the capacitor through a charging wire and configured to charge the capacitor when the charging wire is electrically connected; a measurement unit configured to measure a voltage of the source terminal and a voltage of the capacitor; and a control unit configured to receive the voltage of the source terminal and the voltage of the capacitor from the measurement unit, set a target voltage based on the voltage of the source terminal, charge the capacitor by the voltage source through the electrically connected charging line until the voltage of the capacitor is equal to or higher than the target voltage, and control an operation state of the FET through the electrically connected discharging line after the capacitor is fully charged.
The control unit may be configured to set the target voltage by adding a preset threshold voltage and a voltage of the source terminal.
The threshold voltage may be preset as a voltage difference between the gate terminal and the source terminal, which converts the operation state of the FET into an on state.
The discharge wire may be configured to include: a first cell line having a first switch configured to connect the gate terminal and one end of the capacitor; and a second cell line having a second switch configured to connect the source terminal and the other end of the capacitor.
The charging wire may include: a third cell line having a third switch configured to connect one end of the capacitor and the positive terminal of the voltage source; and a fourth cell line having a fourth switch configured to connect the other end of the capacitor and the negative terminal of the voltage source.
One end of the capacitor may be configured to be connected between the first switch and the third switch.
The other end of the capacitor may be configured to be connected between the second switch and the fourth switch.
The control unit may be configured to simultaneously control the operation states of the first switch and the second switch and simultaneously control the operation states of the third switch and the fourth switch.
The control unit may be configured to electrically connect any one of the charging wire and the discharging wire and electrically disconnect the other thereof every predetermined control period after the capacitor is fully charged.
The predetermined control period may be a period set to maintain the voltage of the capacitor equal to or higher than the target voltage.
When the voltage of the source terminal is changed, the control unit may be configured to reset the target voltage to correspond to the changed voltage of the source terminal and change the predetermined control period based on the reset target voltage.
The measurement unit may be configured to further measure the voltage of the drain terminal.
The control unit may be configured to receive the voltage of the drain terminal from the measurement unit and diagnose whether the FET has a fault by comparing the voltage of the drain terminal and the voltage of the source terminal based on the operation state of the FET.
In another aspect of the present disclosure, there is also provided a battery pack including the FET control device according to one aspect of the present disclosure.
In still another aspect of the present disclosure, there is also provided an FET control method for controlling an operation state of an FET including a drain terminal, a gate terminal, and a source terminal, the FET control method including: a voltage measurement step of measuring a voltage of the source terminal and a voltage of a capacitor connected in parallel with the FET; a target voltage setting step of setting a target voltage based on the voltage of the source terminal measured in the voltage measuring step; a capacitor charging step of charging the capacitor such that a voltage of the capacitor becomes equal to or higher than a target voltage; and an FET operation state control step of controlling an operation state of the FET by using the capacitor fully charged in the capacitor charging step.
Advantageous effects
According to one aspect of the present disclosure, a capacitor may be used to adaptively control a voltage applied to a gate terminal according to a voltage of a source terminal. Therefore, even when the source terminal is not connected to the ground but is connected to an external load, there is an advantage in that the operation state of the FET can be smoothly and accurately controlled.
In addition, according to one aspect of the present disclosure, there is an advantage in that a voltage in a specific range can be applied to the gate terminal of the FET.
The effects of the present disclosure are not limited to the above-described effects, and other effects not mentioned herein will be clearly understood by those skilled in the art from the appended claims.
Drawings
The accompanying drawings illustrate preferred embodiments of the present disclosure and, together with the foregoing disclosure, serve to provide a further understanding of the technical features of the present disclosure, and therefore, the present disclosure is not to be construed as limited to the accompanying drawings.
Fig. 1 is a diagram schematically illustrating an FET control apparatus according to an embodiment of the present disclosure.
Fig. 2 is a diagram exemplarily showing a configuration of a battery pack including the FET control apparatus according to the embodiment of the present disclosure.
Fig. 3 is a diagram showing an exemplary configuration when a capacitor is charged in a battery pack including an FET control device according to an embodiment of the present disclosure.
Fig. 4 is a diagram showing an exemplary configuration when a capacitor is discharged in a battery pack including an FET control device according to an embodiment of the present disclosure.
Fig. 5 is a diagram showing an example of changing the voltage of a capacitor in the FET control apparatus according to the embodiment of the present disclosure.
Fig. 6 is a diagram showing another example of changing the voltage of a capacitor in the FET control apparatus according to the embodiment of the present disclosure.
Fig. 7 is a diagram schematically illustrating an FET control apparatus according to another embodiment of the present disclosure.
Detailed Description
It should be understood that the terms used in the specification and the appended claims should not be construed as limited to general and dictionary meanings, but interpreted based on the meanings and concepts corresponding to technical aspects of the present disclosure on the basis of the principle that the inventors are allowed to define terms appropriately for the best explanation.
Accordingly, the description set forth herein is merely a preferred example for the purpose of illustration only and is not intended to limit the scope of the disclosure, so it should be understood that other equivalents and modifications could be made thereto without departing from the scope of the disclosure.
Additionally, in describing the present disclosure, when a detailed description of related known elements or functions is considered to obscure the key subject matter of the present disclosure, the detailed description is omitted herein.
Terms including ordinal numbers such as "first," "second," and the like may be used to distinguish one element from another element among the various elements, but are not intended to limit the elements by terms.
Throughout the specification, when a portion is referred to as "comprising" or "including" any element, unless specifically stated otherwise, it is meant that the portion may also include other elements without excluding others.
Furthermore, the term "control unit" described in the specification means a unit that processes at least one function or operation, and may be implemented by hardware, software, or a combination of hardware and software.
In addition, throughout the specification, when a portion is referred to as being "connected" to another portion, it is not limited to the case where they are "directly connected" but also includes the case where they are "indirectly connected" with another element interposed therebetween.
Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a diagram schematically illustrating an FET control apparatus 100 according to an embodiment of the present disclosure. Fig. 2 is a diagram exemplarily showing a configuration of the battery pack 1 including the FET control apparatus 100 according to the embodiment of the present disclosure.
Here, the FET 20 is a field effect transistor, and referring to fig. 2, the FET 20 may include a drain terminal D, a gate terminal G, and a source terminal S.
Preferably, the FET 20 may employ a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Preferably, FET 20 may be an N-channel MOSFET. Hereinafter, it is assumed that the FET 20 is an N-channel MOSFET.
Referring to fig. 1, an FET control apparatus 100 according to an embodiment of the present disclosure may include a capacitor 110, a voltage source 120, a measurement unit 130, and a control unit 140.
The capacitor 110 may be configured to be connected in parallel with the FET 20 between the gate terminal G and the source terminal S through a discharge line. Here, the discharge line refers to a line connecting one end C1 of the capacitor 110 and the gate terminal G of the FET 20, and a line connecting the other end C2 of the capacitor 110 and the source terminal S of the FET 20. That is, the discharge line indicates a line through which the current stored in the capacitor 110 is output toward the FET 20 when the capacitor 110 is discharged.
Referring to fig. 2, the battery pack 1 may include a battery cell 10, a FET 20, and a FET control device 100. The FET 20 may be connected in series between the positive terminal p+ of the battery pack 1 and the positive terminal of the battery cell 10.
Specifically, the drain terminal D of the FET 20 may be directly connected to the positive terminal of the battery cell 10, and the source terminal S of the FET 20 may be directly connected to the positive terminal p+ of the battery pack 1. In addition, one end C1 of the capacitor 110 may be connected to the gate terminal G of the FET 20, and the other end C2 of the capacitor 110 may be connected to the source terminal S of the FET 20. That is, as shown in fig. 2, the capacitor 110 may be electrically connected in parallel with the FET 20 between the gate terminal G and the source terminal S of the FET 20. Accordingly, the capacitor 110 and the gate terminal G and the source terminal S of the FET 20 may form a closed loop.
Meanwhile, in the battery pack 1 shown in fig. 2, the battery cell 10 refers to one independent cell that includes a negative terminal and a positive terminal and that may be physically separated. For example, one pouch-type lithium polymer cell may be considered to be the battery cell 10. In addition, unlike fig. 2, the battery pack 1 may include one or more battery cells 10 connected in series and/or parallel. That is, the battery pack 1 may include a battery module having at least one battery cell 10.
The voltage source 120 may be configured to be electrically connected to the capacitor 110 through a charging wire. Here, the charging line refers to a line connecting one end C1 of the capacitor 110 to the positive terminal of the voltage source 120 and a line connecting the other end C2 of the capacitor 110 to the negative terminal of the voltage source 120. That is, the charging line refers to a line that receives current from the voltage source 120 when the capacitor 110 is charged.
For example, the voltage source 120 is a voltage source capable of outputting 12[ V ] DC current, and may be a voltage source independent of the battery cells 10 included in the battery pack 1.
Referring to fig. 2, a positive terminal of the voltage source 120 may be connected to one end C1 of the capacitor 110, and a negative terminal of the voltage source 120 may be connected to the other end C2 of the capacitor 110. The capacitor 110 and the voltage source 120 may form a closed loop.
In addition, the voltage source 120 may be configured to charge the capacitor 110 when the charging line is electrically connected.
For example, in the embodiment of fig. 2, if the operation states of the third switch SW3 and the fourth switch SW4 are controlled to be on states, the capacitor 110 may be charged by the voltage source 120. Specifically, if the operation states of the third switch SW3 and the fourth switch SW4 are controlled to be on states, a current output from the voltage source 120 may flow through a closed loop formed by the third switch SW3, the capacitor 110, the fourth switch SW4 and the voltage source 120. Accordingly, if the charging wire is electrically connected, the capacitor 110 may be charged.
The measurement unit 130 may be configured to measure a voltage (Vs) of the source terminal S and a voltage of the capacitor 110.
For example, referring to fig. 2, the measurement unit 130 may be connected to the second, third, and fourth sensing lines SL2, SL3, and SL4. The measurement unit 130 may measure a voltage (Vs) of the source terminal S of the FET 20 through the second sensing line SL 2. In addition, the measurement unit 130 may measure the voltage of the capacitor 110 through the third sensing line SL3 and the fourth sensing line SL4. At this time, the measurement unit 130 may measure the voltage of one end C1 of the capacitor 110 through the third sensing line SL3, and the voltage of the other end C2 of the capacitor 110 through the fourth sensing line SL4. In addition, the measurement unit 130 may measure the voltage of the capacitor 110 by calculating a difference between the measured voltages at both ends of the capacitor 110.
The control unit 140 may be configured to receive the voltage (Vs) of the source terminal S and the voltage of the capacitor 110 from the measurement unit 130.
The control unit 140 and the measurement unit 130 may be connected to each other to transmit and receive signals.
For example, referring to fig. 2, the control unit 140 and the measurement unit 130 are connected to each other through a wire line so that signals can be transmitted and received from each other.
As another example, unlike fig. 2, the control unit 140 and the measurement unit 130 may be connected to each other through wireless communication so that signals may be transmitted and received from each other.
The measurement unit 130 may convert the measured voltage (Vs) of the source terminal S and the voltage of the capacitor 110 into digital signals. In addition, the measurement unit 130 may output the converted digital signal to a line connected to the control unit 140. The control unit 140 may receive the digital signal from the measurement unit 130 and obtain the voltage (Vs) of the source terminal S and the voltage of the capacitor 110 measured by the measurement unit 130 by reading the received digital signal.
The control unit 140 may be configured to set a target voltage (Vt) based on the voltage (Vs) of the source terminal S.
In the case of the FET 20, current can flow from the drain terminal D to the source terminal S only when the voltage applied to the gate terminal G has a predetermined magnitude or higher than the voltage applied to the source terminal S. That is, in the FET 20, only when the gate voltage (Vgs) is higher than the preset threshold voltage (Vth), the current can flow from the drain terminal D to the source terminal S. Here, the gate voltage (Vgs) is a voltage value obtained by subtracting the voltage (Vs) of the source terminal S from the voltage (Vg) of the gate terminal G. In addition, here, the threshold voltage (Vth) is a voltage value set in advance so that the operation state of the FET 20 becomes the on state. That is, the threshold voltage (Vth) may be set differently according to the specification of the FET 20. Considering such characteristics of the FET 20, the target voltage (Vt) may be a minimum required voltage to be applied to the gate terminal G such that the drain terminal D and the source terminal S of the FET 20 are electrically connected.
The control unit 140 may set a target voltage (Vt) to be applied to the gate terminal G of the FET 20 based on the voltage (Vs) of the source terminal S received from the measurement unit 130.
For example, it is assumed that the threshold voltage (Vth) required for electrically connecting the drain terminal D and the source terminal S of the FET 20 is 3[V ] and the measurement voltage (Vs) of the source terminal S is 1[V ]. If 3[V voltage is applied to the gate terminal G according to the preset threshold voltage (Vth) 3[V ], since the gate voltage (Vgs), which is a voltage difference between the voltage (Vg) of the gate terminal G and the voltage (Vs) of the source terminal S, is 2[V ], the operation state of the FET 20 may not be converted into the on state. This is the case where the source terminal S is not connected to ground, and for example, in the embodiment of fig. 2, this may be the case where a load of voltage 1[V is connected to the battery pack 1. Accordingly, the control unit 140 may set the target voltage (Vt) to be applied to the gate terminal G to 4[V by considering not only the case where the source terminal S is connected to the ground but also the case where another load is connected, for example, the case where the voltage (Vs) of the source terminal S is not 0[ v ]. That is, the control unit 140 may be configured to set the target voltage (Vt) by adding a preset threshold voltage (Vth) and the voltage (Vs) of the source terminal S.
The control unit 140 may be configured to charge the capacitor 110 through the voltage source 120 by electrically connecting the charging line until the voltage of the capacitor 110 becomes equal to or higher than the target voltage (Vt).
Referring to fig. 2, the voltage source 120 may be electrically connected to the capacitor 110 through a charging line and may be configured to charge the capacitor 110 when the charging line is electrically connected. Accordingly, the control unit 140 may electrically connect the charging line until the voltage of the capacitor 110 becomes equal to or higher than the set target voltage (Vt).
For example, as in the previous embodiment, it is assumed that the threshold voltage (Vth) is 3[V, the voltage (Vs) of the source terminal S is 1[V, and the set target voltage (Vt) is 4[V. The control unit 140 may be electrically connected to the charging line such that the capacitor 110 is charged by the voltage source 120. In addition, the control unit 140 may continuously receive the voltage of the capacitor 110 from the measurement unit 130 to determine whether the voltage of the capacitor 110 becomes equal to or higher than 4[V.
The control unit 140 may be configured to control the operation state of the FET 20 by electrically connecting the discharge line after the capacitor 110 is fully charged.
Preferably, the control unit 140 may electrically connect the discharge line after blocking the connection of the charge line. In this case, as the current stored in the capacitor 110 flows through the discharge line, the voltage of the capacitor 110 may be applied to the gate terminal G of the FET 20. Since the voltage of the capacitor 110 is equal to or higher than the target voltage (Vt), the gate voltage (Vgs) may be equal to or higher than the preset threshold voltage (Vth). Accordingly, the operation state of the FET 20 is converted to the on state so that the current output from the battery cell 10 can flow from the drain terminal D to the source terminal S.
For example, in the embodiment of fig. 2, it is assumed that a load is connected to the positive terminal p+ and the negative terminal P-of the battery pack 1. If the control unit 140 is electrically connected to the discharge line, the operation state of the FET 20 is converted into an on state by the capacitor 110 being charged to be equal to or higher than the target voltage (Vt), and the current output from the battery cell 10 may be applied to the load through the FET 20.
The FET control apparatus 100 according to the embodiment of the present disclosure may control the voltage applied to the gate terminal G according to the voltage (Vs) of the source terminal S by using the capacitor 110. That is, the FET control device 100 may set the target voltage (Vt) to be applied to the gate terminal G in consideration of the voltage (Vs) of the source terminal S. Therefore, even if the source terminal S is not connected to the ground but to an external load, there is an advantage in that the operation state of the FET 20 can be smoothly and accurately controlled.
Meanwhile, the control unit 140 included in the FET control apparatus 100 may optionally include a processor, an Application Specific Integrated Circuit (ASIC), another chipset, a logic circuit, a register, a communication modem, a data processing device, and the like, which are known in the art for executing various control logics disclosed below. In addition, when the control logic is implemented in software, the control unit 140 may be implemented as a set of program modules. At this time, the program modules may be stored in the memory and executed by the control unit 140. The memory may be provided inside or outside the control unit 140 and may be connected to the control unit 140 by various known means.
Hereinafter, an exemplary configuration of the FET control apparatus 100 according to the embodiment of the present disclosure will be described in more detail.
The discharge wire may be configured to include: a first cell line having a first switch SW1 configured to connect the gate terminal G and one end C1 of the capacitor 110; and a second cell line having a second switch SW2 configured to connect the source terminal S and the other end C2 of the capacitor 110.
Specifically, the discharge wire may be constituted by a first cell wire and a second cell wire. A first switch SW1 for making or breaking the connection between the gate terminal G of the FET20 and the one end C1 of the capacitor 110 may be arranged on the first cell line. In addition, a second switch SW2 for turning on or off the connection between the source terminal S of the FET20 and the other end C2 of the capacitor 110 may be arranged on the second cell line.
For example, in the embodiment of fig. 2, the first cell line may be a line between the gate terminal G and one end C1 of the capacitor 110. A first switch SW1 connected in series with the gate terminal G and one end C1 of the capacitor 110 may be arranged on the first cell line. In addition, the second cell line may be a line between the source terminal S and the other end C2 of the capacitor 110. A second switch SW2 connected in series with the source terminal S and the other end C2 of the capacitor 110 may be arranged on the second cell line.
In addition, the operation states of the first switch SW1 and the second switch SW2 may be controlled by the control unit 140.
For example, in the embodiment of fig. 2, the control unit 140 may be connected to the first switch SW1 and the second switch SW2 through the first control line CL 1. In addition, the control unit 140 may control the operation states of the first switch SW1 and the second switch SW2 by outputting an operation state control signal to the first control line CL 1. Here, the operation state control signal may include an on control signal for converting the operation states of the first switch SW1 and the second switch SW2 into an on state and an off control signal for converting them into an off state.
The charging wire may be configured to include: a third cell line having a third switch SW3 configured to connect one end C1 of the capacitor 110 and the positive terminal of the voltage source 120; and a fourth cell line having a fourth switch SW4 configured to connect the other end C2 of the capacitor 110 and the negative terminal of the voltage source 120.
Specifically, the charging line may be constituted by a third cell line and a fourth cell line. A third switch SW3 for making or breaking a connection between one end of the voltage source 120 and one end C1 of the capacitor 110 may be arranged on the third cell line. In addition, a fourth switch SW4 for making or breaking the connection between the other end of the voltage source 120 and the other end C2 of the capacitor 110 may be arranged on the fourth cell line. Here, one end of the voltage source 120 may be a positive terminal of the voltage source 120, and the other end of the voltage source 120 may be a negative terminal of the voltage source 120.
For example, in the embodiment of fig. 2, the third cell line may be a line between one end of the voltage source 120 and one end C1 of the capacitor 110. A third switch SW3 connected in series with one end of the voltage source 120 and one end C1 of the capacitor 110 may be arranged on the third cell line. In addition, the fourth cell line may be a line between the other end of the voltage source 120 and the other end C2 of the capacitor 110. A fourth switch SW4 connected in series with the other end of the voltage source 120 and the other end C2 of the capacitor 110 may be arranged on the fourth cell line.
In addition, the operation states of the third switch SW3 and the fourth switch SW4 may be controlled by the control unit 140.
For example, in the embodiment of fig. 2, the control unit 140 may be connected to the third switch SW3 and the fourth switch SW4 through the second control line CL 2. In addition, the control unit 140 may control the operation states of the third switch SW3 and the fourth switch SW4 by outputting an operation state control signal to the second control line CL 2. Here, the operation state control signal may include an on control signal for converting the operation states of the third switch SW3 and the fourth switch SW4 into an on state and an off control signal for converting them into an off state.
Preferably, one end C1 of the capacitor 110 may be configured to be connected between the first switch SW1 and the third switch SW 3. In addition, the other end C2 of the capacitor 110 may be configured to be connected between the second switch SW2 and the fourth switch SW 4.
For example, if the operation states of the first switch SW1 and the second switch SW2 are on states and the operation states of the third switch SW3 and the fourth switch SW4 are off states, the capacitor 110 may be discharged. That is, the current stored in the capacitor 110 may be output toward the FET 20. More specifically, the current stored in the capacitor 110 may be output toward the gate terminal G of the FET 20.
As another example, if the operating states of the third switch SW3 and the fourth switch SW4 are on states and the operating states of the first switch SW1 and the second switch SW2 are off states, the capacitor 110 may be charged by the voltage source 120. That is, the current output from the voltage source 120 may be applied to the capacitor 110.
The control unit 140 may be configured to simultaneously control the operation states of the first switch SW1 and the second switch SW2 and simultaneously control the operation states of the third switch SW3 and the fourth switch SW 4.
That is, the control unit 140 may block the connection between the discharge line and the capacitor 110 when the charge line is electrically connected, and may block the connection between the charge line and the capacitor 110 when the discharge line is electrically connected.
An example in which the control unit 140 controls the operation states of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 will be described with reference to fig. 3 and 4.
Fig. 3 is a diagram showing an exemplary configuration when the capacitor 110 is charged in the battery pack 1 including the FET control apparatus 100 according to the embodiment of the present disclosure. Fig. 4 is a diagram showing an exemplary configuration when the capacitor 110 is discharged in the battery pack 1 including the FET control apparatus 100 according to the embodiment of the present disclosure.
Referring to fig. 3, when the capacitor 110 is charged, the control unit 140 may control the operation states of the third switch SW3 and the fourth switch SW4 to be on states. Specifically, the control unit 140 may output an on control signal to the second control line CL2 and an off control signal to the first control line CL 1. In this case, the operation states of the first switch SW1 and the second switch SW2 may be off states, and the operation states of the third switch SW3 and the fourth switch SW4 may be on states. The voltage source 120, the third switch SW3, the capacitor 110 and the fourth switch SW4 form a closed loop such that the capacitor 110 can be charged by the voltage source 120.
Referring to fig. 4, when the capacitor 110 is discharged to switch the operation state of the FET 20 to the on state, the control unit 140 may control the operation states of the first and second switches SW1 and SW2 to the on state. Specifically, the control unit 140 may output an on control signal to the first control line CL1 and an off control signal to the second control line CL 2. In this case, the operation states of the first switch SW1 and the second switch SW2 may be on states, and the operation states of the third switch SW3 and the fourth switch SW4 may be off states. The capacitor 110, the first switch SW1, the FET 20, and the second switch SW2 may form a closed loop such that the operation state of the FET 20 is converted into an on state.
That is, the FET control apparatus 100 according to the embodiment of the present disclosure may include a unit circuit for charging the capacitor 110 and a unit circuit for discharging the capacitor 110, respectively. In addition, the FET control device 100 may charge the capacitor 110 until the voltage of the capacitor 110 becomes equal to or higher than the target voltage (Vt). Accordingly, since the voltage of the capacitor 110 can be charged to correspond to the target voltage (Vt) based on the voltage (Vs) of the source terminal S, there is an advantage in that the operation state of the FET 20 can be adaptively controlled according to the voltage (Vs) of the source terminal S.
After the capacitor 110 is fully charged, the control unit 140 may be configured to electrically connect and disconnect any one of the charging and discharging lines and the other thereof every predetermined control period.
For example, after the capacitor 110 is charged such that the voltage of the capacitor 110 is equal to or higher than the target voltage (Vt), if the charging line is electrically connected to maintain the operation state of the FET 20 in the on state, the voltage of the capacitor 110 will gradually decrease. That is, since the current stored in the capacitor 110 is continuously output, the voltage of the capacitor 110 gradually decreases, so that the voltage of the capacitor 110 may become lower than the target voltage (Vt). In this case, since the gate voltage (Vgs) which is the difference between the voltage (Vg) of the gate terminal G and the voltage (Vs) of the source terminal S of the FET 20 is lower than the preset threshold voltage (Vth), the operation state of the FET 20 can be converted into the off state.
Accordingly, the control unit 140 may maintain the voltage applied to the gate terminal G of the FET 20 within a certain range by alternately electrically connecting the charge line and the discharge line every predetermined control period.
For example, if the control unit 140 controls the operation states of the first and second switches SW1 and SW2 to the on state, the operation states of the third and fourth switches SW3 and SW4 may be controlled to the off state. In addition, if the control unit 140 controls the operation states of the first switch SW1 and the second switch SW2 to be off-states, the operation states of the third switch SW3 and the fourth switch SW4 may be controlled to be on-states. That is, as shown in fig. 3 and 4, the operation states of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 may be switched according to a predetermined control period.
Preferably, the predetermined control period may be set to any one of 0.3ms (e.g., 3kHz frequency) to 10ms (e.g., 100Hz frequency). More preferably, the predetermined control period may be set to 0.5ms (e.g., 2kHz frequency).
Fig. 5 is a diagram showing an example of a voltage change of the capacitor 110 in the FET control apparatus 100 according to the embodiment of the present disclosure.
Hereinafter, in fig. 5, it is assumed that the operation states of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 are all on-states at a time before t 0. In addition, it is assumed that the target voltage (Vt) is set to Vt based on the voltage (Vs) of the source terminal S of the FET 20 and the preset threshold voltage (Vth).
Referring to fig. 5, the charging of the capacitor 110 may begin at t 0. For example, at t0, the control unit 140 may output an on control signal to the second control line CL2 to transition the operation states of the third switch SW3 and the fourth switch SW4 to the on state.
During t0 to t2, the capacitor 110 may be charged. Here, the control unit 140 may electrically connect the charging line until the voltage of the capacitor 110 becomes equal to the target voltage (Vt) or higher than the target voltage (Vt) by a certain voltage (Δv). That is, at t1, the voltage of the capacitor 110 may reach the target voltage (Vt), but the control unit 140 may electrically connect the charging line until t2 such that the voltage of the capacitor 110 becomes equal to the target voltage (Vt) or higher than the target voltage (Vt) by a certain voltage (Δv).
Here, the specific voltage (Δv) may be a voltage value preset by the control unit 140. For example, the specific voltage (DeltaV) may be 0[ V ] or higher. Preferably, the specific voltage (DeltaV) may be 0.1[ V ]. That is, the control unit 140 may be electrically connected to the charging line such that the voltage of the capacitor 110 becomes equal to the target voltage (Vt) or 0.1[ v ] higher than the target voltage (Vt).
If the discharge line is electrically connected to discharge the capacitor 110, the voltage of the capacitor 110 decreases. Therefore, in order to prevent the operation state of the FET 20 from being accidentally switched to the off state, the control unit 140 may electrically connect the charging line until the voltage of the capacitor 110 becomes equal to the target voltage (Vt) or higher than the target voltage (Vt) by a certain voltage (Δv).
In addition, during t2 to t3, the capacitor 110 may be discharged. At t2, the control unit 140 may output an off control signal to the second control line CL2 to transition the operation states of the third switch SW3 and the fourth switch SW4 to an off state, and output an on control signal to the first control line CL1 to transition the operation states of the first switch SW1 and the second switch SW2 to an on state.
As shown in fig. 5, when the capacitor 110 is charged (t 0 to t 2), the voltage of the capacitor 110 may exponentially increase, and when the capacitor 110 is discharged (t 2 to t 3), the voltage of the capacitor 110 may exponentially decrease. Accordingly, the control unit 140 may alternately electrically connect the charge line and the discharge line such that the voltage of the capacitor 110 is maintained to be equal to the target voltage (Vt) or higher than the target voltage (Vt) within a specific voltage range (Δv) during t1 to t 3.
After t3, the control unit 140 may electrically connect the charge line and the discharge line alternately with each other. The control unit 140 may electrically connect the charging line during t3 to t4, the discharging line during t4 to t5, the charging line during t5 to t6, and the discharging line during t6 to t 7. Here, when the charging wires are electrically connected, the connection of the discharging wires may be blocked, and when the discharging wires are electrically connected, the connection of the charging wires may be blocked.
For example, assuming that the predetermined control period is set to 0.5ms, the control unit 140 may be electrically connected to the charge line or the discharge line every 0.5ms. That is, in the embodiment of fig. 5, t1, t3, t5, and t7 may differ from each other by 0.5ms. In addition, in the embodiment of fig. 5, t2, t4, and t6 may differ from each other by 0.5ms.
Accordingly, the FET control apparatus 100 according to the embodiment of the present disclosure may maintain the voltage of the capacitor 110 to be equal to or higher than the target voltage (Vt) by alternately electrically connecting the charge line and the discharge line. In addition, the FET control device 100 may constantly maintain the voltage of the capacitor 110 within a specific range, so that the voltage applied to the gate terminal G of the FET 20 is constantly maintained. Therefore, malfunction of the FET 20 caused by application of the overvoltage can be prevented.
Preferably, the predetermined control period may be a period set such that the voltage of the capacitor 110 is maintained to be equal to or higher than the target voltage (Vt).
Specifically, the predetermined control period may be set to correspond to a time required for the voltage of the capacitor 110 to reach the target voltage (Vt) when the charged capacitor 110 is discharged.
For example, referring to fig. 5, at t0 to t2, the capacitor 110 may be charged until the voltage becomes equal to the target voltage (Vt) or higher than the target voltage (Vt) by a certain voltage (Δv). In addition, the control unit 140 may calculate in advance a time (t 2 to t 3) required for the voltage of the capacitor 110 to reach the target voltage (Vt) when the capacitor 110 is discharged, and set the calculated time as the control period. Here, the control unit 140 may calculate the control period based on the time constant of the capacitor 110 and the magnitude of the specific voltage (Δv). Here, the time constant of the capacitor 110 is a general term for calculating the charge time and the discharge time of the capacitor 110, and a detailed description thereof will be omitted.
In addition, the control unit 140 may maintain the voltage of the capacitor 110 to be equal to or higher than the target voltage (Vt) by alternately electrically connecting the charge line and the discharge line every predetermined period.
For example, in the embodiment of fig. 5, the control unit 140 may electrically connect the charging lines at t0, t3, t5, and t7 and block the connection of the discharging lines. In addition, the control unit 140 may electrically connect the discharge line at t2, t4, and t6 and block the connection of the charge line.
Accordingly, the FET control device 100 according to the embodiment of the present disclosure has an advantage of applying a voltage within a specific range to the gate terminal G of the FET 20. That is, the FET control device 100 can maintain the gate voltage (Vgs) equal to or higher than the threshold voltage (Vth), thereby preventing the operation state of the FET 20 from being accidentally switched to the off state.
If the voltage (Vs) of the source terminal S is changed, the control unit 140 may be configured to reset the target voltage (Vt) to correspond to the changed voltage (Vs) of the source terminal S.
Fig. 6 is a diagram showing another example of the voltage change of the capacitor 110 in the FET control apparatus 100 according to the embodiment of the present disclosure.
Fig. 6 is a diagram showing a change in the voltage of the capacitor 110 when the voltage (Vs) of the source terminal S changes at t 3. Specifically, fig. 6 is a diagram showing a case where the voltage (Vs) of the source terminal S at t3 is increased compared to the voltage (Vs) of the source terminal S at t 0.
The case where the voltage (Vs) of the source terminal S increases may correspond to the case where the voltage of the load connected to the battery pack 1 increases, or the case where the size of the resistor connected to the source terminal S of the FET 20 decreases so that the voltage applied to the source terminal S of the FET 20 increases. For example, when the operation state of the FET 20 is an off state, the voltage applied to the source terminal S of the FET 20 through the positive terminal p+ of the battery pack 1 may be increased. Hereinafter, a case where the voltage (Vs) of the source terminal S increases will be described, but the FET control apparatus 100 according to the embodiment of the present disclosure may also be applied to a case where the voltage (Vs) of the source terminal S decreases.
Referring to the embodiment of fig. 6, the control unit 140 may set a first target voltage (Vt 1) corresponding to the voltage (Vs) of the source terminal S at t 0. In addition, if the voltage (Vs) of the source terminal S increases at t3, the control unit 140 may set the second target voltage (Vt 2) corresponding to the increased voltage (Vs) of the source terminal S. After t3, the control unit 140 may increase the time for electrically connecting the charging line such that the voltage of the capacitor 110 becomes equal to the set second target voltage (Vt 2) or higher than the set second target voltage (Vt 2) by a certain voltage (Δv).
For example, it is assumed that the threshold voltage (Vth) of the FET 20 is 3[V ], the voltage (Vs) of the source terminal S at t0 is 1[V ], and the voltage (Vs) of the source terminal S after t3 is 2[V ]. The control unit 140 may set the first target voltage (Vt 1) at t0 to 4[V, which is the sum of the threshold voltage (Vth) and the voltage (Vs) of the source terminal S. In addition, the control unit 140 may set the second target voltage (Vt 2) at t3 to 5[V, which is the sum of the threshold voltage (Vth) and the increased voltage (Vs) of the source terminal S. If the target voltage (Vt) does not change after t3, the gate voltage (Vgs) of FET 20 may be lower than the threshold voltage (Vth). In this case, the operation state of the FET 20 is accidentally switched to the off state, so the control unit 140 can reset the target voltage (Vt) to a changed voltage (Vs) corresponding to the source terminal S.
In addition, the control unit 140 may be configured to change a predetermined control period based on the reset target voltage (Vt).
In the embodiment of fig. 6, after t3, the control unit 140 may charge the capacitor 110 by electrically connecting the charging line until the voltage of the capacitor 110 becomes equal to the second target voltage (Vt 2) or higher than the second target voltage (Vt 2) by a certain voltage (Δv). In addition, the control unit 140 may calculate the time taken until the fully charged capacitor 110 reaches the second target voltage (Vt 2) in consideration of the time constant of the capacitor 110. The control unit 140 may change the predetermined control period to the calculated time. That is, the times t1 to t3 may be control periods before the change, and the times t4 to t6 and t6 to t8 may be control periods after the change. For example, the control period before the change may be 0.5ms, and the control period after the change may be 0.7ms.
After t3, the control unit 140 may control the operation state of the FET20 by alternately electrically connecting the charge line and the discharge line based on the reset second target voltage (Vt 2) and the changed control period.
Accordingly, the FET control device 100 according to the embodiment of the present disclosure has an advantage of controlling the operation state of the FET20 by adaptively changing the voltage applied to the gate terminal G of the FET20 even if the voltage applied to the source terminal S of the FET20 is changed.
The measurement unit 130 may be configured to further measure the voltage (Vd) of the drain terminal D.
For example, referring to fig. 2, the measurement unit 130 may be electrically connected to the drain terminal D of the FET 20 through the first sensing line SL 1. In addition, the measurement unit 130 may measure the voltage (Vd) of the drain terminal D through the first sensing line SL 1.
The control unit 140 may be configured to receive the voltage (Vd) of the drain terminal D from the measurement unit 130.
The measurement unit 130 may convert the measurement voltage (Vd) of the drain terminal D into a digital signal. In addition, the measurement unit 130 may output the converted digital signal to a line connected to the control unit 140. The control unit 140 may receive the digital signal from the measurement unit 130 and obtain the voltage (Vd) of the drain terminal D measured by the measurement unit 130 by reading the received digital signal.
In addition, the control unit 140 may be configured to diagnose whether the FET 20 has a fault by comparing the voltage (Vd) of the drain terminal D and the voltage (Vs) of the source terminal S based on the operation state of the FET 20.
Specifically, the control unit 140 may compare the voltage (Vd) of the drain terminal D with the voltage (Vs) of the source terminal S after electrically connecting the charging lines. At this time, if the voltage (Vd) of the drain terminal D and the voltage (Vs) of the source terminal S are the same, the control unit 140 may determine that the operation state of the FET 20 is normally converted to the on state. That is, in this case, the control unit 140 may diagnose that the state of the FET 20 is a normal state. The control unit 140 may diagnose the state of the FET 20 as a fault state if the voltage (Vd) of the drain terminal D and the voltage (Vs) of the source terminal S are not identical. In particular, the control unit 140 may diagnose that the state of the FET 20 is an on-fault state in which the operation state is not converted into an on-state.
Accordingly, the FET control device 100 according to the embodiment of the present disclosure has an advantage of diagnosing whether the FET20 has a fault by comparing the voltage (Vd) of the drain terminal D and the voltage (Vs) of the source terminal S of the FET 20.
In addition, the FET control device 100 according to the present disclosure may be provided to the battery pack 1. That is, the battery pack 1 according to the present disclosure may include the above-described FET control device 100 and at least one battery cell 10. In addition, the battery pack 1 may further include electrical equipment (relays, fuses, etc.), a case, and the like.
For example, referring to fig. 2, the battery pack 1 may include a battery cell 10, a FET 20, and a FET control device 100. Here, the drain terminal D of the FET 20 may be connected to the positive terminal of the battery cell 10, the source terminal S of the FET 20 may be connected to the positive terminal p+ of the battery pack 1, and the capacitor 110 may be connected between the gate terminal G and the source terminal S of the FET 20.
Fig. 7 is a diagram schematically illustrating a FET control method according to another embodiment of the present disclosure.
The FET control method may be performed by the FET control apparatus 100 according to the embodiment of the present disclosure.
Referring to fig. 7, the FET control method may include a voltage measurement step (S100), a target voltage setting step (S200), a capacitor charging step (S300), and a FET operation state control step (S400).
The voltage measuring step (S100) is a step of measuring the voltage (Vs) of the source terminal S and the voltage of the capacitor 110 connected in parallel to the FET 20, and may be performed by the measuring unit 130.
For example, in the embodiment of fig. 2, the measurement unit 130 may measure the voltage (Vs) of the source terminal S of the FET 20 through the second sensing line SL 2. In addition, the measurement unit 130 may measure the voltage of the capacitor 110 through the third sensing line SL3 and the fourth sensing line SL 4.
The target voltage setting step (S200) is a step of setting a target voltage (Vt) based on the voltage (Vs) of the source terminal S measured in the voltage measuring step (S100), and may be performed by the control unit 140.
The control unit 140 may set the target voltage (Vt) by summing the voltage (Vs) of the source terminal S measured by the measurement unit 130 and the preset threshold voltage (Vth) of the FET 20.
The capacitor charging step (S300) is a step of charging the capacitor 110 such that the voltage of the capacitor 110 becomes equal to or higher than the target voltage (Vt), and may be performed by the control unit 140.
Specifically, after setting the target voltage (Vt), the control unit 140 may charge the capacitor 110 by controlling the operation states of the third switch SW3 and the fourth switch SW4 arranged on the charging line to the on state.
In addition, the control unit 140 may receive the voltage of the capacitor 110 from the measurement unit 130 and maintain the operation states of the third switch SW3 and the fourth switch SW4 in an on state until the voltage of the capacitor 110 becomes equal to the target voltage (Vt) or higher than the target voltage (Vt) by a certain voltage (Δv).
The FET operation state control step (S400) is a step of controlling the operation state of the FET 20 using the capacitor 110 fully charged in the capacitor charging step (S300), and may be performed by the control unit 140.
The control unit 140 may control the operation state of the FET20 by alternately electrically connecting the charge line and the discharge line. At this time, the control unit 140 may maintain the voltage of the capacitor 110 to be equal to or higher than the target voltage (Vt) by alternately electrically connecting the charge line and the discharge line according to a predetermined control period.
In addition, if the voltage applied to the source terminal S is changed while the control unit 140 is controlling the operation state of the FET 20, the control unit 140 may reset the target voltage (Vt) to correspond to the changed voltage (Vs) of the source terminal S and change the predetermined control period based on the target voltage (Vt) to be reset. Then, the control unit 140 may maintain the voltage of the capacitor 110 to be equal to or higher than the reset target voltage (Vt) by alternately electrically connecting the charge line and the discharge line based on the changed control period.
The FET control apparatus 100 according to the present disclosure may be applied to a BMS (battery management system). That is, the BMS according to the present disclosure may include the above-described FET control device 100. In this configuration, at least some of the components of the FET control apparatus 100 may be implemented by supplementing or adding the functions of the components included in the conventional BMS. For example, the capacitor 110, the voltage source 120, the measurement unit 130, and the control unit 140 of the FET control device 100 may be implemented as components of the BMS.
The embodiments of the present disclosure described above are not necessarily implemented by the apparatus and method, but may also be implemented by a program for implementing a function corresponding to the configuration of the present disclosure or a recording medium having the program recorded thereon. Such an implementation may be readily performed by one skilled in the art in light of the foregoing description of embodiments.
The present disclosure has been described in detail. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the disclosure, are given by way of illustration only, since various changes and modifications within the scope of the disclosure will become apparent to those skilled in the art from this detailed description.
Additionally, many alternatives, modifications and variations may be made by those skilled in the art to the present disclosure described above without departing from the technical aspects of the present disclosure, and the present disclosure is not limited to the above-described embodiments and drawings, but each embodiment may be selectively combined in part or in whole to allow various modifications.
(Reference numerals)
1: Battery pack
10: Battery cell
20：FET
100: FET control device
110: Capacitor with a capacitor body
120: Voltage source
130: Measuring unit
140: Control unit

Claims (10)

1. A FET control device for controlling an operating state of a FET including a drain terminal, a gate terminal, and a source terminal, the FET control device comprising:
a capacitor configured to be connected in parallel with the FET between the gate terminal and the source terminal through a discharge line;
a voltage source configured to be electrically connected to the capacitor through a charging wire and configured to charge the capacitor when the charging wire is electrically connected;
A measurement unit configured to measure a voltage of the source terminal and a voltage of the capacitor; and
A control unit configured to receive the voltage of the source terminal and the voltage of the capacitor from the measurement unit, set a target voltage by adding a preset threshold voltage and the voltage of the source terminal, charge the capacitor by the voltage source by electrically connecting the charging wire until the voltage of the capacitor becomes equal to or higher than the target voltage, and control an operation state of the FET by electrically connecting the discharging wire after the capacitor is fully charged,
Wherein the threshold voltage is preset to a voltage difference between the gate terminal and the source terminal, the voltage difference converting an operation state of the FET to an on state, and
Wherein when the voltage of the source terminal is changed, the control unit is configured to reset the target voltage to correspond to the changed voltage of the source terminal.
2. The FET control device of claim 1,
Wherein the discharge line is configured to include:
A first cell line having a first switch configured to connect the gate terminal and one end of the capacitor; and
A second cell line having a second switch configured to connect the source terminal and the other end of the capacitor.
3. The FET control device according to claim 2,
Wherein, the charging line includes:
A third cell line having a third switch configured to connect one end of the capacitor and a positive terminal of the voltage source; and
A fourth cell line having a fourth switch configured to connect the other end of the capacitor and the negative terminal of the voltage source,
Wherein one end of the capacitor is configured to be connected between the first switch and the third switch, and
Wherein the other end of the capacitor is configured to be connected between the second switch and the fourth switch.
4. The FET control device according to claim 3,
Wherein the control unit is configured to control the operating states of the first switch and the second switch simultaneously and to control the operating states of the third switch and the fourth switch simultaneously.
5. The FET control device of claim 1,
Wherein the control unit is configured to electrically connect any one of the charging wire and the discharging wire and electrically disconnect the other of the charging wire and the discharging wire every predetermined control period after the capacitor is fully charged.
6. The FET control device of claim 5,
Wherein the predetermined control period is a period set to maintain the voltage of the capacitor equal to or higher than the target voltage.
7. The FET control device of claim 5,
Wherein when the voltage of the source terminal is changed, the control unit is configured to change the predetermined control period based on the reset target voltage.
8. The FET control device of claim 1,
Wherein the measurement unit is configured to further measure the voltage of the drain terminal, and
Wherein the control unit is configured to receive the voltage of the drain terminal from the measurement unit and diagnose whether the FET has a fault by comparing the voltage of the drain terminal and the voltage of the source terminal based on the operation state of the FET.
9. A battery pack comprising the FET control apparatus according to any one of claims 1 to 8.
10. A FET control method for controlling an operating state of a FET including a drain terminal, a gate terminal, and a source terminal, the FET control method comprising:
a voltage measurement step of measuring a voltage of the source terminal and a voltage of a capacitor connected in parallel with the FET;
a target voltage setting step of setting a target voltage by adding a preset threshold voltage and the voltage of the source terminal measured in the voltage measuring step;
A capacitor charging step of charging the capacitor such that a voltage of the capacitor becomes equal to or higher than the target voltage; and
A FET operation state control step of controlling an operation state of the FET by using the capacitor fully charged in the capacitor charging step,
Wherein the threshold voltage is preset to a voltage difference between the gate terminal and the source terminal, the voltage difference converting an operation state of the FET to an on state, and
Wherein when the voltage of the source terminal is changed, the target voltage is reset to correspond to the changed voltage of the source terminal.
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