CN113766758A - Three-dimensional circuit generation method and circuit board - Google Patents
Three-dimensional circuit generation method and circuit board Download PDFInfo
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- CN113766758A CN113766758A CN202111161199.2A CN202111161199A CN113766758A CN 113766758 A CN113766758 A CN 113766758A CN 202111161199 A CN202111161199 A CN 202111161199A CN 113766758 A CN113766758 A CN 113766758A
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- dimensional
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention discloses a method for generating a three-dimensional circuit and a circuit board, wherein the method comprises the following steps: step A, grinding an initial circuit on a substrate; b, generating a metal layer on the substrate; step C, adhering a photosensitive film on the metal layer, exposing and developing; step D, etching off irrelevant parts; e, adhering the photosensitive film again, exposing and developing to obtain a groove; step F, obtaining a current three-dimensional line; step G, carrying out grinding treatment; and H, repeatedly executing the steps B to G to finish all the three-dimensional lines. The scheme can realize 3D interconnection of materials with good conductivity, such as copper circuit three-dimensional interconnection, thereby realizing complex application of the ceramic circuit board, realizing signal transmission perpendicular to the circuit board, greatly shortening transmission delay and being particularly suitable for application of a bus structure; the double-sided three-dimensional circuit can also realize the separation of signals and a power supply, realize higher reliability and anti-interference capability, solve the high impedance problem and improve the application range.
Description
Technical Field
The invention relates to the technical field of three-dimensional circuits, in particular to a three-dimensional circuit generating method and a circuit board.
Background
At present, with the continuous development of the technology, more than one layer of circuit on the circuit board is needed, multiple layers are needed to realize functions together, the circuits among the layers need to be connected with each other in a three-dimensional space, and in the existing mode, one of the multiple layers of circuit boards is used for realizing three-dimensional interconnection through a laminated pressing structure; in addition, the interconnection of the spatial multilayer circuit boards is realized by multilayer sintering processes such as Low Temperature Co-fired Ceramic (LTCC), High Temperature Co-fired Ceramic (HTCC) and the like; in addition, a TSV (Through Silicon Via) can also be used for 3D interconnection of spatial lines, but the method is only suitable for chip manufacturing and packaging. As for the lamination and lamination structure of multiple circuit boards and the LTCC, HTCC, etc., there are many problems of the conductor material during interconnection, such as silver migration and high impedance, which limits the application.
Thus, there is a need for a better solution to the problems of the prior art.
Disclosure of Invention
In view of this, the present invention provides a method for generating a three-dimensional circuit and a circuit board, so as to solve the problems in the prior art.
Specifically, the present invention proposes the following specific examples:
the embodiment of the invention provides a method for generating a three-dimensional line, which comprises the following steps:
a, grinding an initial line on a substrate, and reserving a photosensitive film for generating the initial line in the grinding process;
b, generating a metal layer on one side of the substrate, which is provided with the initial circuit;
step C, attaching a photosensitive film on the metal layer, and exposing and developing to expose the part of the metal layer irrelevant to the current three-dimensional circuit; the metal layer part related to the current three-dimensional line is connected with the initial line;
step D, etching off the metal layer part irrelevant to the current three-dimensional circuit, and removing the attached photosensitive film;
e, attaching the photosensitive film again for exposure and development to obtain a groove related to the current three-dimensional line; the bottom of the groove is connected with the metal layer part related to the current three-dimensional line;
step F, electroplating treatment is carried out in the groove to obtain the current three-dimensional line;
step G, reserving the photosensitive film which is attached again, and carrying out grinding treatment on the current three-dimensional line;
and H, repeatedly executing the steps B to G until all the three-dimensional lines are finished.
In a specific embodiment, the initial wiring is provided on one or both sides of the substrate.
In a specific embodiment, the metal layer is formed by PVD.
In a specific embodiment, the metal layer has a thickness in the range of 10nm to 10 μm.
In a specific embodiment, the metal layer has a thickness in the range of 300nm to 1 μm.
In a specific embodiment, when all stereo lines are completed, the method further includes:
all the remaining photosensitive film is removed.
In a specific embodiment, the method further comprises:
filling material is poured between the solid lines to provide structural support for the solid lines.
In a specific embodiment, Al is added to the filler2O3Powder and/or AlN powder.
In a specific embodiment, the method further comprises: and carrying out solder mask treatment on the external contact points on the three-dimensional circuit so as to limit the welding area.
In a specific embodiment, the method further comprises: and generating a fence surrounding the three-dimensional line on the substrate at the same time of generating the three-dimensional line.
In a specific embodiment, the enclosure surrounds to form a cavity; the method further comprises the following steps:
and sealing the opening of the cavity through the cover plate to obtain a sealed cavity.
In a specific embodiment, the method further comprises the following steps:
and carrying out heat treatment on the substrate with all the three-dimensional lines to release stress.
The embodiment of the invention also provides a circuit board which is manufactured by the method.
Therefore, the embodiment of the invention provides a method for generating a three-dimensional circuit and a circuit board, wherein the method comprises the following steps: a, grinding an initial line on a substrate, and reserving a photosensitive film for generating the initial line in the grinding process; b, generating a metal layer on one side of the substrate, which is provided with the initial circuit; step C, attaching a photosensitive film on the metal layer, and exposing and developing to expose the part of the metal layer irrelevant to the current three-dimensional circuit; the metal layer part related to the current three-dimensional line is connected with the initial line; step D, etching off the metal layer part irrelevant to the current three-dimensional circuit, and removing the attached photosensitive film; e, attaching the photosensitive film again for exposure and development to obtain a groove related to the current three-dimensional line; the bottom of the groove is connected with the metal layer part related to the current three-dimensional line; step F, electroplating treatment is carried out in the groove to obtain the current three-dimensional line; step G, reserving the photosensitive film which is attached again, and carrying out grinding treatment on the current three-dimensional line; and H, repeatedly executing the steps B to G until all the three-dimensional lines are finished. The scheme can realize 3D interconnection of materials with good conductivity, such as copper line three-dimensional interconnection, thereby realizing complex application of the ceramic circuit board, such as embedded part (embedded part) application, high-frequency application, anti-interference application, application for reducing circuit transmission delay and the like. The signal transmission vertical to the circuit board can be realized, the transmission delay is greatly shortened, and the bus structure is particularly suitable for application; the double-sided three-dimensional circuit can also realize the separation of signals and a power supply, realize higher reliability and anti-interference capability, solve the high impedance problem and improve the application range.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
Fig. 1 is a schematic flow chart illustrating a method for generating a stereo line according to an embodiment of the present invention;
fig. 2 is a schematic perspective view illustrating a three-dimensional structure of a circuit board generated by a method for generating a three-dimensional circuit according to an embodiment of the present invention;
fig. 3 is a schematic side structure diagram of a circuit board generated by a method for generating a three-dimensional circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another side of a circuit board generated by a method for generating a three-dimensional circuit according to an embodiment of the present invention;
fig. 5 is a schematic side structure diagram of a circuit board generated by the method for generating a three-dimensional circuit according to the embodiment of the present invention.
Illustration of the drawings:
100-a substrate; 110-initial line;
200-stereo lines; 210-support columns; 220-transverse connecting lines.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Example 1
The embodiment 1 of the invention discloses a method for generating a three-dimensional line, which comprises the following steps as shown in fig. 1:
step S101, polishing the initial line 110 on the substrate 100, and reserving a photosensitive film for generating the initial line 110 during the polishing process;
specifically, the initial wiring 110 is disposed on one or both sides of the substrate 100. As shown in fig. 2, 3 and 4.
The substrate 100 may be, for example, a ceramic plate, and the substrate 100 may be provided with the substrate 100 traces on one side or both sides of the substrate 100 in advance, and the initial traces 110 may be formed by substantially attaching a photosensitive film, exposing and developing the photosensitive film to form grooves of the initial traces 110, and then performing a plating operation to form the initial traces 110 in the grooves.
Due to the difference in uniformity of electroplating, the initial circuit 110 is not flat, which affects subsequent other processes, and therefore, in this process, a planarization process is required and the photosensitive film does not need to be removed.
Step S102, generating a metal layer on the side of the substrate 100 where the initial line 110 is disposed;
in a specific embodiment, to facilitate the growth of the three-dimensional wire 200, a metal layer is generated on the side of the substrate 100 on which the initial wire 110 is disposed, and if the initial wire 110 is present on both sides of the substrate 100, the metal layer is generated on both sides.
Further, the metal layer is formed by PVD (physical vapor deposition).
In a specific embodiment, the metal layer has a thickness in the range of 10nm to 10 μm.
Further, the thickness of the metal layer is in the range of 300nm-1 μm.
A specific metal layer may be a copper layer.
Step S103, attaching a photosensitive film on the metal layer, and performing exposure and development to expose a portion of the metal layer unrelated to the current three-dimensional line 200; the metal layer part related to the current stereo line 200 is connected to the initial line 110;
specifically, after a photosensitive film is attached to the metal layer, exposure and development are performed to expose portions irrelevant to the current solid line 200, and then the irrelevant portions are etched away, only the relevant portions are remained, and the growth of the current solid line 200 is continued.
Step S104, etching off a metal layer part irrelevant to the current three-dimensional line 200, and removing the attached photosensitive film;
the growth of the three-dimensional line 200 is continued by etching away extraneous portions and removing the attached photosensitive film, in preparation for the next step.
After the etching is completed, the support columns 210 of the three-dimensional line 200 are left partially obtained;
step S105, adhering a photosensitive film again for exposure and development to obtain a groove related to the current three-dimensional line 200; the bottom of the groove is connected with the metal layer part related to the current three-dimensional line 200;
in the above steps, the irrelevant portions are etched away, and only the relevant portions are remained, and on the basis, the relevant portions are subjected to exposure and development based on the photosensitive film to form the grooves relevant to the current three-dimensional circuit 200, so that the three-dimensional circuit 200 is formed by electroplating in the following process. The solid line 200 corresponds to the transverse connecting line 220 connecting the supporting columns 210.
Step S106, electroplating treatment is carried out in the groove to obtain the current three-dimensional line 200;
step S107, reserving the reattached photosensitive film, and carrying out grinding treatment on the current three-dimensional line 200;
through the above steps S102 to S107, one stereo line 200 can be completed, but in practical cases, there may be a plurality of stereo lines 200, in which case, S102 to S107 need to be performed a plurality of times to complete all stereo lines 200, that is, step S108 is performed.
And step S108, repeatedly executing the step S102 to the step S107 until all the stereoscopic lines 200 are completed.
In addition, in this embodiment, when all the stereo lines 200 are completed, the method further includes:
and removing all residual photosensitive films and removing the connecting metal reserved for ensuring electroplating.
By removing the residual photosensitive film and the connecting metal reserved for ensuring electroplating, the cleanness and tidiness of the obtained three-dimensional circuit 200 can be ensured, and the working stability of the three-dimensional circuit 200 is also ensured.
In a specific embodiment, the method further comprises:
a filler is poured between the solid lines 200 to provide structural support for the solid lines 200.
Specifically, the filler fills objects with different dielectric constants according to the purpose of the circuit, and is used as a structural carrier between circuits.
In a specific embodiment, Al is added to the filler2O3Powder and/or AlN powder.
Further, by filling with Al2O3The powder and/or AlN powder may effectively increase the thermal conductivity, facilitating the removal of heat generated by the three-dimensional circuit 200.
Further, the method further comprises:
the external contact points on the three-dimensional circuit 200 are subjected to solder resist treatment to limit the soldering area.
Specifically, the solid line 200 needs to be connected to an external circuit or an external component, and the specific connection generally adopts a soldering manner, but when soldering, the position of a Solder joint or a Solder pad is easily enlarged, so that other parts are easily affected.
In addition, in the present embodiment, since the growth speed, length, height, etc. can be controlled, the generated three-dimensional circuit 200 can realize die bonding and wire bonding planes with different heights or SMD (Surface Mounted Devices) parts welding and fixing surfaces.
In a specific embodiment, the method further comprises:
at the same time as the solid line 200 is generated, a fence surrounding the solid line 200 is generated on the substrate 100.
Further, the enclosing wall surrounds to form a cavity; the method further comprises the following steps:
and sealing the opening of the cavity through the cover plate to obtain a sealed cavity.
Specifically, when the three-dimensional circuit 200 is generated to obtain a circuit board, a wall cavity can be synchronously grown on the substrate 100 to realize sealed packaging; the periphery of the circuit board can synchronously grow a wall cavity, an airtight cavity is obtained after the cover plate is sealed and packaged, and gas or liquid can flow through the cavity, so that the purpose of heat dissipation is achieved.
Further, in a particular embodiment, the method further comprises:
and carrying out heat treatment on the substrate with all the three-dimensional lines to release stress.
Specifically, after all three-dimensional lines are obtained, heat treatment can be performed to release stress, so that the properties of the obtained product are more stable, and the long-term stable operation is facilitated.
Example 2
The embodiment 2 of the invention also discloses a circuit board which is manufactured by the method in the embodiment 1. The resulting wiring board may be as shown in fig. 2 and 5.
Therefore, the embodiment of the present invention provides a method for generating a three-dimensional circuit 200 and a circuit board, where the method includes: step A, grinding an initial line 110 on a substrate 100, and reserving a photosensitive film for generating the initial line 110 in the grinding process; step B, generating a metal layer on the side of the substrate 100 on which the initial line 110 is disposed; step C, attaching a photosensitive film on the metal layer and carrying out exposure and development to expose the metal layer part irrelevant to the current three-dimensional circuit 200; the metal layer part related to the current stereo line 200 is connected to the initial line 110; step D, etching off a metal layer part irrelevant to the current three-dimensional line 200, and removing the attached photosensitive film; step E, attaching the photosensitive film again for exposure and development to obtain a groove related to the current three-dimensional line 200; the bottom of the groove is connected with the metal layer part related to the current three-dimensional line 200; step F, electroplating treatment is carried out in the groove to obtain the current three-dimensional line 200; step G, reserving the photosensitive film which is attached again, and carrying out grinding treatment on the current three-dimensional line 200; and H, repeatedly executing the steps B to G until all the three-dimensional lines 200 are completed. The scheme can realize 3D interconnection of materials with good conductivity, such as copper line three-dimensional interconnection, thereby realizing complex application of the ceramic circuit board, such as embedded part (embedded part) application, high-frequency application, anti-interference application, application for reducing circuit transmission delay and the like. The signal transmission vertical to the circuit board can be realized, the transmission delay is greatly shortened, and the bus structure is particularly suitable for application; the double-sided three-dimensional circuit 200 can also realize the separation of signals and power supply, realize higher reliability and anti-interference ability, simultaneously also solve the high impedance problem, improve the range of application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a portion of a module. It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.
Claims (13)
1. A method for generating a stereo line, comprising:
a, grinding an initial line on a substrate, and reserving a photosensitive film for generating the initial line in the grinding process;
b, generating a metal layer on one side of the substrate, which is provided with the initial circuit;
step C, attaching a photosensitive film on the metal layer, and exposing and developing to expose the part of the metal layer irrelevant to the current three-dimensional circuit; the metal layer part related to the current three-dimensional line is connected with the initial line;
step D, etching off the metal layer part irrelevant to the current three-dimensional circuit, and removing the attached photosensitive film;
e, attaching the photosensitive film again for exposure and development to obtain a groove related to the current three-dimensional line; the bottom of the groove is connected with the metal layer part related to the current three-dimensional line;
step F, electroplating treatment is carried out in the groove to obtain the current three-dimensional line;
step G, reserving the photosensitive film which is attached again, and carrying out grinding treatment on the current three-dimensional line;
and H, repeatedly executing the steps B to G until all the three-dimensional lines are finished.
2. The method of claim 1, wherein the initial traces are disposed on one or both sides of the substrate.
3. The method of claim 1, wherein the metal layer is formed by PVD.
4. The method of claim 1 or 3, wherein the metal layer has a thickness in the range of 10nm to 10 μm.
5. The method of claim 4, wherein the metal layer has a thickness in a range from 300nm to 1 μm.
6. The method of claim 1, wherein upon completion of all stereo lines, further comprising:
all the remaining photosensitive film is removed.
7. The method of claim 1, further comprising:
filling material is poured between the solid lines to provide structural support for the solid lines.
8. The method of claim 7, wherein the filler has Al added thereto2O3Powder and/or AlN powder.
9. The method of claim 1, further comprising:
and carrying out solder mask treatment on the external contact points on the three-dimensional circuit so as to limit the welding area.
10. The method of claim 1, further comprising:
and generating a fence surrounding the three-dimensional line on the substrate at the same time of generating the three-dimensional line.
11. The method of claim 10, wherein the perimeter wall forms a cavity around it; the method further comprises the following steps:
and sealing the opening of the cavity through the cover plate to obtain a sealed cavity.
12. The method of claim 1, further comprising:
and carrying out heat treatment on the substrate with all the three-dimensional lines to release stress.
13. A wiring board, characterized in that it is produced by the method of any one of claims 1 to 12.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111161199.2A CN113766758B (en) | 2021-09-30 | 2021-09-30 | Three-dimensional circuit generation method and circuit board |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111161199.2A CN113766758B (en) | 2021-09-30 | 2021-09-30 | Three-dimensional circuit generation method and circuit board |
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| CN113766758A true CN113766758A (en) | 2021-12-07 |
| CN113766758B CN113766758B (en) | 2023-04-11 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1120611A (en) * | 1978-12-29 | 1982-03-23 | Hormazdyar M. Dalal | Forming interconnections for multilevel interconnection metallurgy systems |
| CN103298275A (en) * | 2013-05-20 | 2013-09-11 | 江苏长电科技股份有限公司 | Metal circuit plating and etching successive method for multilayer circuit base board with metal frame |
| CN106961803A (en) * | 2017-04-07 | 2017-07-18 | 安捷利电子科技（苏州）有限公司 | A kind of preparation method of lifting PCB circuit depth-width ratios |
-
2021
- 2021-09-30 CN CN202111161199.2A patent/CN113766758B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1120611A (en) * | 1978-12-29 | 1982-03-23 | Hormazdyar M. Dalal | Forming interconnections for multilevel interconnection metallurgy systems |
| CN103298275A (en) * | 2013-05-20 | 2013-09-11 | 江苏长电科技股份有限公司 | Metal circuit plating and etching successive method for multilayer circuit base board with metal frame |
| CN106961803A (en) * | 2017-04-07 | 2017-07-18 | 安捷利电子科技（苏州）有限公司 | A kind of preparation method of lifting PCB circuit depth-width ratios |
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| CN113766758B (en) | 2023-04-11 |
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