CN109874225B - Integrated circuit board - Google Patents
Integrated circuit board Download PDFInfo
- Publication number
- CN109874225B CN109874225B CN201811407939.4A CN201811407939A CN109874225B CN 109874225 B CN109874225 B CN 109874225B CN 201811407939 A CN201811407939 A CN 201811407939A CN 109874225 B CN109874225 B CN 109874225B
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- China
- Prior art keywords
- conductive film
- circuit
- stacked
- circuit board
- insulating carrier
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- 238000007747 plating Methods 0.000 claims description 8
- 230000004907 flux Effects 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 26
- 230000000694 effects Effects 0.000 abstract description 6
- 230000002457 bidirectional effect Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 239000000919 ceramic Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Abstract
The integrated circuit board comprises an insulating carrier plate, at least one conductive film circuit arranged on one surface of the insulating carrier plate, and at least one layer of stacked circuit arranged on partial region of the conductive film circuit; and the conductive film circuit or the stacked circuit built on the insulating carrier plate through bidirectional fractional etching has the circuit thickness relatively larger than the circuit distance, which is beneficial to integrating a low-power control circuit and a high-power electronic element on the same circuit board, and enabling the high-power electronic element to reduce the distance of electrical pins, thereby reducing the overall structure cost by the integration effect.
Description
Technical Field
The present invention relates to an integrated circuit board, and more particularly, to an integrated circuit board having fine lines with high accuracy and high lines with large current lines, and a method for manufacturing conductive film lines thereof.
Background
The ceramic copper-clad plate is an important component of a high-voltage high-power IGBT module, has the characteristics of high heat conduction, high electrical insulation, high mechanical strength, low expansion and the like of ceramic, has the high conductivity and excellent welding performance of oxygen-free copper, and can etch various circuit patterns like a PCB (printed circuit board).
A method for selective metallization on ceramic substrates is known, in which a ceramic layer is sinter bonded to a metal layer, such as a copper layer, at a high temperature by using a Direct Bonded Copper (DBC) technique, and the bonding force between the ceramic layer and the copper layer is strong and reliable after sintering.
However, there are problems of internal stress and interface void ratio between the large-area ceramic layer interface and the large-area copper layer interface, which further generate the material defect commonly called shell grain, and it can only use one-way etching to form the circuit, so its minimum line distance can only be equal to the height of the same line, and therefore the characteristic of integrating different power devices is limited.
Disclosure of Invention
The present invention provides an integrated circuit board that integrates a low current circuit with a relatively low thickness and a high current circuit with a relatively high thickness on the same surface of an insulating carrier, and a method for manufacturing a conductive film circuit related thereto.
The integrated circuit board comprises an insulating carrier plate, at least one conductive film circuit arranged on one surface of the insulating carrier plate, and at least one layer of stacked circuit arranged on partial region of the conductive film circuit.
According to the above technical features, the integrated circuit board has a conductive film circuit disposed on both sides of the insulating carrier plate, at least one through hole is disposed on the insulating carrier plate, and a conductive member for electrically connecting the conductive film circuits on both sides of the insulating carrier plate and increasing the amount of current flowing through the conductive film circuit is filled in the at least one through hole.
According to the above technical features, the integrated circuit board has a stacked circuit on the conductive film circuit, and a bonding layer made of a conductive material is disposed between the conductive film circuit and the stacked circuit.
According to the technical characteristics, the integrated circuit board is provided with a plurality of stacked circuits on the conductive film circuit, and joint layers made of conductive materials are respectively arranged between the conductive film circuit and the plurality of stacked circuits and between the stacked circuits, so that secondary buffering is achieved by the joint layers among the stacked circuits, and the problem of shell line effect and stress of joint with heterogeneous materials is reduced.
According to the technical characteristics, the integrated circuit board is covered with a film coating layer on the conductive film circuit and the exposed part of each stacked circuit.
Each bonding layer can be selected from one of solder, flux, plating, or a combination thereof.
The stacked circuit on the conductive film circuit has at least one first bridging block crossing and connecting between the adjacent blocks to which the conductive film circuit belongs.
The stacked circuit on the upper layer of the conductive film circuit is provided with at least one first bridging block which is connected between the adjacent blocks of the conductive film circuit in a crossing way; and the stacked circuit on the upper layer of at least one stacked circuit is provided with at least one second bridging block which is connected between the adjacent blocks of the stacked circuit on the lower layer in a crossing way.
The conductive film circuit manufacturing method of the invention comprises the following steps: (a) establishing a first etching framework, providing a temporary carrier plate, covering a conductive film on the surface of the temporary carrier plate, and taking the surface of the conductive film which is not contacted with the temporary carrier plate as a first etching surface; (b) first etching the circuit, removing the non-circuit pattern part on the first etched surface of the conductive film to a preset depth by etching; (c) establishing a second etching framework, providing an insulating carrier plate, and fixedly arranging the conductive film and the temporary carrier plate on the insulating carrier plate in a manner that a first etching surface of the conductive film completing the first line etching is contacted with the insulating carrier plate; (d) generating a second etched surface, and removing the temporary carrier plate above the conductive film after the conductive film is really fixed on the insulating carrier plate, so that the surface of the conductive film originally contacted with the temporary carrier plate is exposed to form a second etched surface; (e) and performing second circuit etching, namely completely removing the non-circuit pattern part corresponding to the second etched surface and the first etched surface of the conductive film in an etching mode, so that a conductive film circuit with the circuit thickness relatively larger than the circuit interval can be constructed on the insulating carrier plate.
The temporary carrier plate may be a quartz glass or ceramic carrier plate.
The conductive film may be a copper foil.
The insulating carrier may be a ceramic carrier.
The invention is mainly used for the design that one surface of an insulating carrier plate is provided with a conductive film circuit, and at least one layer of stacked circuits are covered on partial areas of the conductive film circuit, so that a low-power control circuit and a high-power electronic element can be integrated on the same circuit board, the spacing of electrical pins can be reduced by the high-power electronic element, and the integral structure cost is reduced by the integrated effect; particularly, through the bidirectional fractional etching, the limitation that the minimum line distance can only be as high as the same line height when the traditional circuit is used for unidirectional etching is effectively solved, the problems of internal stress and junction porosity are effectively solved, and the defect of the material commonly called shell grains is avoided.
Drawings
FIG. 1: the first embodiment of the invention is an integrated circuit board structure cross-sectional view.
FIG. 2: a cross-sectional view of an integrated circuit board structure according to a second embodiment of the present invention.
FIG. 3: a cross-sectional view of an integrated circuit board structure according to a third embodiment of the present invention.
FIG. 4: the invention relates to a conductive film circuit manufacturing flow chart.
FIG. 5: the conductive film circuit of the present invention is a schematic diagram of the forming state of each step in the manufacturing process.
FIG. 6: a cross-sectional view of an integrated circuit board structure according to a fourth embodiment of the present invention.
Description of the figure numbers:
10 insulating carrier plate
11 through hole
12A conductive film
12 conductive film circuit
13 conductive member
20 stacked circuit
211 first bridging block
212 second bridging block
22 bonding layer
30 coating film layer
40 temporary carrier plate.
Detailed Description
The present invention mainly provides an integrated circuit board with high precision fine circuit and high current line and its related conductive film circuit manufacturing method, as shown in fig. 1, the integrated circuit board of the present invention has an insulating carrier plate 10, at least one conductive film circuit 12 is disposed on one side of the insulating carrier plate 10, and at least one layer of stacked circuit 20 is disposed on a partial region of the conductive film circuit 12.
Accordingly, the integrated circuit board can form a low current circuit with a lower thickness formed by the conductive film circuit 12 and a high current circuit with a higher thickness formed by the conductive film circuit 12 and the stacked circuit 20 on the same surface of the insulating carrier plate 10, so that a low power control circuit and a high power electronic element can be integrated on the same circuit board, and the high power electronic element can also reduce the distance between electrical pins, thereby reducing the overall structure cost by the integration effect.
In the integrated circuit board of the present invention, when implementing, the pre-fabricated stacked circuit 20 is bonded to the conductive film circuit 12 by using the solder, the flux or the bonding film on the stacked circuit 20 to form the bonding layer 22, and the conductive film circuit 12 and the stacked circuit 20 are bonded by using the bonding layer 22, and the stacked circuit 20 of the second or more layers can be stacked by using the same method, as shown in fig. 2, and the bonding layer 22 between the stacked circuits 20 is used to achieve the secondary buffer, so as to reduce the shell-ring effect and the stress problem of bonding with the heterogeneous material.
Furthermore, the stacked circuit 20 on the conductive film circuit 12 has at least one first bridging block 211 (shown in fig. 6) crossing and connecting between the adjacent blocks to which the conductive film circuit 12 belongs; even in the embodiment where the integrated circuit board is stacked with the stacked wiring 20 above the second layer, the stacked circuit 20 on the upper layer of at least one stacked circuit 20 may also have at least one second bridging block 212 (as shown in fig. 6) crossing and connecting between the adjacent blocks of the stacked circuit 20 on the lower layer, at least the circuit design of the first bridging block 211 (or the first bridging block 211 and the second bridging block 212) separates the original whole circuit layer into a plurality of three-dimensionally stacked connected block circuit layers, thereby guiding the expansion stress to the height direction and buffering the stress in the horizontal direction by the bending of the bridging blocks, the stress problem of the shell effect and the stress problem of the bonding with the heterogeneous material are reduced by a relatively more positive and reliable means, and it is worth mentioning that the stress problem between the carrier and the carrier can be effectively improved and the reliability of the carrier and the circuit can be improved by guiding the stress to the height direction.
Even further, a plating layer 30 can be coated on the exposed portions of the conductive film circuit 12 and each stacked circuit 20 by using a plating or electroless plating method, so as to achieve the purpose of reducing the line pitch and protecting the stacked circuits 20 by adding the plating layer 30.
Of course, in the integrated circuit board of the present invention, when the integrated circuit board is implemented, the plurality of stacked circuits 20 fabricated in advance may be stacked and bonded to a predetermined thickness by using solder, flux or the stacked circuits 20 each having a bonding film coated thereon, and then the plurality of stacked circuits 20 bonded in advance may be coated on the conductive film circuit 12; of course, each of the bonding layers 22 may be selected to be one of solder, flux, plating, or a combination thereof.
As shown in fig. 3, in the integrated circuit board of the present invention, during the implementation, the integrated circuit board may also have a conductive film circuit 12 disposed on both sides of the insulating carrier 10 according to the requirement of the circuit design, at least one through hole 11 is disposed on the insulating carrier 10, and a conductive member 13 for electrically connecting the conductive film circuit 12 forming the insulating carrier 10 and increasing the amount of current flowing is filled in the at least one through hole 11 corresponding to different current densities, so as to achieve the purpose of disposing the large current circuits on both sides of the insulating carrier 10.
The integrated circuit board of the present invention can further use a manufacturing method of bi-directional fractional etching to make the thickness of the conductive film line 12 or the stacked line 20 on the insulating carrier 10 be relatively larger than the line pitch, even the line thickness can be twice of the line pitch, and under the condition of the same line thickness, the line design with smaller line pitch can be realized, and furthermore, the conductive film line 12 on the insulating carrier 10 of the integrated circuit board of the present invention can be a film-coated line or a copper foil line.
Referring to fig. 4 and 5, the method for manufacturing a conductive film circuit of the present invention includes the following steps.
(a) Establishing a first etching framework, providing a temporary carrier plate 40, covering a conductive film 12A on the surface of the temporary carrier plate 40, and using the surface of the conductive film 12A not contacted with the temporary carrier plate 40 as a first etching surface; in practice, the temporary carrier 40 may be a quartz glass or ceramic carrier; the conductive film 12A may be a copper foil.
(b) The first etching process is performed to remove the non-circuit pattern portion on the first etched surface of the conductive film 12A to a predetermined depth.
(c) Establishing a second etching framework, providing an insulating carrier plate 10, and fixing the conductive film 12A and the temporary carrier plate 40 on the insulating carrier plate 10 in a manner that the first etching surface of the conductive film 12A completing the first line etching is contacted with the insulating carrier plate 10; in practice, the insulating carrier 10 may be a ceramic carrier.
(d) After the conductive film 12A is firmly fixed on the insulating carrier 10, the temporary carrier 40 above the conductive film 12A is removed, so that the surface of the conductive film 12A originally contacting the temporary carrier 40 is exposed to form a second circuit etching surface.
(e) And a second circuit etching step, in which the non-circuit pattern portion corresponding to the second etched surface of the conductive film 12A and the first etched surface of the conductive film 12A is completely removed by etching, so as to construct a conductive film circuit 12 with a circuit thickness relatively larger than the circuit pitch on the insulating carrier 10.
Because the conductive film circuit 12 with the circuit thickness relatively larger than the circuit distance is built on the insulating carrier plate 10 through bidirectional fractional etching, the invention not only effectively solves the limitation that the minimum line distance of the traditional circuit can only be equal to the height of the same line by using unidirectional etching.
Particularly, when the conductive film 12A after the first etching is fixed on the insulating carrier 10, since the contact area between the conductive film 12A and the insulating carrier 10 is much smaller than the original area of the conductive film 12A that has not been etched or replaced by a plating circuit, the problems of internal stress and junction porosity caused by the Direct Bonded Copper (DBC) technology can be effectively solved, and the material defect commonly called shell grain can be avoided.
Claims (6)
1. An integrated circuit board is characterized in that the integrated circuit board comprises an insulating carrier plate (10), at least one conductive film circuit (12) is arranged on one surface of the insulating carrier plate (10), and at least one layer of stacked circuit (20) is covered on partial area of the conductive film circuit (12);
wherein the integrated circuit board is stacked with more than a second layer of stacked circuits (20), the stacked circuit (20) on the upper layer of the conductive film circuit (12) is provided with at least one first bridging block (211) which is connected between the adjacent blocks of the conductive film circuit (12) in a crossing way; and the stacked circuit (20) on the upper layer of at least one stacked circuit (20) is provided with at least one second bridging block (212) which is connected between the adjacent blocks of the stacked circuit (20) on the lower layer in a crossing way.
2. The integrated circuit board of claim 1, wherein the conductive film lines (12) are disposed on both sides of the insulating carrier (10), at least one through hole (11) is disposed on the insulating carrier (10), and a conductive member (13) for electrically connecting the conductive film lines (12) forming the insulating carrier (10) and increasing the amount of current flowing is filled in the at least one through hole (11).
3. The integrated circuit board of claim 1, wherein a stacked trace (20) is disposed on the conductive film trace (12), and a bonding layer (22) made of a conductive material is disposed between the conductive film trace (12) and the stacked trace (20).
4. The integrated circuit board of claim 1, wherein a bonding layer (22) made of a conductive material is disposed between the conductive film line (12) and each of the stacked lines (20).
5. The IC board of any one of claims 1 to 4, wherein the IC board is coated with a plating layer (30) on the exposed portions of the conductive film lines (12) and each of the stacked lines (20).
6. The integrated circuit board of claim 3 or 4, wherein each of the bonding layers (22) is selected from one of solder, flux, plating, or a combination thereof.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106141270 | 2017-11-28 | ||
| TW106141270A TW201927094A (en) | 2017-11-28 | 2017-11-28 | Integrated carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109874225A CN109874225A (en) | 2019-06-11 |
| CN109874225B true CN109874225B (en) | 2021-03-02 |
Family
ID=66916991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811407939.4A Active CN109874225B (en) | 2017-11-28 | 2018-11-23 | Integrated circuit board |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109874225B (en) |
| TW (1) | TW201927094A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111447753A (en) * | 2020-03-18 | 2020-07-24 | 盐城维信电子有限公司 | Circuit board and manufacturing method thereof |
| CN111405770B (en) * | 2020-03-19 | 2021-10-22 | 盐城维信电子有限公司 | Circuit board and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4992139A (en) * | 1989-11-16 | 1991-02-12 | Motorola, Inc. | Conductive mask and method of making same |
| CN101310571A (en) * | 2005-11-15 | 2008-11-19 | 三井金属矿业株式会社 | Printed wiring board, method for manufacturing same and use of same |
| JP2011018728A (en) * | 2009-07-08 | 2011-01-27 | Fujikura Ltd | Laminated wiring board, and method of manufacturing the same |
| CN102030565A (en) * | 2009-10-02 | 2011-04-27 | 揖斐电株式会社 | Ceramic wiring board and method of manufacturing thereof |
| KR20120019144A (en) * | 2010-08-25 | 2012-03-06 | 아페리오(주) | Method for manufacturing a printed circuit board |
| CN104684263A (en) * | 2013-11-29 | 2015-06-03 | 深南电路有限公司 | Processing method of female and male thick copper circuit board |
| CN105992463A (en) * | 2015-03-06 | 2016-10-05 | 深南电路股份有限公司 | Method for manufacturing step circuit board and step circuit board |
-
2017
- 2017-11-28 TW TW106141270A patent/TW201927094A/en unknown
-
2018
- 2018-11-23 CN CN201811407939.4A patent/CN109874225B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4992139A (en) * | 1989-11-16 | 1991-02-12 | Motorola, Inc. | Conductive mask and method of making same |
| CN101310571A (en) * | 2005-11-15 | 2008-11-19 | 三井金属矿业株式会社 | Printed wiring board, method for manufacturing same and use of same |
| JP2011018728A (en) * | 2009-07-08 | 2011-01-27 | Fujikura Ltd | Laminated wiring board, and method of manufacturing the same |
| CN102030565A (en) * | 2009-10-02 | 2011-04-27 | 揖斐电株式会社 | Ceramic wiring board and method of manufacturing thereof |
| KR20120019144A (en) * | 2010-08-25 | 2012-03-06 | 아페리오(주) | Method for manufacturing a printed circuit board |
| CN104684263A (en) * | 2013-11-29 | 2015-06-03 | 深南电路有限公司 | Processing method of female and male thick copper circuit board |
| CN105992463A (en) * | 2015-03-06 | 2016-10-05 | 深南电路股份有限公司 | Method for manufacturing step circuit board and step circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201927094A (en) | 2019-07-01 |
| CN109874225A (en) | 2019-06-11 |
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