CN113746565A - Laser echo signal receiving device and method for linear array anti-sniper detection system - Google Patents
Laser echo signal receiving device and method for linear array anti-sniper detection system Download PDFInfo
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Abstract
The invention belongs to the technical field of photoelectric detection, and particularly relates to a laser echo signal receiving device and method of a linear array anti-sniper detection system. The laser echo signal receiving device of the linear array anti-sniper detection system comprises: the data acquisition device and the data receiving device; wherein the data receiving apparatus includes: the data processing device comprises a data difference unit, a data receiving unit and a data preprocessing and storing unit; the invention has small volume and light weight of each unit, and can be used by splitting according to functions. The small divided space of the system can be fully utilized after the disassembly, and the installation is flexible. The problem of in the mode one, the structure installation inflexibility that laser echo signal receiving module inseparability caused is solved. Meanwhile, the failure troubleshooting of the system laser echo signal receiving module is facilitated, and the problem of difficulty in troubleshooting is solved. In addition, the invention solves the problems of a large number of interface lines and a large size of an interface connector caused by data parallel transmission and reception.
Description
Technical Field
The invention belongs to the technical field of photoelectric detection, and particularly relates to a laser echo signal receiving device and method of a linear array anti-sniper detection system.
Background
In modern military wars, anti-terrorism, security protection and protection of an operator, an anti-sniper photoelectric detection system based on a linear array detector is assembled and used for searching, detecting and giving a sound alarm to threaten a sniper. The device mainly comprises a laser emitting module, a laser echo signal receiving module, a signal processing module and a white light telescopic module. The laser echo signal receiving module finishes the work of collecting, sending, receiving, preprocessing and storing target characteristic data, and is used for a post-stage signal processing module to read, process and extract threat target signals. Therefore, the system also comprises a data acquisition device and a data receiving device (comprising a sending preprocessing unit, a receiving preprocessing unit and a storage unit) according to functions. When the linear array anti-sniper detection system is in a real-time continuous working state, accurate receiving of the acquired image data requires strict matching of sending and receiving working clocks and data transmission, so that spatial displacement and bit error rate between frames of the sequence image data are reduced.
The image data of the existing anti-sniper photoelectric detection system is received in two ways:
in the first mode, the data receiving device and the data acquisition device are installed on an inseparable single body. After image signals acquired by the data acquisition device are converted into digital quantity through an A/D (analog-to-digital conversion) chip, the digital quantity is directly transmitted to the data receiving device in parallel or in series, and preprocessing and storage are completed for later-stage access. However, the anti-sniper photoelectric detection system is mostly handheld, and is generally small in size, although the size of the laser echo signal receiving module is reduced by monomer integration, the whole system is inseparable, and the requirements of flexible installation of the module and easy troubleshooting of faults cannot be met.
And in the second mode, the data receiving device and the data acquisition device are respectively arranged at different positions in the system, and the data receiving device and the data acquisition device are interconnected through a connecting cable. The image signal collected by the data collecting device is converted into digital quantity by an A/D (analog-to-digital conversion) chip and then is transmitted in parallel or in series by a connecting cable. This allows 2 devices to be flexibly installed in the system interior space and also facilitates troubleshooting. However, due to the working principle of the system, 3 kinds of synchronous clocks are needed for receiving image data, the detection precision requirement is added, and the data conversion precision is 14 bits, so that the number of interface lines needed by data parallel transmission is not less than 14, and the occupied number of the interface lines is not less than 17. And serial transmission is adopted, so that the occupied number of port lines can be reduced, but the serial transmission of data in the cable is easily interfered by an electromagnetic field, so that clock signal transmission displacement, serial data transmission misconnection and misconnection are caused, the error rate is high, and finally, image data cannot be used.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to provide a reliable and stable laser echo signal data receiving device and method for a linear array anti-sniper photoelectric detection system to solve the problems that the structure installation is inflexible, trouble elimination is difficult, the number of data transmission interface lines is too large, or the transmission anti-jamming capability is poor, misconnection and misconnection data are caused by the design mode of the data receiving device in the application of the handheld linear array anti-sniper photoelectric detection system.
(II) technical scheme
In order to solve the technical problem, the invention provides a laser echo signal receiving device of a linear array anti-sniper detection system, which comprises: the data acquisition device and the data receiving device; wherein the data receiving apparatus includes: the data processing device comprises a data difference unit, a data receiving unit and a data preprocessing and storing unit;
the data differential unit is stacked with the data acquisition device and used for converting an original synchronous signal, an original clock signal and an original image data signal output by the data acquisition device into differential signals and transmitting the differential signals to the data receiving unit;
the data receiving unit is used for receiving the differential signals and converting the differential signals into original synchronous signals, original clock signals and original image data signals output by the data acquisition device for use by the data preprocessing and storage unit;
the data preprocessing and storage unit is used for carrying out calculation preprocessing on the received original image data signals according to the original synchronous signals and the original clock signals, and then storing the original image data signals in a register inside the data preprocessing and storage unit for a subsequent signal processing module to use.
Wherein the original synchronization signal comprises: a frame synchronization signal and a pixel synchronization signal; the original clock signal comprises a data transfer clock signal.
The data differential unit is used for carrying out differential operation on the frame synchronization signal, the pixel synchronization signal, the data transmission clock signal and the original image data signal, generating 8 paths of differential signals and outputting the differential signals.
The data receiving unit is used for receiving the 8 paths of differential signals, and the 8 paths of differential signals are converted into 4 paths of original signals through an internal differential receiving circuit, namely frame synchronization signals, pixel synchronization signals, data transmission clock signals and 1 path of original image data signals, which are used by the data preprocessing and storage unit.
The data preprocessing and storing unit is internally provided with an FPGA register, and 2 random memories with read/write enable, read/write clock and storage address number which are the same as the pixel number contained in an image frame output by the system linear array detector are set through parameter setting, wherein one random memory is used for storing a laser irradiation imaging image data frame group value called RAM001, and the other random memory is used for storing a group value obtained by subtracting a laser irradiation image data frame from a non-laser irradiation image data frame called RAM 002; the 2 random access memories complete the reading/writing of the image data through the reading/writing enable signal and the reading/writing clock.
In addition, the invention also provides a method for receiving the laser echo signal of the linear array anti-sniper detection system, which is implemented based on the device for receiving the laser echo signal of the linear array anti-sniper detection system, and comprises the following steps:
step 1: designing a cache;
calling FPGA register resources in a data preprocessing and storage unit, and setting 2 random memories with read/write enable, read/write clock and storage address number which are the same as the number of pixels contained in an image frame output by a system linear array detector through parameter setting, wherein one random memory is used for storing a laser irradiation imaging image data frame group value called RAM001, and the other random memory is used for storing a group value called RAM002 after the subtraction of a laser irradiation image data frame and a non-laser irradiation image data frame; the 2 random access memories complete the reading/writing of the image data through a reading/writing enabling signal and a reading/writing clock;
step 2: differential conversion of original signals of clock and data;
the data differential unit and the data acquisition device are designed and stacked; the data differential unit converts the original synchronous signal, the original clock signal and the original image data signal output by the data acquisition device into differential signals and transmits the differential signals to the data receiving unit. (ii) a
And step 3: converting the differential signal into a clock and data original signal;
the data receiving unit receives the differential signal and converts the differential signal into an original synchronous signal, an original clock signal and an original image data signal which are output by the data acquisition device and are used by the data preprocessing and storage unit;
and 4, step 4: preprocessing calculation and control;
the data preprocessing and storage unit carries out calculation preprocessing on the received original image data signals according to the original synchronous signals and the original clock signals, and then stores the original image data signals in a register inside the data preprocessing and storage unit for a subsequent signal processing module to use.
Wherein the original synchronization signal comprises: a frame synchronization signal and a pixel synchronization signal; the original clock signal comprises a data transfer clock signal.
In step 2, the data difference unit performs difference operation on the frame synchronization signal, the pixel synchronization signal, the data transmission clock signal and the original image data signal to generate 8 paths of difference signals and outputs the difference signals.
In step 3, the data receiving unit receives the 8 paths of differential signals, and converts the 8 paths of differential signals into 4 paths of original signals, namely, a frame synchronization signal, a pixel synchronization signal, a data transmission clock signal and 1 path of original image data signal, through an internal differential receiving circuit, for use by the data preprocessing and storage unit.
In step 4, the original image data signals received by the data preprocessing and storage unit start to work according to 2 preset RAMs of the original image data signals after the original image data signals and the original clock signals are processed, the I/O pins of the FPGA detect the frame synchronization signals, and the number of times is counted for each detected rising edge of the frame synchronization signals;
when the count value is 2n, n is the count value, which indicates that 1 frame of image data needs to be received by laser irradiation, and the RAM001 write enable is effective; when the RAM001 detects the rising edge of the synchronous signal of 1 pixel, the RAM indicates that 1 pixel in the received frame needs to be received, the address of the internal register is increased by 1, and 14bit data in the pixel is written into the corresponding address register according to the data transmission clock signal until all the pixels are received, which indicates that the frame receiving of 1 frame data is finished;
when the count value is (2n-1), n is a count value indicating that 1 frame of image data without laser irradiation needs to be received, and is stored in the RAM002 after being subjected to data processing with the image data frame with laser irradiation; therefore, the read enable of the RAM001 and the write enable of the RAM002 are simultaneously enabled, that is, the laser irradiation image data frame is read out from the RAM001, and is subtracted from the received laser irradiation-free image data frame, and after the absolute value of the obtained data value is obtained, the absolute value is written into the RAM002 according to the corresponding address register for the subsequent data processor to use; that is, when the rising edge of the synchronous signal of 1 pixel is detected, the address of the internal registers of the RAM001 and the RAM002 are simultaneously increased by 1, 1 pixel value of the image data frame irradiated by laser is read out from the corresponding address of the RAM001, the difference is subtracted from the 1 pixel value in the image data frame without laser irradiation received in the same period, the absolute value is obtained, and 14bit data is written into the corresponding address register in the RAM002 by a data transmission clock until all the pixels are received, which indicates that the receiving work of the data receiving device is finished.
(III) advantageous effects
Compared with the prior art, the invention has the following beneficial effects:
(1) the device of the invention consists of a data difference unit, a data receiving unit and a data preprocessing and storing unit. Each unit has small volume and light weight, and can be split and used according to functions. The small divided space of the system can be fully utilized after the disassembly, and the installation is flexible. The problem of in the mode one, the structure installation inflexibility that laser echo signal receiving module inseparability caused is solved. Meanwhile, the failure troubleshooting of the system laser echo signal receiving module is facilitated, and the problem of difficulty in troubleshooting is solved.
(2) The invention solves the problems of a large number of interface lines and a large size of an interface connector caused by data parallel transmission and reception. The original system laser echo signal receiving module needs 3 paths of external synchronous clock signals and 1 path of 14bit data signals for data transmission, and the total number of the signals is 3+ 14-17 paths of signals, so that an 18-core connector is needed, if the connector is arranged in double rows according to the pin pitch of 1.27mm, the length of the connector is 18/2 × 1.27-11.43 mm, and the size of the connector is about 15mm by adding an external insulating component; the data receiving device and the data receiving method receive data sent by a data acquisition device in a serial mode, and transmit 3 original external synchronous clock signals and 1 original data signal after difference, only 6 clock difference signals (clock 1+, clock 1-; clock 2+, clock 2-; clock 3+, clock 3-) and 2 data difference signals (data +, data-) are needed, and only one 8-core connector is needed for 6+ 2-8 difference signals in total, if the two-row arrangement is carried out according to the pin pitch of 1.27mm, the length of the connector is 8/2-1.27-5.08 mm, and the size is about 7.0mm by adding an external insulating component. The occupied space position is half of the original space position. Thereby reducing the PCB circuit board size.
(4) The invention converts the signal to be transmitted into the differential signal to transmit the signal, and can reduce the clock signal delay phenomenon and the data transmission error code, misconnection and misconnection phenomenon caused by the impedance of the cable.
Drawings
Fig. 1 is a schematic diagram of a laser echo signal receiving module.
FIG. 2 is a schematic diagram of the operation of the data receiving apparatus
Fig. 3 is a timing diagram of the operation of the data receiving device.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
In order to solve the problems in the prior art, the invention provides a laser echo signal receiving device of a linear array anti-sniper detection system, as shown in fig. 1, the laser echo signal receiving device of the linear array anti-sniper detection system comprises: the data acquisition device and the data receiving device; wherein the data receiving apparatus includes: the data processing device comprises a data difference unit, a data receiving unit and a data preprocessing and storing unit;
the data differential unit is stacked with the data acquisition device and used for converting original synchronous signals, original clock signals and original image data signals output by the data acquisition device into differential signals and transmitting the differential signals to the data receiving unit through a cable;
the data receiving unit is used for receiving the differential signals through a cable connected with the data differential unit, converting the differential signals into original synchronous signals, original clock signals and original image data signals output by the data acquisition device, and supplying the original synchronous signals, the original clock signals and the original image data signals to the data preprocessing and storage unit;
the data preprocessing and storage unit is used for carrying out calculation preprocessing on the received original image data signals according to the original synchronous signals and the original clock signals, and then storing the original image data signals in a register inside the data preprocessing and storage unit for a subsequent signal processing module to use.
Wherein the original synchronization signal comprises: a frame synchronization signal and a pixel synchronization signal; the original clock signal comprises a data transfer clock signal.
The data differential unit is used for carrying out differential operation on the frame synchronization signal, the pixel synchronization signal, the data transmission clock signal and the original image data signal, generating 8 paths of differential signals and outputting the differential signals.
The data receiving unit is used for receiving the 8 paths of differential signals, and the 8 paths of differential signals are converted into 4 paths of original signals through an internal differential receiving circuit, namely frame synchronization signals, pixel synchronization signals, data transmission clock signals and 1 path of original image data signals, which are used by the data preprocessing and storage unit.
The data preprocessing and storing unit is internally provided with an FPGA register, and 2 random memories with read/write enable, read/write clock and storage address number which are the same as the pixel number contained in an image frame output by the system linear array detector are set through parameter setting, wherein one random memory is used for storing a laser irradiation imaging image data frame group value called RAM001, and the other random memory is used for storing a group value obtained by subtracting a laser irradiation image data frame from a non-laser irradiation image data frame called RAM 002; the 2 random access memories complete the reading/writing of the image data through the reading/writing enable signal and the reading/writing clock.
In addition, the invention also provides a method for receiving the laser echo signal of the linear array anti-sniper detection system, which is implemented based on the device for receiving the laser echo signal of the linear array anti-sniper detection system, and comprises the following steps:
step 1: designing a cache;
calling FPGA register resources in a data preprocessing and storage unit, and setting 2 random memories with read/write enable, read/write clock and storage address number which are the same as the number of pixels contained in an image frame output by a system linear array detector through parameter setting, wherein one random memory is used for storing a laser irradiation imaging image data frame group value called RAM001, and the other random memory is used for storing a group value called RAM002 after the subtraction of a laser irradiation image data frame and a non-laser irradiation image data frame; the 2 random access memories complete the reading/writing of the image data through a reading/writing enabling signal and a reading/writing clock;
step 2: differential conversion of original signals of clock and data;
the data differential unit and the data acquisition device are designed and stacked; the data differential unit converts the original synchronous signal, the original clock signal and the original image data signal output by the data acquisition device into differential signals and transmits the differential signals to the data receiving unit through a cable. (ii) a
And step 3: converting the differential signal into a clock and data original signal;
the data receiving unit receives the differential signal through a connected cable, and converts the differential signal into an original synchronous signal, an original clock signal and an original image data signal output by the data acquisition device for use by the data preprocessing and storage unit;
and 4, step 4: preprocessing calculation and control;
the data preprocessing and storage unit carries out calculation preprocessing on the received original image data signals according to the original synchronous signals and the original clock signals, and then stores the original image data signals in a register inside the data preprocessing and storage unit for a subsequent signal processing module to use.
Wherein the original synchronization signal comprises: a frame synchronization signal and a pixel synchronization signal; the original clock signal comprises a data transfer clock signal.
In step 2, the data difference unit performs difference operation on the frame synchronization signal, the pixel synchronization signal, the data transmission clock signal and the original image data signal to generate 8 paths of difference signals and outputs the difference signals.
In step 3, the data receiving unit receives the 8 paths of differential signals, and converts the 8 paths of differential signals into 4 paths of original signals, namely, a frame synchronization signal, a pixel synchronization signal, a data transmission clock signal and 1 path of original image data signal, through an internal differential receiving circuit, for use by the data preprocessing and storage unit.
In step 4, the original image data signals received by the data preprocessing and storage unit start to work according to 2 preset RAMs of the original image data signals after the original image data signals and the original clock signals are processed, the I/O pins of the FPGA detect the frame synchronization signals, and the number of times is counted for each detected rising edge of the frame synchronization signals;
when the count value is 2n, n is the count value, which indicates that 1 frame of image data needs to be received by laser irradiation, and the RAM001 write enable is effective; when the RAM001 detects the rising edge of the synchronous signal of 1 pixel, the RAM indicates that 1 pixel in the received frame needs to be received, the address of the internal register is increased by 1, and 14bit data in the pixel is written into the corresponding address register according to the data transmission clock signal until all the pixels are received, which indicates that the frame receiving of 1 frame data is finished;
when the count value is (2n-1), n is a count value indicating that 1 frame of image data without laser irradiation needs to be received, and is stored in the RAM002 after being subjected to data processing with the image data frame with laser irradiation; therefore, the read enable of the RAM001 and the write enable of the RAM002 are simultaneously enabled, that is, the laser irradiation image data frame is read out from the RAM001, and is subtracted from the received laser irradiation-free image data frame, and after the absolute value of the obtained data value is obtained, the absolute value is written into the RAM002 according to the corresponding address register for the subsequent data processor to use; that is, when the rising edge of the synchronous signal of 1 pixel is detected, the address of the internal registers of the RAM001 and the RAM002 are simultaneously increased by 1, 1 pixel value of the image data frame irradiated by laser is read out from the corresponding address of the RAM001, the difference is subtracted from the 1 pixel value in the image data frame without laser irradiation received in the same period, the absolute value is obtained, and 14bit data is written into the corresponding address register in the RAM002 by a data transmission clock until all the pixels are received, which indicates that the receiving work of the data receiving device is finished.
Example 1
As shown in fig. 1, the laser echo signal receiving device of the linear array anti-sniper detection system in this embodiment includes: a data acquisition device 1 and a data receiving device 2. The preferred embodiment of the data receiving device of the present invention comprises a data differentiating unit 01, a data receiving unit 02, and a data preprocessing and storing unit 03.
The data receiving apparatus 2 is divided into two major functional groups, a signal differential function and a differential signal receiving function, according to functional division. In order to complete corresponding functions, the data differential unit 01 in the data receiving device 2 and the data acquisition device 1 are stacked and installed to form a group, and are installed behind an optical component in the laser echo receiving module to complete laser echo signal data acquisition and transmission. The data receiving unit 02 and the data preprocessing and storage unit 03 in the data receiving device 2 are stacked and mounted to form another group, and the laser echo signal data receiving, preprocessing calculation and caching are completed. The two functional groups are connected through a transmission cable.
In the diagram shown in fig. 2, the data acquisition device 1 outputs 3 internal working timing signals shown in fig. 3, such as a frame synchronization signal, a pixel synchronization signal, a data transmission clock, and the like, and 1 image data signal according to the linear array detector driving timing. The data receiving device 2 detects a frame synchronization signal through an I/O pin of an internal FPGA, and the frame synchronization signal is used as a synchronization signal for controlling the on and off of the synchronous laser, so that the linear array detector in the data acquisition device 1 can acquire a laser irradiation image and a laser irradiation-free image, 2 groups of image signals are converted into processable digital quantity, and the subsequent transmission and processing are facilitated.
The steps of receiving the laser echo signal data by the data receiving device 2 are as follows:
step 1: and (4) designing image data cache.
The image data buffer design is completed by using the FPGA in the data preprocessing and storage unit 03 shown in fig. 2. And (3) calling register resources in the FPGA, and setting 2 Random Access Memories (RAMs) with read/write enable, read/write clocks and the same storage address number as the pixel number contained in an image frame output by the system linear array detector through parameter setting. One for storing the laser shot image data frame set value is referred to as RAM 001. The other is used for storing the numerical value of the subtraction of the laser irradiation image data frame and the non-laser irradiation image data frame, and is called RAM 002. The post-stage data processor completes the read/write of the image data in the 2 random access memories through the read/write control signal.
Step 2: and (4) carrying out differential conversion on the clock and the image data original signals.
The data acquisition apparatus 1 shown in fig. 2 outputs 3 original external synchronization clock signals: a frame synchronization signal, a pixel synchronization signal, a data transmission clock, and a 1-path image data signal.
The data differential unit 01 is stacked and inserted on 2 single-row jacks of the data acquisition device 1, wherein the single-row jacks are 1 × 2 and 1.27mm in specification, and 2 single-row pins of 1 × 2 and 1.27mm in specification are stacked and inserted, and 4 paths of original signals are inserted into a differential conversion circuit of the data differential unit 01. The data differential unit 01 outputs 8 paths of differential signals and transmits the signals to the data receiving unit 02 through an 8-core cable.
And step 3: and converting the clock and data differential signals into original signals.
The data receiving unit 02 shown in fig. 2 receives the 8 paths of differential signals output by the data differential unit 01, and converts the signals into 4 paths of original signals, namely, a frame synchronization signal, a pixel synchronization signal, a data transmission clock, and a 1 path of image data signals, through the differential receiving circuit in the unit. For use by the data preprocessing and storage unit.
And step 3: preprocessing calculation and data storage.
According to the operation timing shown in fig. 3, 2 RAMs designed in the FPGA of the data preprocessing and storage unit 03 shown in fig. 2 start to operate, the I/O pin of the FPGA detects the frame synchronization signal, and the count is performed 1 time each time the rising edge of the frame synchronization signal is detected.
When the count value is 2n (n is the count value), it indicates that 1 frame of laser-irradiated image data needs to be received, and the RAM001 write enable is enabled. When the RAM001 detects the rising edge of the synchronous signal of 1 pixel, the RAM indicates that 1 pixel in the received frame needs to be received, the address of the internal register is increased by 1, and 14bit data in the pixel is written into the corresponding address register according to the data transmission clock until all the pixels are received, which indicates that the receiving of the data frame of 1 frame is finished.
When the count value is (2n-1) (n is a count value), it indicates that 1 frame of the non-laser-irradiated image data needs to be received, and the received image data is processed with the laser-irradiated image data frame data and then stored in the RAM 002. Therefore, the read enable of the RAM001 and the write enable of the RAM002 are simultaneously enabled, that is, the laser-irradiated image data frame is read out from the RAM001, subtracted from the received non-laser-irradiated image data frame, and the absolute value of the obtained data value is written into the RAM002 according to the corresponding address register for use by the subsequent data processor. That is, when the rising edge of the synchronous signal of 1 pixel is detected, the address of the internal registers of the RAM001 and the RAM002 are simultaneously increased by 1, 1 pixel value of the image data frame irradiated by laser is read out from the corresponding address of the RAM001, the difference is subtracted from the 1 pixel value in the image data frame without laser irradiation received in the same period, the absolute value is obtained, and 14bit data is written into the corresponding address register in the RAM002 by a data transmission clock until all the pixels are received, which indicates that the receiving work of the data receiving device is finished.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. The utility model provides an anti-sniper detection system laser echo signal receiving arrangement of linear array, its characterized in that, anti-sniper detection system laser echo signal receiving arrangement of linear array includes: the data acquisition device and the data receiving device; wherein the data receiving apparatus includes: the data processing device comprises a data difference unit, a data receiving unit and a data preprocessing and storing unit;
the data differential unit is stacked with the data acquisition device and used for converting an original synchronous signal, an original clock signal and an original image data signal output by the data acquisition device into differential signals and transmitting the differential signals to the data receiving unit;
the data receiving unit is used for receiving the differential signals and converting the differential signals into original synchronous signals, original clock signals and original image data signals output by the data acquisition device for use by the data preprocessing and storage unit;
the data preprocessing and storage unit is used for carrying out calculation preprocessing on the received original image data signals according to the original synchronous signals and the original clock signals, and then storing the original image data signals in a register inside the data preprocessing and storage unit for a subsequent signal processing module to use.
2. The linear array anti-sniper detection system laser echo signal receiving device of claim 1, wherein the original synchronization signal comprises: a frame synchronization signal and a pixel synchronization signal; the original clock signal comprises a data transfer clock signal.
3. The laser echo signal receiving device of the linear array anti-sniper detection system as claimed in claim 2, wherein the data differencing unit is configured to perform differencing operation on the frame synchronization signal, the pixel synchronization signal, the data transmission clock signal, and the original image data signal, generate 8 paths of differential signals, and output the differential signals.
4. The laser echo signal receiving device of the linear array anti-sniper detection system as claimed in claim 3, wherein the data receiving unit is configured to receive the 8 paths of differential signals, and convert the 8 paths of differential signals into 4 paths of original signals, that is, a frame synchronization signal, a pixel synchronization signal, a data transmission clock signal, and 1 path of original image data signal, through an internal differential receiving circuit, for use by the data preprocessing and storage unit.
5. The laser echo signal receiving device of the linear array anti-sniper detection system as claimed in claim 4, wherein an FPGA register is arranged in the data preprocessing and storage unit, and 2 random memories having read/write enable, read/write clock, and storage address number the same as the number of pixels included in the image frame output by the system linear array detector are arranged by parameter setting, one of the random memories is used for storing a laser irradiation imaging image data frame group value called RAM001, and the other random memory is used for storing a number group value obtained by subtracting the laser irradiation image data frame from the non-laser irradiation image data frame called RAM 002; the 2 random access memories complete the reading/writing of the image data through the reading/writing enable signal and the reading/writing clock.
6. A method for receiving laser echo signals of a linear array anti-sniper detection system is characterized by being implemented on the basis of the device for receiving the laser echo signals of the linear array anti-sniper detection system of claim 1, and comprising the following steps of:
step 1: designing a cache;
calling FPGA register resources in a data preprocessing and storage unit, and setting 2 random memories with read/write enable, read/write clock and storage address number which are the same as the number of pixels contained in an image frame output by a system linear array detector through parameter setting, wherein one random memory is used for storing a laser irradiation imaging image data frame group value called RAM001, and the other random memory is used for storing a group value called RAM002 after the subtraction of a laser irradiation image data frame and a non-laser irradiation image data frame; the 2 random access memories complete the reading/writing of the image data through a reading/writing enabling signal and a reading/writing clock;
step 2: differential conversion of original signals of clock and data;
the data differential unit and the data acquisition device are designed and stacked; the data differential unit converts the original synchronous signal, the original clock signal and the original image data signal output by the data acquisition device into differential signals and transmits the differential signals to the data receiving unit. (ii) a
And step 3: converting the differential signal into a clock and data original signal;
the data receiving unit receives the differential signal and converts the differential signal into an original synchronous signal, an original clock signal and an original image data signal which are output by the data acquisition device and are used by the data preprocessing and storage unit;
and 4, step 4: preprocessing calculation and control;
the data preprocessing and storage unit carries out calculation preprocessing on the received original image data signals according to the original synchronous signals and the original clock signals, and then stores the original image data signals in a register inside the data preprocessing and storage unit for a subsequent signal processing module to use.
7. The linear array anti-sniper detection system laser echo signal receiving method as claimed in claim 6, wherein said original synchronization signal includes: a frame synchronization signal and a pixel synchronization signal; the original clock signal comprises a data transfer clock signal.
8. The linear array anti-sniper detection system laser echo signal receiving method as claimed in claim 7, wherein in step 2, said data differencing unit performs differencing operation on said frame synchronization signal and said pixel synchronization signal, said data transmission clock signal and said original image data signal, generates 8 paths of differential signals and outputs them.
9. The linear array anti-sniper detection system laser echo signal receiving method as claimed in claim 8, wherein in step 3, the data receiving unit receives the 8 paths of differential signals, and converts the 8 paths of differential signals into 4 paths of original signals, namely, a frame synchronization signal, a pixel synchronization signal, a data transmission clock signal and 1 path of original image data signal, through an internal differential receiving circuit, for use by the data preprocessing and storage unit.
10. The linear array anti-sniper detection system laser echo signal receiving method of claim 9, wherein in step 4, the data preprocessing and storage unit receives original image data signals, and after each original synchronization signal and original clock signal, its preset 2 RAMs start to operate, and the I/O pin of the FPGA detects a frame synchronization signal, and counts 1 time each time the rising edge of the frame synchronization signal is detected;
when the count value is 2n, n is the count value, which indicates that 1 frame of image data needs to be received by laser irradiation, and the RAM001 write enable is effective; when the RAM001 detects the rising edge of the synchronous signal of 1 pixel, the RAM indicates that 1 pixel in the received frame needs to be received, the address of the internal register is increased by 1, and 14bit data in the pixel is written into the corresponding address register according to the data transmission clock signal until all the pixels are received, which indicates that the frame receiving of 1 frame data is finished;
when the count value is (2n-1), n is a count value indicating that 1 frame of image data without laser irradiation needs to be received, and is stored in the RAM002 after being subjected to data processing with the image data frame with laser irradiation; therefore, the read enable of the RAM001 and the write enable of the RAM002 are simultaneously enabled, that is, the laser irradiation image data frame is read out from the RAM001, and is subtracted from the received laser irradiation-free image data frame, and after the absolute value of the obtained data value is obtained, the absolute value is written into the RAM002 according to the corresponding address register for the subsequent data processor to use; that is, when the rising edge of the synchronous signal of 1 pixel is detected, the address of the internal registers of the RAM001 and the RAM002 are simultaneously increased by 1, 1 pixel value of the image data frame irradiated by laser is read out from the corresponding address of the RAM001, the difference is subtracted from the 1 pixel value in the image data frame without laser irradiation received in the same period, the absolute value is obtained, and 14bit data is written into the corresponding address register in the RAM002 by a data transmission clock until all the pixels are received, which indicates that the receiving work of the data receiving device is finished.
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