CN113742003A - Program code execution method and device based on FPGA chip - Google Patents
Program code execution method and device based on FPGA chip Download PDFInfo
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- CN113742003A CN113742003A CN202111083820.8A CN202111083820A CN113742003A CN 113742003 A CN113742003 A CN 113742003A CN 202111083820 A CN202111083820 A CN 202111083820A CN 113742003 A CN113742003 A CN 113742003A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a program code execution method and device based on an FPGA chip, wherein the method comprises the following steps: the equipment detects a control instruction, and the control instruction is used for indicating the equipment to call a program code associated with the control instruction; the program code is used for compressing the acquired ultra-high-definition video by the equipment, or the program code is used for decompressing the compressed ultra-high-definition video by the equipment; responding to the control instruction, calling a program code associated with the control instruction by the equipment, and loading the program code into the FPGA chip; the device executes the program code through the FPGA chip to compress the acquired ultra high definition video, or the device executes the program code through the FPGA chip to decompress the compressed ultra high definition video. By adopting the invention, the equipment can be used as equipment for compressing the acquired ultra-high-definition video and can also be used as equipment for decompressing the compressed ultra-high-definition video, thereby being very convenient and fast and having higher user experience.
Description
Technical Field
The invention relates to the technical field of video processing, in particular to a program code execution method and device based on an FPGA chip.
Background
At present, the industry generally considers that after a coding algorithm is burned into an ASIC chip, the obtained high definition video is compressed by the ASIC chip running with the coding algorithm, or alternatively, a decoding algorithm is burned into the ASIC chip, and the compressed high definition video code stream data is decompressed by the ASIC chip running with the decoding algorithm; then, the above mentioned ASIC chip has a single function, and can only use the compression of the high definition video, or can only be used for the decompression operation of the compressed high definition video code stream data, so that the user experience is low.
Disclosure of Invention
In order to solve the technical problem, the invention provides a program code execution method and device based on an FPGA chip.
In order to solve the above technical problem, the present invention provides a program code execution method based on an FPGA chip, including:
the method comprises the steps that a device detects a control instruction, wherein the control instruction is used for instructing the device to call program codes related to the control instruction; the program code is used for the device to compress the acquired ultra high definition video, or the program code is used for the device to decompress the compressed ultra high definition video;
responding to the control instruction, the equipment calls a program code associated with the control instruction and loads the program code into an FPGA chip;
the device executes the program code through the FPGA chip to compress the acquired ultra high definition video, or the device executes the program code through the FPGA chip to decompress the compressed ultra high definition video.
In order to solve the above technical problem, the present invention provides a program code execution device based on an FPGA chip, including: the device comprises a processor and an FPGA chip, wherein the processor is used for detecting a control instruction, and the control instruction is used for instructing the device to call a program code associated with the control instruction; the program code is used for the equipment to compress the acquired ultra high definition video or decompress the compressed ultra high definition video; the FPGA chip is used for executing the program code to compress the uncompressed ultra high definition video, or the FPGA chip executes the program code to decompress the compressed ultra high definition video.
After the scheme is adopted, the acquired ultra-high-definition video is compressed or the compressed ultra-high-definition video is decompressed by executing different program codes through the FPGA chip, so that the equipment can be used as equipment for compressing the acquired ultra-high-definition video and can also be used as equipment for decompressing the compressed ultra-high-definition video, and the method is very convenient and fast and has high user experience.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart of a method for executing program codes based on an FPGA chip provided by the invention;
fig. 2-6 are schematic structural diagrams of the program code execution device based on the FPGA chip provided by the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Referring to fig. 1, which is a schematic flow chart of a method for executing a program code based on an FPGA chip according to the present invention, as shown in fig. 1,
s101, the equipment detects a control instruction.
The device detects the control command, which may include but is not limited to the following:
mode 1:
when a user dials a dial switch of the equipment to a first side, the equipment detects that the level of a preset I/O interface of a micro control unit of the equipment is '0', and a program code associated with the level of the '0' I/O interface is used for compressing the acquired ultra high definition video by the equipment; program code associated with said "0" I/O interface level comprising: a compression algorithm for compressing the acquired ultra high definition video; the preset I/O interface is any one interface of the micro control unit; alternatively, the first and second electrodes may be,
when a user dials a dial switch of the equipment to a second side, the equipment detects that the level of a preset I/O interface of the equipment is '1', and program codes related to the level of the '1' I/O interface are used for decompressing compressed ultra-high-definition video by the equipment; the program code associated with the "1" I/O interface level comprises: a decompression algorithm for decompressing compressed ultra high definition video. Wherein the first side comprises: left, right, upper or lower; the second side includes: left, right, upper or lower.
It should be noted that the position of the first side corresponds to or is symmetrical to the position of the second side; that is, when the first side is a left side, the second side is a right side, and when the first side is a right side, the second side is a left side; when the first side is the upper side, the second side is the lower side; when the first side is a lower side, the second side is an upper side; when the first side is the left upper side, the second side is the right lower side; when the first side is the left lower side, the second side is the right upper side. In particular, the method comprises the following steps of,
it should be noted that, when the dial switch of the device is dialed to the left, the device detects that the level of the preset I/O interface of the device is "1", and when the dial switch of the device is dialed to the left, the device detects that the level of the preset I/O interface of the device is "0"; and the program code associated with the level of the "0" I/O interface is used for the device to compress the acquired ultra high definition video, and the program code associated with the level of the "1" I/O interface is used for the device to decompress the compressed ultra high definition video.
It should be noted that, when the dial switch of the device is dialed to the upper side, the device detects that the level of the preset I/O interface of the device is "0", and when the dial switch of the device is dialed to the lower side, the device detects that the level of the preset I/O interface of the device is "1", and the program code associated with the level of the "1" I/O interface is used by the device to compress the acquired ultra high definition video, and the program code associated with the level of the "1" I/O interface is used by the device to decompress the compressed ultra high definition video.
It should be noted that, when the dial switch of the device is dialed to the lower side, the device detects that the level of the preset I/O interface of the device is "0", and when the dial switch of the device is dialed to the upper side, the device detects that the level of the preset I/O interface of the device is "1"; and the program code associated with the level of the '0' I/O interface is used for compressing the acquired ultra high definition video by the equipment, and the program code associated with the level of the '1' I/O interface is used for decompressing the compressed ultra high definition video by the equipment.
Mode 2:
the device detects a first control instruction sent by the control device and received through the control interface, wherein the first control instruction is used for indicating that: the equipment is sending equipment, and the equipment calls a program code associated with the first control instruction to compress the acquired ultra high definition video; alternatively, the first and second electrodes may be,
the device detects a second control instruction sent by the control device and received through the control interface, wherein the second control instruction is used for indicating that: the device is a receiving device, and the device calls the program code associated with the second control instruction to decompress the compressed ultra high definition video; wherein the first control instruction is different from the second control instruction. The control devices may include, but are not limited to: a mouse or keyboard;
or the device detects a second control instruction sent by control software of the control device and received by the control interface;
wherein the control interface may include, but is not limited to: one or more of a Type-C interface, a USB interface, an RS232 interface, an SPI interface, a network port or an I2C interface.
In an embodiment of the present invention, the control instruction is used to instruct the device to call a program code associated with the control instruction. The program code is used for the device to compress the acquired ultra high definition video, or the program code is used for the device to decompress the compressed ultra high definition video;
among others, ultra high definition video may include, but is not limited to: ultra high definition video in RGB format or YUV format, or ultra high definition video in RGB format; the high definition video data may further include, but is not limited to, the following features: the resolution may be: 1080P, 4K or 8K resolution; the frame rate may be 30FPS, 60FPS, 100FPS, or 120 FPS; high Dynamic Range hdr (high Dynamic Range imaging).
Before the device detects the control instruction, the method may further include:
the equipment acquires a control instruction through an input interface; wherein the input interface may include, but is not limited to: one or more of an HDMI interface, a VGA interface, a USB interface, a Type-C interface or a DVI interface.
The program code is used for the apparatus to compress the acquired ultra high definition video, for example, the program code for compressing the ultra high definition video may include but is not limited to: medium compression encoding algorithm codes and light compression encoding algorithm codes.
Wherein, the medium compression coding algorithm comprises: an encoding algorithm based on an intra block copy prediction mode, an encoding algorithm based on a wide-angle intra prediction mode or an H.264 encoding algorithm; HEVC-SCC coding algorithm;
the light compression coding algorithm comprises the following steps: a coding algorithm based on wavelet transform, a coding algorithm based on short-time Fourier transform and a coding algorithm based on discrete cosine transform; the wavelet transform-based coding algorithm comprises: JPEG-XS encoding algorithm, JPEG-LS encoding algorithm, or VDC-M encoding algorithm.
Program code for decompressing ultra high definition video may include, but is not limited to: a medium compression decoding algorithm code and a light compression decoding algorithm code.
Wherein, the compression decoding algorithm comprises: a decoding algorithm based on an intra block copy prediction mode, a decoding algorithm based on a wide-angle intra prediction mode or an H.264 decoding algorithm; HEVC-SCC decoding algorithm;
the light compression decoding algorithm includes: a decoding algorithm based on wavelet transform, a decoding algorithm based on short-time Fourier transform and a decoding algorithm based on discrete cosine transform; the wavelet transform-based decoding algorithm comprises: JPEG-XS decoding algorithm, JPEG-LS decoding algorithm or VDC-M decoding algorithm.
And S102, responding to the control instruction, calling a program code associated with the control instruction by the equipment, and loading the program code into the FPGA chip.
In this embodiment of the present invention, in response to the control instruction, the device invokes the program code associated with the control instruction, which may include but is not limited to:
in response to the control instruction, the device calls, by means of a Micro Control Unit (MCU), program code associated with the control instruction from a memory integrated in the device; the memory may include, but is not limited to: cache, FLASH memory or memory; alternatively, the first and second electrodes may be,
in response to the control instruction, the device invokes program code associated with the control instruction from a cloud database associated with the device. (ii) a The cloud database comprises: an open source program code database.
In response to the control instruction, the device calls a program code associated with the control instruction and loads the program code into the FPGA chip, which may include, but is not limited to, the following steps:
and responding to the control instruction, calling a program code associated with the control instruction by the device through an internally integrated micro control unit, and loading the program code into the FPGA chip through an SPI (serial peripheral interface) of the micro control unit.
When the memory comprises: the FLASH memory, the control instruction includes: the device comprises a first control instruction and a second control instruction, wherein the first control instruction is used for instructing the device to call the program code associated with the first control instruction to compress the acquired ultra high definition video, and the second control instruction is used for instructing the device to call the program code associated with the second control instruction to decompress the compressed ultra high definition video;
in response to the control instruction, the device invokes the program code associated with the control instruction from a memory integrated in the device, which may include, but is not limited to, the following processes:
in response to the first control instruction, the device calls program codes for compressing the acquired ultra-high-definition video from a first storage area in a FLASH memory integrated in the device; alternatively, the first and second electrodes may be,
in response to the second control instruction, the device calls program code for decompressing the compressed ultra high definition video from a second memory area in a FLASH memory integrated in the device.
And S103, the equipment executes the program codes through the FPGA chip to compress the acquired ultra-high-definition video, or the equipment executes the program codes through the FPGA chip to decompress the compressed ultra-high-definition video.
Specifically, the device executes the program code through the FPGA chip to compress the acquired ultra high definition video, which may include but is not limited to:
the equipment executes the program code through the FPGA chip to compress the acquired ultra-high-definition video to obtain code stream data;
the code stream data is used for packaging equipment through a communication protocol to obtain a data packet; the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol; the program code includes: and a compression algorithm for compressing the ultra high definition video obtained as described above.
Specifically, the device decompresses the compressed ultra-high-definition video by executing the program code through the FPGA chip, and the decompression may include, but is not limited to:
the device decompresses the code stream data by executing the program code through the FPGA chip to obtain the ultra-high definition video;
wherein the compressed ultra high definition video comprises: code stream data; the program code includes: a decompression algorithm for decompressing the code stream data.
The device executes the program code through the FPGA chip to compress the uncompressed ultra high definition video, and after code stream data is obtained, the device further comprises:
the equipment encapsulates the code stream data into a data packet through a communication protocol;
the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol; the data packet includes: UDP packets, TCP packets, or custom packets. More specifically, the present invention is to provide a novel,
the equipment encapsulates the code stream data into UDP data packets through a UDP communication protocol; that is, the equipment encapsulates the UDP data head, the UDP data tail and the code stream data into a UDP data packet; the UDP data head and the UDP data tail both comprise control information such as a destination address, a source address, a port number, a marking bit and the like of the ultra-high definition video; alternatively, the first and second electrodes may be,
the equipment encapsulates the code stream data into a TCP data packet through a TCP communication protocol; that is, the device encapsulates the TCP data header, the TCP data trailer and the code stream data into a TCP data packet; the TCP data head and the TCP data tail comprise control information such as a destination address, a source address, a port number, a marking bit and the like of the ultra-high definition video; alternatively, the first and second electrodes may be,
the equipment encapsulates the code stream data into a custom data packet through a custom communication protocol; that is, the device encapsulates the custom data header, the custom data trailer and the code stream data into a custom data packet; the custom data head and the custom data tail both comprise control information such as a destination address, a source address, a port number, a mark bit and the like of the ultra-high definition video.
After the device encapsulates the code stream data into the data packet through the communication protocol, the method may further include:
the device converts the data packet into an optical signal through the optical module and transmits the optical signal to a preset device, or,
the device converts the data packet into an optical signal through the optical module and sends the optical signal to the switch, wherein the switch is used for forwarding the optical signal to the preset device.
After the device encapsulates the code stream data into a data packet through a communication protocol, the method may further include:
after the device outputs the data packet to the PHY chip through the communication timing interface of the MAC unit, the device outputs the data packet to the RJ-45 interface through the PHY chip, and sends the data packet to a preset device through the RJ-45 interface, or,
after the device outputs the data packet to the PHY chip through the communication time sequence interface of the MAC unit, the data packet is output to the RJ-45 interface through the PHY chip and is sent to the switch through the RJ-45 interface, wherein the switch is used for forwarding the data packet to the preset device; the switch may include: a gigabit switch or a gigabit switch; the switch may also be: a stack switch.
The communication timing interface may include, but is not limited to: one or more of an XFI interface, MII interface, GMII interface, SGMII interface, RGMII interface, XGMII interface, Serdes interface, XAUI interface, or RXAAUI interface.
After the device encapsulates the code stream data into a data packet through a communication protocol, the method may further include:
the device sends the data packet to a preset device through a 5G communication module;
the communication interface of the 5G communication module may include, but is not limited to: a PCIE interface, a gigabit Ethernet interface, a 1G Ethernet interface, a 10G Ethernet interface, a USB3.0 interface, etc. The 5G communication module may be a 5G communication module that encapsulates a plurality of antennas inside by using an aip (antenna in package) technology, and may improve a transmission rate of protocol stream data and reduce transmission delay by using a large-scale Multiple Input Multiple Output (MIMO) technology.
Alternatively, the first and second electrodes may be,
the device sends the data packet to the base station through the 5G communication module, and the base station is used for forwarding the data packet to the preset device.
When the preset device comprises: when the first preset device and the second preset device are used,
the device sends the data packet to the preset device through the 5G communication module, which may include:
the device sends the data packet to a first preset device and a second preset device through a 5G communication module respectively.
When the base station includes: when the first base station and the second base station are in use,
the device sends the data packet to the base station through the 5G communication module, which may include:
the device sends the data packet to the first base station through the 5G communication module, forwards the data packet to the second base station through the first base station, and forwards the data packet to the preset device through the second base station.
After the device encapsulates the code stream data into a data packet through a communication protocol, the device further comprises:
the device sends the data packet to the preset device through the WIFI communication module.
And the device sends the data packet to a preset device through a WIFI communication module. The WIFI module adopts an Orthogonal Frequency Division Multiple Access (OFDMA) technology, and on the other hand, the WIFI module integrates a communication module with a plurality of antennas.
When the preset device comprises: when the first preset device and the second preset device are used,
the device sends the data packet to the preset device through the WIFI communication module, which may include:
the device sends the data packets to the first preset device and the second preset device through the WIFI communication module respectively.
After the device encapsulates the code stream data into the data packet through the communication protocol, the method may further include:
the device sends the data packet to the preset device through the 60G communication module.
When the preset device comprises: when the first preset device and the second preset device are used,
the device sends the data packet to the preset device through the 60G communication module, which may include:
the device respectively sends the data packets to the first preset device and the second preset device through the 60G communication module.
The device decompresses the code stream data by executing the program code through the FPGA chip to obtain the ultra-high definition video, and the method further comprises the following steps:
outputting, by a device, the ultra high definition video to a display device coupled with the device through an output interface; the display device is used for displaying the ultra-high-definition video; the output interface includes: one or more of an HDMI interface, a VGA interface, a USB interface, a Type-C interface or a DVI interface.
The invention provides a program code execution device based on an FPGA chip, which can be used for realizing the program code execution method based on the FPGA chip in the embodiment of figure 1. The apparatus shown in fig. 2 may be used to implement the description in the embodiment of fig. 1.
As shown in fig. 2, the apparatus 20 may include, but is not limited to: input interface 200, memory 201, processor 202, optical module 203, FPGA chip 204.
A processor 202 operable to:
detecting a control instruction, wherein the control instruction is used for instructing the equipment to call program codes associated with the control instruction from a memory 201 through a preset I/O interface of a processor 202; the program code is used for the device 20 to compress the acquired ultra high definition video or decompress the compressed ultra high definition video;
in response to the control instruction, calling a program code associated with the control instruction from the memory 201, and loading the program code into the FPGA chip 204; among them, the memory 201 may include: a FLASH memory;
among other things, the processor 202 may include, but is not limited to: a Micro Control Unit (MCU);
and responding to the control instruction, calling a program code associated with the control instruction, and loading the program code into the FPGA chip through the SPI interface of the processor 202.
in response to said first control instruction, calling program code for compressing the acquired ultra high definition video from a first memory area in a FLASH memory integrated in said device 20; alternatively, the first and second electrodes may be,
in response to said second control instruction, program code for decompressing the compressed ultra high definition video is called from a second memory area in a FLASH memory integrated in said device 20.
the program code is executed to compress the uncompressed ultra high definition video or is operable to execute the program code to decompress the compressed ultra high definition video.
The processor 202 may be specifically configured to:
when a user dials a dial switch of the device 20 to a first side, it is detected that a level of a preset I/O interface of the device 20 is "0", and a program code associated with the level of the I/O interface of "0" is used for compressing the acquired ultra high definition video by the device 20; the "0" level associated program code comprising: a compression algorithm for compressing the obtained ultra high definition video; alternatively, the first and second electrodes may be,
when a user dials a dial switch of the device 20 to a second side, detecting that a level of a preset I/O interface of the device 20 is "1", where a program code associated with the "1" level is used by the device 20 to decompress a compressed ultra high definition video; the "1" level associated program code comprising: a decompression algorithm for decompressing the compressed ultra high definition video; wherein the position of the first side corresponds to or is symmetrical to the position of the second side.
The processor 202 may be further configured to:
detecting a first control instruction sent by the control device and received through the control interface, where the first control instruction is used to instruct the device 20 to call a program code associated with the first control instruction to compress the acquired ultra high definition video; alternatively, the first and second electrodes may be,
detecting a second control instruction sent by the control device and received through the control interface, where the second control instruction is used to instruct the device 20 to call program code associated with the second control instruction to decompress the compressed ultra high definition video; the control apparatus includes: a mouse or keyboard;
wherein the control interface comprises: a USB interface, an RS232 interface, an SPI interface, or an I2C interface.
The processor 202 may be further configured to:
in response to said control instruction, calling the program code associated with said control instruction from a memory integrated in the device 20; alternatively, the first and second electrodes may be,
in response to the control instruction, program code associated with the control instruction is called from a cloud database associated with device 20.
executing a program code for compressing the ultra-high-definition video to compress the acquired ultra-high-definition video to obtain code stream data;
the code stream data is used for packaging the equipment through a communication protocol to obtain a data packet; the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol; the program code includes: a compression algorithm for compressing said obtained ultra high definition video.
The FPGA chip 204 may also be configured to:
executing a program code for decompressing a compressed ultra-high-definition video to decompress the compressed ultra-high-definition video to obtain an ultra-high-definition video;
wherein the compressed ultra high definition video comprises: the code stream data; the program code includes: and the decompression algorithm is used for decompressing the code stream data.
The FPGA chip 204 may also be configured to:
compressing the obtained ultra-high-definition video to obtain code stream data, and then:
packaging the code stream data into a data packet through a communication protocol; the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol; the data packet includes: UDP packets, TCP packets, or custom packets.
An optical module 203 operable to:
converting the data packet into an optical signal and transmitting the optical signal to a preset device, or,
and converting the data packet into an optical signal, and sending the optical signal to a switch, wherein the switch is used for forwarding the optical signal to the preset equipment.
It should be understood that apparatus 20 is only one example provided by embodiments of the present invention and that apparatus 20 may have more or fewer components than shown, may combine two or more components, or may have a different configuration implementation of components.
It is understood that, regarding the specific implementation manner of the functional modules included in the device 20, reference may be made to the foregoing method embodiment shown in fig. 1, and details are not described here again.
Fig. 2 is only for explaining the embodiment of the present invention, and the present invention should not be limited thereto.
The invention provides another program code execution device based on an FPGA chip, which can be used for realizing the program code execution method based on the FPGA chip in the embodiment of FIG. 1. The apparatus shown in fig. 3 may be used to implement the description in the embodiment of fig. 1.
As shown in fig. 3, the device 30 may include, but is not limited to: input interface 300, memory 301, processor 302, electrical module 303, FPGA chip 304.
The specific implementation method or functions of the input interface 300 and the processor 302 can refer to the functions of the processor in fig. 2, and the embodiment of the present invention is not described again.
The specific implementation method or function of the FPGA chip 304 may refer to the function of the FPGA chip in fig. 2, and is not described again in the embodiments of the present invention.
The electrical module 303 may include: PHY chip and RJ-45 interface; wherein, the device 30 is operable to output the data packet to the PHY chip through a communication timing interface of the MAC unit; wherein, communication chronogenesis interface includes: an XFI interface, an MII interface, a GMII interface, an SGMII interface, an RGMII interface, an XGMII interface, a Serdes interface, an XAUI interface, or an RXAUI interface.
The electrical module 303 is configured to:
the received data packet is output to the RJ-45 interface through the PHY chip, and is transmitted to a preset device through the RJ-45 interface, or,
the received data packet is output to the RJ-45 interface through the PHY chip and is sent to the switch through the RJ-45 interface, and the switch is used for forwarding the data packet to preset equipment.
It should be understood that device 30 is only one example provided by embodiments of the present invention, and that device 30 may have more or fewer components than shown, may combine two or more components, or may have a different configuration implementation of components.
It can be understood that, regarding the specific implementation manner of the functional modules included in the device 30, reference may be made to the foregoing method embodiment shown in fig. 1 and the embodiment shown in fig. 2, and details are not described here again.
Fig. 3 is only for explaining the embodiment of the present invention, and the present invention should not be limited thereto.
The invention provides still another program code execution device based on an FPGA chip, which can be used for realizing the program code execution method based on the FPGA chip in the embodiment of FIG. 1. The device shown in fig. 4 may be used to implement the description in the embodiment of fig. 1.
As shown in fig. 4, the device 40 may include, but is not limited to: input interface 400, memory 401, processor 402, WIFI communication module 403, FPGA chip 404.
The specific implementation method or functions of the input interface 400 and the processor 402 can refer to the functions of the processor in fig. 2, and the embodiment of the present invention is not described in detail again.
The specific implementation method or function of the FPGA chip 404 may refer to the function of the FPGA chip in fig. 2, and the embodiment of the present invention is not described again.
A WIFI communication module 403, operable to:
and sending the data packet to preset equipment through the WIFI communication module.
When the preset device comprises: when the first preset device and the second preset device are used,
a WIFI communication module 403, operable to:
and respectively sending the data packets to the first preset device and the second preset device through a WIFI communication module.
The WIFI module adopts an Orthogonal Frequency Division Multiple Access (OFDMA) technology, and on the other hand, the WIFI module integrates a communication module with a plurality of antennas.
It should be understood that device 40 is only one example provided by embodiments of the present invention, and that device 40 may have more or fewer components than shown, may combine two or more components, or may have a different configuration of components to implement.
It can be understood that, regarding the specific implementation manner of the functional modules included in the device 40, reference may be made to the method embodiment shown in fig. 1 and the embodiment shown in fig. 2, which are not described herein again.
Fig. 4 is only for explaining the embodiment of the present invention, and the present invention should not be limited thereto.
The invention provides still another program code execution device based on an FPGA chip, which can be used for realizing the program code execution method based on the FPGA chip in the embodiment of FIG. 1. The apparatus shown in fig. 5 may be used to implement the description in the embodiment of fig. 1.
As shown in fig. 5, the device 50 may include, but is not limited to: input interface 500, memory 501, processor 502, 5G communication module 503, FPGA chip 504.
The specific implementation method or functions of the input interface 500 and the processor 502 may refer to the functions of the processor in fig. 2, and the embodiment of the present invention is not described in detail again.
The specific implementation method or function of the FPGA chip 504 may refer to the function of the FPGA chip in fig. 2, and the embodiment of the present invention is not described again.
A 5G communication module 503, operable to:
sending the data packet to preset equipment; the communication interface of the 5G communication module 503 may include, but is not limited to: a PCIE interface, a gigabit Ethernet interface, a 1G Ethernet interface, a 10G Ethernet interface, a USB3.0 interface, etc. Alternatively, the first and second electrodes may be,
and sending the data packet to a base station, wherein the base station is used for forwarding the data packet to preset equipment.
When the preset device comprises: when the first preset device and the second preset device are used,
and respectively sending the data packet to the first preset device and the second preset device. And the first display equipment connected with the first preset equipment and the second display equipment connected with the second preset equipment can respectively display the ultrahigh-definition videos. Alternatively, the first and second electrodes may be,
and sending the data packet to the first base station, forwarding the data packet to the second base station through the first base station, and forwarding the data packet to preset equipment through the second base station.
It should be understood that device 50 is only one example provided by embodiments of the present invention, and that device 50 may have more or fewer components than shown, may combine two or more components, or may have a different configuration implementation of components.
It can be understood that, regarding the specific implementation manner of the functional modules included in the device 50, reference may be made to the foregoing method embodiment shown in fig. 1 and the embodiment shown in fig. 2, and details are not described here again.
Fig. 5 is only for explaining the embodiment of the present invention, and the present invention should not be limited thereto.
The invention provides still another program code execution device based on an FPGA chip, which can be used for realizing the program code execution method based on the FPGA chip in the embodiment of FIG. 1. The apparatus shown in fig. 6 may be used to implement the description in the embodiment of fig. 1.
As shown in fig. 6, the device 60 may include, but is not limited to: input interface 600, memory 601, processor 602, 5G communication module 603, FPGA chip 604.
The specific implementation method or functions of the input interface 600 and the processor 602 may refer to the functions of the processor in fig. 2, and the embodiment of the present invention is not described in detail again.
The specific implementation method or function of the FPGA chip 604 may refer to the function of the FPGA chip in fig. 2, and the embodiment of the present invention is not described again.
A 5G communication module 603 operable to:
and after the modem modulates the data packet, the modem is used for sending the modulated signal to preset equipment through a millimeter wave communication technology of a 60Ghz frequency band.
When the preset device comprises: when the first preset device and the second preset device are used,
a 60G communication module 603 operable to:
and respectively sending the data packets to the first preset device and the second preset device through a millimeter wave communication technology of a 60Ghz frequency band.
It should be understood that device 60 is only one example provided by embodiments of the present invention, and that device 60 may have more or fewer components than shown, may combine two or more components, or may have a different configuration implementation of components.
It can be understood that, regarding the specific implementation manner of the functional modules included in the device 60, reference may be made to the method embodiment shown in fig. 1 and the embodiment shown in fig. 2, which are not described herein again.
Fig. 6 is only for explaining the embodiment of the present invention, and the present invention should not be limited thereto.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses, systems and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided by the present invention, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. For example, the components and steps of the various examples are described. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The above-described embodiments of the system and apparatus are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices, systems or units, and may also be an electrical, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (12)
1. A program code execution method based on an FPGA chip is characterized by comprising the following steps:
the method comprises the steps that a device detects a control instruction, wherein the control instruction is used for instructing the device to call program codes related to the control instruction; the program code is used for the device to compress the acquired ultra high definition video, or the program code is used for the device to decompress the compressed ultra high definition video;
responding to the control instruction, the equipment calls a program code associated with the control instruction and loads the program code into an FPGA chip;
the device executes the program code through the FPGA chip to compress the acquired ultra high definition video, or the device executes the program code through the FPGA chip to decompress the compressed ultra high definition video.
2. The FPGA chip-based program code execution method of claim 1,
the device detects a control instruction, including:
when a user dials a dial switch of the equipment to a first side, the equipment detects that the level of a preset I/O interface of a micro control unit of the equipment is '0', the '0' level indicates that the equipment is sending equipment, and program codes related to the level of the '0' I/O interface are used for compressing the acquired ultra high definition video by the equipment; program code associated with said "0" I/O interface level comprising: a compression algorithm for compressing the acquired ultra high definition video; the preset I/O interface is any one interface of the micro control unit; alternatively, the first and second electrodes may be,
when a user dials a dial switch of the equipment to a second side, the equipment detects that the level of a preset I/O interface of a micro control unit of the equipment is '1', the '1' level indicates that the equipment is a receiving equipment, and program codes related to the level of the '1' I/O interface are used for decompressing the compressed ultra high definition video by the equipment; the program code associated with the "1" I/O interface level comprises: a decompression algorithm for decompressing the compressed ultra high definition video; wherein the position of the first side corresponds to or is symmetrical to the position of the second side.
3. The FPGA chip-based program code execution method of claim 1,
the device detects a control instruction, including:
the device detects a first control instruction sent by a control device and received through a control interface, wherein the first control instruction is used for indicating that: the equipment is sending equipment, and the equipment calls a program code associated with the first control instruction to compress the acquired ultra high definition video; alternatively, the first and second electrodes may be,
the device detects a second control instruction sent by the control device and received through a control interface, wherein the second control instruction is used for instructing: the device is a receiving device, and the device calls the program code associated with the second control instruction to decompress the compressed ultra high definition video; wherein the control interface comprises: a USB interface, an RS232 interface, an SPI interface, a network port, or an I2C interface.
4. The FPGA chip-based program code execution method of claim 1,
in response to the control instruction, the device invokes program code associated with the control instruction, including:
in response to the control instruction, the device calls program code associated with the control instruction from a memory integrated in the device; alternatively, the first and second electrodes may be,
in response to the control instruction, the device calls program code associated with the control instruction from a cloud database of the device; the cloud database comprises: an open source program code database.
5. The FPGA chip-based program code execution method of claim 1,
responding to the control instruction, the equipment calls a program code associated with the control instruction and loads the program code into an FPGA chip, and the method comprises the following steps:
and responding to the control instruction, calling a program code associated with the control instruction by the device through an internally integrated micro control unit, and loading the program code into the FPGA chip through an SPI (serial peripheral interface) of the micro control unit.
6. The FPGA chip-based program code execution method of claim 4,
the memory includes: a FLASH memory; the control instructions include: a first control instruction and a second control instruction; the first control instruction is used for instructing the equipment to call program codes associated with the first control instruction so as to compress the acquired ultra high definition video; the second control instruction is used for instructing the device to call program code associated with the second control instruction to decompress the compressed ultra high definition video;
in response to the control instruction, the device invokes, from a memory integrated in the device, program code associated with the control instruction, comprising:
in response to the first control instruction, the device calls program codes for compressing the acquired ultra-high-definition video from a first storage area in a FLASH memory integrated in the device; alternatively, the first and second electrodes may be,
in response to the second control instruction, the device calls program code for decompressing the compressed ultra high definition video from a second memory area in a FLASH memory integrated in the device.
7. The FPGA chip-based program code execution method of claim 1,
the device executes the program code through the FPGA chip to compress the acquired ultra high definition video, and the method comprises the following steps:
the device executes the program code through the FPGA chip to compress the acquired ultra-high-definition video to obtain code stream data;
the code stream data is used for packaging the equipment through a communication protocol to obtain a data packet; the program code includes: a compression algorithm for compressing the obtained ultra high definition video; the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol.
8. The FPGA chip-based program code execution method of claim 1,
the device decompresses the compressed ultra high definition video by executing the program code through the FPGA chip, and includes:
the device decompresses code stream data by executing the program code through the FPGA chip to obtain an ultra-high-definition video;
wherein the compressed ultra high definition video comprises: the code stream data; the program code includes: and the decompression algorithm is used for decompressing the code stream data.
9. The FPGA chip-based program code execution method of claim 7,
the device executes the program code through the FPGA chip to compress the acquired ultra high definition video, and after code stream data is acquired, the device further comprises:
the equipment encapsulates the code stream data into a data packet through a communication protocol; the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol; the data packet includes: UDP packets, TCP packets, or custom packets.
10. The FPGA chip-based program code execution method of claim 9,
after the device encapsulates the code stream data into a data packet through a communication protocol, the device further comprises:
the device sends the data packet through a communication module; the communication module includes: the system comprises an optical module, an electric module, a 5G communication module, a WIFI communication module or a 0G communication module; wherein, the electric module includes: a PHY chip and an RJ-45 interface.
11. The FPGA chip-based program code execution method of claim 8,
the device decompresses the code stream data by the FPGA chip executing the program code to obtain the ultra-high definition video, and the method further comprises the following steps:
the device outputting the ultra high definition video to a display device coupled with the device through an output interface; the display device is used for displaying the ultra-high-definition video; the output interface includes: one or more of an HDMI interface, a VGA interface, a USB interface, a Type-C interface or a DVI interface.
12. A program code execution device based on an FPGA chip, comprising:
a processor and an FPGA chip, wherein,
the processor is used for detecting a control instruction, and the control instruction is used for instructing the equipment to call the program code associated with the control instruction; the program code is used for the equipment to compress the acquired ultra high definition video or decompress the compressed ultra high definition video;
the FPGA chip is used for executing the program code to compress uncompressed ultra high definition video, or the FPGA chip executes the program code to decompress compressed ultra high definition video.
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