CN113740705A

CN113740705A - Method, device and related equipment for determining chip test working condition

Info

Publication number: CN113740705A
Application number: CN202110932534.8A
Authority: CN
Inventors: 唐文涛
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-08-13
Filing date: 2021-08-13
Publication date: 2021-12-03

Abstract

The embodiment of the invention provides a method, a device and related equipment for determining a chip test condition, wherein the method comprises the following steps: obtaining a test chip; circularly executing the test and screening of the test chip under the preset test working condition until the preset cycle is circularly executed; the testing of the test chips is used for determining the defective chips in the test chips, and the screening of the test chips is used for selecting and removing the defective chips in the test chips; judging whether the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round or not according to the statistical data of the defective chips determined under the preset round; and if the statistical data of the defect chips accord with the detection rule of the defect chips in the corresponding turn, determining the preset test working condition as the alternative test working condition, thereby accurately determining the alternative test working condition.

Description

Method, device and related equipment for determining chip test working condition

Technical Field

The embodiment of the application relates to the technical field of chip testing, in particular to a method and a device for determining a chip testing working condition and related equipment.

Background

The early failure test of a chip is one of chip tests for screening a defective chip in which an early failure occurs. The early failure of a chip refers to the phenomenon that the chip fails at the early stage of use after the chip is put into use. When the early failure test of the chip is carried out, test working conditions such as voltage and the like can be applied to the chip so as to judge whether the chip can generate failure conditions under the test working conditions. However, if the test working condition is too low, the required test time is too long, and the defective chips are easy to miss-select; if the test working condition is too high, the excessive loss to the chip is indicated, and the service life of the normal chip is further easily shortened.

Therefore, how to determine a suitable test condition from the test conditions applied to the chip so as to accurately implement the chip test (especially, the early failure test of the chip) becomes a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of this, embodiments of the present application provide a method, an apparatus, and a related device for determining a chip test condition, which can quickly and accurately determine the chip test condition, and provide a basis for accurately performing an early failure test of a chip.

In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:

in a first aspect, an embodiment of the present application provides a method for determining a chip test condition, including:

obtaining a test chip;

circularly executing the test and screening of the test chip under the preset test working condition until the preset cycle is circularly executed; the testing of the test chips is used for determining the defective chips in the test chips, and the screening of the test chips is used for selecting and removing the defective chips in the test chips;

judging whether the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round or not according to the statistical data of the defective chips determined under the preset round;

and if the statistical data of the defective chips accord with the detection rule of the defective chips in the corresponding turn, determining the preset test working condition as an alternative test working condition.

Optionally, in the preset round, at least one round at the initial stage of the test is a first round group, and a plurality of rounds at the later stage of the test are second round groups, the statistical data of the defect chip is judged whether to accord with the detection rule of the defect chip at the corresponding round, including:

judging whether the failure rate of the defective chip in the first round group is greater than that of the second round group;

if yes, judging whether the failure rate of the test chip in the second round group approaches to 0;

if yes, the statistical data of the defect chips accord with the detection rule of the defect chips in the corresponding turn.

Optionally, the method further includes:

and acquiring a test working condition to be tested, taking the test working condition to be tested as a preset test working condition, and returning to the step of acquiring the test chip.

Optionally, if the statistical data of the defective chip does not conform to the detection rule of the defective chip in the corresponding round, acquiring the test condition to be tested includes:

judging whether the preset test working condition is too low or not according to the statistical data of the defective chip;

and if the preset test working condition is too low, acquiring a test working condition to be tested with the test working condition higher than the preset test working condition as the preset test working condition.

Optionally, the determining whether the preset test condition is too low includes:

judging whether the failure rate of the defective chip under a preset turn is smaller than a first preset value, wherein the first preset value is larger than or equal to 80% of a predicted value of the failure rate of the test chip;

if yes, the preset test working condition is too low.

judging whether the failure rate of the defective chip in the first round is smaller than a second preset value, wherein the second preset value is larger than or equal to 80% of the estimated value of the failure rate of the test chip;

if yes, judging whether the failure rate of the defective chip in the second round is larger than a third preset value, wherein the third preset value is smaller than or equal to 15% of the estimated value of the failure rate of the test chip;

if yes, the preset test working condition is too low.

Optionally, the obtaining of the test condition to be tested includes:

judging whether the preset test working condition is too high or not according to the statistical data of the defective chip;

and if the preset test working condition is too high, acquiring a test working condition to be tested with the test working condition lower than the preset test working condition as the preset test working condition.

Optionally, the determining whether the preset test condition is too high includes:

judging whether the failure rate of the defective chip under the preset turn is greater than a fourth preset value, wherein the fourth preset value is greater than or equal to 120% of the estimated value of the failure rate of the test chip;

if so, the preset test working condition is too high.

judging whether the failure rate of the statistical data of the defective chips in the first round group is reduced round by round;

judging whether the failure rate of the statistical data of the defective chips in the second round group is increased round by round or not;

if so, the preset test working condition is too high.

Optionally, after determining that the preset test condition is the alternative test condition, the method further includes:

performing a chip life test on the test chip;

and if the test chip passes the chip life test, determining the alternative test working condition as a target test working condition.

Optionally, the performing a chip lifetime test on the test chip includes:

obtaining a comparison chip, wherein the comparison chip is a chip which does not execute the step of circularly executing the test and the screening of the test chip;

and executing a chip life test on the comparison chip and the test chip, and if the difference value between the chip life of the test chip and the chip life of the comparison chip is within a preset range, the test chip passes the chip life test.

Optionally, if the number of the target test working conditions is multiple, the target test working condition with the shortest test time in the target test working conditions is selected as the optimal test working condition.

Optionally, a plurality of preset test working conditions are provided;

the obtaining of the test chips specifically comprises obtaining a plurality of groups of test chips;

the test and screening of the test chips under the preset test working condition are executed in a circulating mode until the preset cycle is executed in a circulating mode, specifically, the test and screening corresponding to the preset test working condition are executed in a circulating mode for the plurality of groups of test chips until the preset cycle is executed in a circulating mode; the group of test chips are used for corresponding to a preset test working condition;

judging whether the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round according to the statistical data of the defective chips determined in the preset round, specifically, judging whether the statistical data of the defective chips in each group of test chips meet the detection rule of the defective chips in the corresponding round one by one according to the statistical data of the defective chips determined in the preset round; if yes, determining a preset test working condition corresponding to the test chip as an alternative test working condition; and if not, determining that the preset test working condition corresponding to the test chip is not the alternative test working condition.

Optionally, the preset test condition includes at least one of the following conditions:

temperature, voltage, duration, and test vector.

Optionally, the selecting and removing the defective chip in the test chip includes:

determining a defective chip in the test chip based on the test data of the test chip;

and removing the defective chip.

In a second aspect, an embodiment of the present application provides an apparatus for determining a chip test condition, where the apparatus includes:

the chip acquisition module is used for acquiring a test chip;

the circulating test module is used for circularly executing the test and the screening of the test chip under the preset test working condition until the circulation preset turn; the testing of the test chips is used for determining the defective chips in the test chips, and the screening of the test chips is used for selecting and removing the defective chips in the test chips;

the data judgment module is used for judging whether the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round or not according to the statistical data of the defective chips determined under the preset round;

and the alternative determining module is used for determining the preset test working condition as an alternative test working condition if the statistical data of the defect chip accords with the detection rule of the defect chip in the corresponding turn.

In a third aspect, an embodiment of the present application provides a test system, where the test system includes a chip test device, and the chip test device is configured to execute the method for determining a chip test condition.

In a fourth aspect, an embodiment of the present application provides a computer device, including: at least one memory and at least one processor; the memory stores one or more computer-executable instructions that are invoked by the processor to perform the above-described method of determining chip test conditions.

In a fifth aspect, an embodiment of the present application provides a storage medium, where the storage medium stores one or more computer-executable instructions, and the one or more computer-executable instructions are configured to execute the method for determining a chip test condition.

Compared with the prior art, the technical scheme of the embodiment of the application has the following advantages:

the method, the device and the related equipment for determining the chip test working condition provided by the embodiment of the application comprise the following steps: obtaining a test chip; circularly executing the test and screening of the test chip under the preset test working condition until the preset cycle is circularly executed; the testing of the test chips is used for determining the defective chips in the test chips, and the screening of the test chips is used for selecting and removing the defective chips in the test chips; judging whether the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round or not according to the statistical data of the defective chips determined under the preset round; and if the statistical data of the defective chips accord with the detection rule of the defective chips in the corresponding turn, determining the preset test working condition as an alternative test working condition.

The statistical data of the defect chips under the corresponding round is obtained by testing and screening the test chips in the preset round, and whether the statistical data of the defect chips accord with the detection rule of the defect chips in the corresponding round is judged according to the statistical data of the defect chips determined under the preset round. If the preset test working condition is effective and does not cause excessive loss to the chip, the detection amount of the corresponding defective chip is in accordance with the detection rule of the defective chip in the corresponding round, so that the statistical data of the defective chip is in accordance with the detection rule of the defective chip in the corresponding round, the preset test working condition is determined to be the alternative test working condition, the chip test working condition is further rapidly and accurately determined, and a foundation is provided for accurately realizing the early failure test of the chip.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of an alternative structure of a chip testing apparatus according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an alternative flow chart of a method for determining a test condition of a chip according to an embodiment of the present invention;

FIG. 3 is an exemplary diagram of failure rates of corresponding rounds under different preset conditions in the embodiment of the present invention;

FIG. 4 is a schematic diagram of an alternative flow chart of another method for determining a test condition of a chip according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating an alternative flow of another method for determining a test condition of a chip according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating an alternative flow chart of step S20 according to the embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating an alternative flow chart of step S20 according to the embodiment of the present invention;

FIG. 8 is a schematic diagram of an alternative process for determining a test condition of a chip according to an embodiment of the present invention;

FIG. 9 is a block diagram of an apparatus for determining a test condition of a chip according to an embodiment of the present invention;

FIG. 10 is a block diagram of another apparatus for determining a test condition of a chip according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Since the manufacturing process of the chip is complicated and the number of processes is large, a defective chip (hereinafter referred to as a defective chip) is inevitably generated in the manufacturing process of the chip. The chip with partial defects has normal performance in initial use, but after a short period of use, the defects are excited to further cause chip failure, and the phenomenon that the chip fails in the initial use stage is called early failure of the chip. The defect chips are good products when leaving factory for detection, and are out of work early when being put into market for use, thereby influencing customers. In order to solve the problem of early failure of the chip, the defective chip can be screened through the early failure test of the chip. To facilitate understanding of the early failure test, the early failure test is described in detail below.

Early failure testing of chips is typically done before shipment, such as after FT (Final-Test) and before SLT (System-Level-Test), or embedded during Wafer-Test (WS) or Chip-Probe (CP) after Chip packaging.

Independent early failure testing typically employs Burn-in or embedded methods similar to Burn-in methods to screen the chips. The burn-in method is generally applied to packaged chips, and a separate test machine is required to be arranged in corresponding test equipment to provide a test environment. The embedded method is combined in the WS test or the CP test, and the corresponding test environment and test conditions can be provided by the WS test or CP test equipment.

Referring to fig. 1, an alternative structure of a chip testing apparatus 100 may include: processor 10, memory 11, peripheral interface 12, test machine 13.

The processor 10 may be an integrated circuit chip for implementing or executing the methods, steps and logic diagrams disclosed in the embodiments of the present application, including a chip early failure testing method and a method for determining a chip testing condition.

The memory 11 is used for storing programs, such as an early failure test program or a program for determining the test condition of the chip, and the processor 11 reads and executes the programs after receiving corresponding instructions.

The peripheral interface 12 is configured to output a corresponding test signal or control signal, and input a feedback response signal after executing a corresponding test procedure or determining a chip test condition procedure.

The test machine 13 is configured to execute a test on the chip based on the corresponding test signal or the control signal, and feed back a corresponding response signal to the peripheral interface 12.

The peripheral interface 12 couples the tester platform 13 to the processor 10 and the memory 11. In some embodiments, the processor 10, the memory 11, and the peripheral interface 12 may be implemented in the same chip. In some alternative examples, they may be implemented separately by separate chips.

In the chip testing device, the components are directly or indirectly electrically connected with each other to realize data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines.

Illustratively, when performing the early failure test, the memory 11 stores an early failure test program, and when the processor 10 runs the early failure test program, the early failure test can be performed on the chip based on the test machine.

When a chip test procedure is executed, a test condition may be understood as a test condition applied to a chip, which may also be referred to as a stress condition. In the early failure test procedure, the test conditions may include temperature T, voltage V, duration T, and test vector P. The Test vector P may be an ATE (Automatic-Test-Equipment) Test vector, such as an ATE BIST (built-in-self-Test) vector or an ATPG (Automatic-Test-pattern-generator) vector. In the embodiment of the present application, the test condition may be defined as: f (T, V, T, P). An alternative preset test condition may be represented as: fj (Tj, Vj, Tj, Pj).

Specifically, the early failure testing process of the chip is as follows: and under the determined test working condition, executing a test flow of the chip, placing the chip under the corresponding test working condition, judging whether the chip under the test working condition is invalid or not, and if the chip under the test working condition is invalid, considering the corresponding chip as a defective chip, and screening the defective chip.

Based on the background technology, in the testing process, the testing working condition is too low, the required testing time is too long, and the defective chips are easy to miss-select; the too high test condition means excessive loss to the chip, and further the service life of the normal chip is easily shortened. In the field of chip testing, how to determine a suitable test condition from test conditions applied to a chip so as to accurately implement chip testing (especially early failure testing of the chip) becomes a technical problem that needs to be solved by those skilled in the art.

The inventor has noted that, under ideal conditions, if the test conditions are appropriate, only one round of test is usually performed during the chip test, and the defective chip in the chip is determined based on the test data of the round. If the test working condition is appropriate, the corresponding test can determine the defective chip in the chip and can also generate loss to the chip as less as possible. Based on this, the inventor further analyzes and considers that, on the premise that the test working condition is appropriate, if the chips are subjected to the multiple rounds of cycle test and screening, the test data corresponding to the multiple rounds should accord with the detection rule of the defective chip in the corresponding round.

Based on this, the embodiment of the present invention provides a method, an apparatus and a related device for determining a chip test condition, where the method includes: obtaining a test chip; circularly executing the test and screening of the test chip under the preset test working condition until the preset cycle is circularly executed; the testing of the test chips is used for determining the defective chips in the test chips, and the screening of the test chips is used for selecting and removing the defective chips in the test chips; judging whether the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round or not according to the statistical data of the defective chips determined under the preset round; and if the statistical data of the defective chips accord with the detection rule of the defective chips in the corresponding turn, determining the preset test working condition as an alternative test working condition.

It can be seen that the statistical data of the defective chips under the corresponding round is obtained by testing and screening the test chips in the preset round, and whether the statistical data of the defective chips accords with the statistical rule of the defective chips is further judged according to the statistical data of the defective chips determined under the preset round. It can be understood that if the preset test condition is too low, the conditions such as selection omission may occur, so that the statistical data of the corresponding defective chip cannot accord with the statistical rule of the defective chip, and if the preset test condition is too high, the defective chip generated by multiple tests inevitably occurs after the multiple tests through the preset round of cycle tests, so that the statistical data of the corresponding defective chip cannot accord with the statistical rule of the defective chip. Therefore, only after the test and the screening of the preset turns, the preset test working condition that the statistical data of the defect chip accords with the statistical rule of the defect chip is the proper test working condition, so that the preset test working condition can be determined as the alternative test working condition, the test working condition of the chip is determined quickly and accurately, and a foundation is provided for accurately testing the early failure of the chip.

In an alternative embodiment of the present invention, referring to fig. 2, an alternative flow chart of a method for determining a test condition of a chip is shown, as shown in fig. 2, the method includes:

step S10: obtaining a test chip;

the test chip is a chip to be tested before leaving a factory, and the test chip can be understood as a chip positioned on a wafer or an independent chip after being packaged.

The number of the test chips is multiple, wherein the number of the test chips and the number of the defective chips in the test chips can at least reflect the statistical rules of the defective chips. In an alternative example, the failure rate (the proportion of defective chips in the test chip) of the test chip is usually less than 10%, and therefore, the test chip should embody the statistical regularity of the defective chips, and the number of corresponding test chips should be greater than or equal to 100. In a preferred example, the number of test chips may also be greater than or equal to 1000.

For example, a batch of chips may be selected as test chips.

It should be noted that, if the Test chip is a chip on a wafer, the corresponding preset Test condition may be a Test condition of an early failure Test embedded in an HVST (High-Voltage-Stress-Test), and if the Test chip is a package chip, the corresponding preset Test condition may be a Test condition in a Burn-in Test.

Step S11: circularly executing the test and screening of the test chip under the preset test working condition until the preset cycle is circularly executed;

the testing of the test chips is used for determining the defective chips in the test chips, and the screening of the test chips is used for selecting and removing the defective chips in the test chips.

By circularly executing the test and the screening of the test chip under the preset test working condition, whether the preset test working condition is the proper test working condition or not can be judged from the statistical angle. The preset test working condition comprises at least one of temperature T, voltage V, duration T and a test vector P.

The temperature T is a test temperature which is used for limiting a specific test environment, the test temperature is usually larger than or equal to room temperature, in the process of determining the test working condition of the chip, the temperature can be set into a plurality of values, one preset test working condition corresponds to one temperature value, and the temperature values are determined one by one based on the corresponding preset test working condition.

The voltage V is a voltage that the test chip needs to bear in the test process, and the voltage may be generally within a preset proportion range of a maximum voltage that the test chip can bear, for example, 60% to 100%, and the like.

The duration t is the duration of applying the test working condition to the test chip in the test process, the duration can be determined according to the actual function of the chip and the early failure experience value of the chip, in the determination process of the test working condition of the chip, the duration t can be set into a plurality of values, a preset test working condition corresponds to one duration, and the duration t is determined one by one based on the corresponding preset test working condition.

The test vector P is an electrical signal applied by the test chip during the test process, and the electrical signal can be characterized as a string composed of a segment of 0 and a segment of 1. The test vector may execute a memory BIST or a logic BIST, and a person skilled in the art may determine the test vector P according to an actual function of the chip, and in the determination process of the test condition of the chip, the test vector P may set a plurality of schemes, and a preset test condition corresponds to a test vector, and the test vector P is determined one by one based on the corresponding preset test condition.

In the embodiment of the present application, the test condition may be defined as: f (T, V, T, P), an optional predetermined test condition may be expressed as: fj (Tj, Vj, Tj, Pj).

It can be understood that different test conditions can be correspondingly set based on different parameters, and based on different test conditions, the test determination can be performed one by one, or the parallel test determination can be performed based on different groups of test chips.

Under a preset test condition, testing and screening of the test chip can be performed. The test of the test chip can be realized by controlling the test body through corresponding test programs, such as WS, CP, FT, SLT and the like in the ATE test program.

The test on the test chip may include a test in one cycle, the corresponding time duration may be tj, or a test in multiple cycles, the corresponding time duration may be tj × cj, where c is the number of cycles of the test. Accordingly, the preset test condition for performing the test can be expressed as: fj (Tj, Vj, Tj × cj, Pj). It should be noted that, in the preset test condition according to the embodiment of the present invention, even if the test is performed for a plurality of cycles, the test is still understood to be performed once (i.e., one round).

In the screening process of the test chips, the defective chips in the test chips can be determined based on the test data of the test chips, and further removed.

It should be noted that, the test and the screening of the test chip are performed once, which is understood to be a cycle. In the process of circulating a plurality of rounds, the test of each round is executed for a corresponding number of cycles, and after the test of the round is executed, the screening of the round is executed.

The statistical data of the defective chips in the corresponding round can be determined according to the number of the defective chips screened in each round. In an optional example, the statistical data of the defective chips may be, for example, failure rates of the test chips detected in each test round (i.e., occupation ratios of the defective chips in the test chips), such as 3% failure rate in the first test round, 1% failure rate in the second test round, and so on.

And based on the statistical data of the defective chips determined in the preset turn, determining whether the statistical data of the defective chips conform to the statistical rules of the defective chips, and correspondingly, the statistical data of the defective chips determined in the preset turn should be capable of representing the statistical variation trend of the defective chips. Specifically, the number of preset rounds may be greater than or equal to 12. In an optional example, the number of preset turns may be determined according to an actual situation when it is satisfied that the statistical data of the defect chips determined in the preset turns can represent a statistical variation trend of the defect chips, and the present invention is not limited specifically herein.

Step S12: judging whether the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round or not according to the statistical data of the defective chips determined under the preset round;

it can be understood that, in an ideal test process, if the preset test condition is valid and will not cause excessive loss to the chip, the detected amount of the corresponding defective chip should be detected in one test round of the preset test condition, and the detected amount of the subsequent round is 0. Considering the deviation between the actual operation and the ideal situation, the detection amount of the corresponding defective chip should detect most of the initial test rounds (for example, 80% to 95% of all the defective chips), and the detection amount of the subsequent rounds is close to 0. Therefore, if the preset test condition is valid and does not cause excessive loss to the chip (hereinafter referred to as a proper condition), the statistical data of the defective chip determined in the preset round should conform to the detection rule of the defective chip in the corresponding round.

Referring to fig. 3, an exemplary graph of failure rates of corresponding rounds under different preset conditions is shown, where Gj denotes a test chip corresponding to a preset test condition Fj, and 4 groups shown in the graph include G1, G2, G3, and G4, which are respectively used for corresponding to preset test conditions F1, F2, F3, and F4, it can be seen that the failure rates of G1 and G2 in initial several test rounds are high, so that most defective chips are detected, the failure rates in subsequent rounds approach to 0, and the corresponding detected amounts approach to 0, so that the detection rule of the defective chips in the corresponding rounds is met.

In the judgment of this step, if the statistical data of the defective chip conforms to the detection rule of the defective chip in the corresponding round, step S13 may be executed to determine that the preset test condition is an alternative test condition; and if the statistical data of the defective chips does not accord with the detection rule of the defective chips in the corresponding turn, the preset test working condition is not the alternative test working condition.

In an alternative example, of the preset rounds, at least one round at the initial stage of the test may be defined as a first round group, and a plurality of rounds at the later stage of the test may be defined as a second round group, where the first round group and the second round group do not overlap. Optionally, the number of rounds of the first run group is smaller than the number of rounds of the second run group. Preferably, 2 to 6 rounds in the initial period of the test can be defined as a first round group, and the rest rounds can be defined as a second round group.

Correspondingly, judging whether the statistical data of the defective chip conforms to the statistical rule of the defective chip or not comprises the following steps:

step S121: judging whether the failure rate of the defective chip in the first round group is greater than that of the second round group;

detection rule based on defective chips: most of the test runs (for example, 80% to 95% of all the defective chips) in the initial test runs, and the detected amount of the subsequent test runs approaches to 0, and obviously, if the preset test working condition is a proper working condition, the failure rate of the defective chip in the first run group should be greater than that of the second run group.

The failure rate of the first round group can be understood as the sum of the failure rates of all rounds in the round group, and the failure rate of the second round group can be understood as the sum of the failure rates of all rounds in the round group.

In the judgment of the step, if yes, the failure rate of the second round group can be further judged; if not, determining that the statistical data of the defective chips does not accord with the detection rule of the defective chips in the corresponding turn, and determining that the preset test working condition is not the alternative test working condition.

Step S122: judging whether the failure rate of the test chip in the second round group approaches to 0 or not;

it can be understood that if the preset test condition is a suitable condition, the failure rate of the test chip in the second round group should approach 0. Wherein said approach to 0 may be understood as being close to 0. In an alternative example, the failure rate of the second round subgroup approaches 0, which may be defined as the failure rate of the second round subgroup being less than or equal to 10%.

In the judgment of the step, if yes, the statistical data of the defect chips conform to the detection rule of the defect chips in the corresponding turn; if not, determining that the statistical data of the defective chips does not accord with the detection rule of the defective chips in the corresponding turn, and determining that the preset test working condition is not the alternative test working condition.

If the statistical data of the defective chips matches the detection rule of the defective chips in the corresponding round, step S13 may be executed.

Step S13: and determining the preset test working condition as an alternative test working condition.

The alternative test condition may be understood as a test condition to be used. In an optional example, the alternative test condition may be used as a suitable test condition, or the alternative test condition may be further tested and verified to determine that the alternative test condition is valid and does not cause excessive loss to the chip.

It can be seen that, in the embodiment of the present invention, the statistical data of the defective chip in the corresponding round is obtained by performing the test and the screening of the test chip in the preset round, and whether the statistical data of the defective chip conforms to the detection rule of the defective chip in the corresponding round is further determined according to the statistical data of the defective chip determined in the preset round. If the preset test working condition is effective and does not cause excessive loss to the chips, the detection amount of the corresponding defect chips is in accordance with the detection rule of the defect chips in the corresponding turn, so that the statistical data of the defect chips are in accordance with the detection rule of the defect chips in the corresponding turn, and the preset test working condition is determined to be the alternative test working condition.

In an optional embodiment of the present invention, the method for determining the test condition of the chip may further perform a life test on the screened test chip after determining the candidate test condition, and further determine whether the life of the corresponding chip is affected after the test chip is subjected to the test and the screening for the preset number of times, so as to verify that the candidate test condition is the appropriate test condition.

Specifically, referring to an alternative flow chart of the method for determining the test condition of the chip shown in fig. 4, as shown in fig. 4, the method further includes:

step S14: performing a chip life test on the test chip;

and if the test chip passes the chip life test, executing a step S15, and determining that the alternative test working condition is a target test working condition.

It can be understood that after the chip life test, whether the corresponding chip life is affected by the test chip after the test of the preset round and the screening can be verified. It should be noted that, in consideration of the fact that the actual test process may cause a small loss to the test chip, the lifetime of the chip is not affected, and does not mean that the lifetime of the chip is not affected at all, but means that the lifetime difference is within a controllable range compared with the lifetime of the chip that is not subjected to the test and screening of the preset round.

Optionally, the chip lifetime test may be an HTOL (High temperature operating lifetime) test.

Wherein, the step S14 may include:

step S141: obtaining a comparison chip;

wherein the control chip is a chip for which the test and screening steps for the test chip are not performed in the loop; through this comparison chip with the test chip compares, can confirm through the test of predetermineeing the round and screening back, whether the chip life-span of test chip receives the influence, perhaps, whether the difference of the chip life-span of test chip and comparison chip is in predetermined within range to carry out the chip life-span verification of test chip.

The number of the control chips is plural, and it is understood that the number of the control chips should be sufficient to statistically represent the average life of the control chips. Alternatively, the number of control chips may be greater than or equal to 100.

In a preferred example, the control chip may be a chip that has been screened for an early failure test, so as to avoid that the control chip contains too many chips with early failure defects, thereby affecting the chip lifetime.

Step S142: performing a chip life test on the comparison chip and the test chip;

and executing a chip life test on the comparison chip and the test chip, so that the difference between the chip life of the test chip and the chip life of the comparison chip can be determined, and whether the test chip passes the chip life test can be determined based on the difference between the chip life of the test chip and the chip life of the comparison chip.

It is understood that the corresponding test conditions should be consistent for the chip life tests performed by the control chip and the test chip. Optionally, the chip lifetime tests of the control chip and the test chip may be performed in parallel.

The chip life test is typically performed at high temperature, high pressure and high stress. Wherein, the temperature may be greater than or equal to 125 degrees celsius, the voltage may be greater than or equal to 1.1 times Vdd (the operating voltage of the chip), and after the Test, an ATE (Auto Test Equipment), FT (Final Test)/SLT (System Level Test) Test is performed to confirm whether it is failed.

And if the difference value of the chip life of the test chip and the chip life of the comparison chip is within a preset range, the test chip passes the chip life test. Taking the HTOL test as an example, the preset range may be 10% of the chip life of the control chip, and in other optional examples, the preset range may also be 5% of the chip life of the control chip.

In an optional example, if the test chip has the corresponding comparison parameter, the test chip may be directly subjected to a chip life test without performing a test on the comparison chip, and the corresponding comparison parameter is obtained, and the test data of the test chip and the comparison parameter are compared and determined.

If the test chip passes the chip life test, step S15 is executed.

And step S15, determining the alternative test working condition as a target test working condition.

Through the alternative test working condition of the chip life test, the test working condition can be considered as a proper test working condition, so that the alternative test working condition can be determined as a target test working condition.

It can be seen that after the alternative test working condition is determined, the service life of the screened test chip is further tested, so that whether the service life of the corresponding chip is influenced after the test chip is tested and screened for the preset times is determined, and the alternative test working condition is verified to be the proper test working condition.

In another optional embodiment of the present invention, the method for determining the test condition of the chip may further perform the determination process of the preset test condition in a loop according to different test conditions to be tested. Specifically, referring to fig. 5, an alternative flow chart of another method for determining a test condition of a chip may be shown, and as shown in fig. 5, the method may include:

step S20: acquiring a test working condition to be tested, and taking the test working condition to be tested as a preset test working condition;

the test condition to be tested can be understood as the test condition to be determined. The test to be tested can be obtained in sequence or based on a preset rule, so that a new determining process of the preset test working condition is executed based on the test working condition to be tested.

After step S20 is performed, the process returns to step S10 of acquiring a test chip.

Step S20 may be executed after step S12, in other embodiments, after step S13 is executed when the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round, or in this embodiment, step S20 may be executed after step S14.

In an optional example, when the statistical data of the defect chip does not conform to the detection rule of the defect chip in the corresponding round, whether the preset test condition is too low or not may be further determined, and then according to the determination, a suitable test condition to be tested is selected as the preset test condition to execute the determination process of the next preset test condition.

Specifically, in step S12, if the statistical data of the defective chips does not conform to the rule of detecting the defective chips in the corresponding round, referring to an optional flowchart of step S20 shown in fig. 6, as shown in fig. 6, step S20 may include:

step S21: judging whether the preset test working condition is too low or not according to the statistical data of the defective chip;

when the preset test working condition is too low, the condition of missing detection of the defect chip may occur, so that the rule that the overall failure rate of the test chip is lower after the test and the screening of the preset round may occur. Or, from the detection rules of different rounds, the detection quantity of the defect chip is less due to missing detection in the initial round, and the detection quantity of the defect chip which is missed in the later round is more.

Referring to the failure rate example diagram of the corresponding round under different preset working conditions in fig. 3 in combination, it can be seen that the overall failure rate of G4 is low, and from the failure rates of different rounds, the failure rate of the defective chip in the initial round is low, and the failure rate in the later round (e.g. 8 th round) is high, so that it can be seen that the initial round detection amount is low in the test of the test chip, and the later round detection amount is high, so that the preset test working condition F4 corresponding to G4 is too low.

Based on this, step S21 may include:

step S211: judging whether the failure rate of the defect chip under a preset turn is smaller than a first preset value or not;

and if the failure rate of the defective chip under the preset turn is less than the first preset value, the overall failure rate is considered to be low, and the preset test working condition is considered to be too low.

Therefore, in the determination step of step S211, if yes, it is determined that the preset test condition is too low, and step S22 is executed.

In another example, considering the situation that the missing detection may occur in the defect chip when the preset test condition is too low, from the detection rules of different rounds, the detection amount of the defect chip in the initial round due to the missing detection is less, and the detection amount of the missed defect chip in the later round is more.

Based on this, step S21 may include:

step S212: judging whether the failure rate of the defective chip in the first round group is smaller than a second preset value or not;

wherein the second preset value is greater than or equal to 80% of the estimated value of the failure rate of the test chip. Based on the first round group being the initial round, whether the failure rate of the defect chip in the first round group is smaller than a second preset value or not can be judged, if yes, step S213 is further executed to judge the failure rate in the second round group to determine whether the preset test condition is too low or not.

Step S213: judging whether the failure rate of the defective chip in the second round group is greater than a third preset value or not;

wherein the third preset value is less than or equal to 15% of the estimated value of the failure rate of the test chip. And judging whether the failure rate of the defect chip in the second round group is less than a third preset value or not based on the fact that the second round group is a later round group, and judging whether the detected quantity of the defect chip in the later round group is more or not so as to determine whether the preset test working condition is too low or not.

If yes, the preset test condition is too low, and step S22 is executed.

Step S22: and acquiring a test working condition to be tested with a test working condition higher than the preset test working condition as the preset test working condition.

Under the condition that the preset test working condition is over-low, when the test working condition to be tested is obtained, the test working condition to be tested, which is higher than the preset test working condition, can be obtained as the preset test working condition, so that the proper test working condition can be quickly and accurately found out.

In an optional example, when the statistical data of the defect chip does not conform to the detection rule of the defect chip in the corresponding round, whether the preset test condition is too high may be further determined, and then according to the determination, a suitable test condition to be tested is selected as the preset test condition to execute the determination process of the next preset test condition.

Specifically, in step S12, if the statistical data of the defective chips does not conform to the rule of detecting the defective chips in the corresponding round, referring to another alternative flow diagram of step S20 shown in fig. 7, as shown in fig. 7, step S20 may further include:

step S23: judging whether the preset test working condition is too high or not according to the statistical data of the defective chip;

when the preset test working condition is too high, the test chip is subjected to excessive loss caused by cycle test, so that the service life of the normal test chip is exhausted, the test chip is changed into a defect chip, and the failure rate of the defect chip under the preset turn is shown as a higher rule on the whole.

Referring to the failure rate example diagrams of corresponding rounds under different preset working conditions in fig. 3 in a combined manner, it can be seen that the overall failure rate of G3 is higher, so that it can be determined that the preset test working condition F3 corresponding to G3 is too high.

Based on this, step S23 may include:

step S231: judging whether the failure rate of the defect chip under the preset turn is greater than a fourth preset value or not;

and if the failure rate of the defective chip under the preset turn is greater than the fourth preset value, the overall failure rate is considered to be higher, and the preset test working condition is considered to be too high.

Therefore, in the determination step of step S231, if yes, it is determined that the preset test condition is too high, and step S24 is executed.

In another example, when the preset test condition is considered to be too high, in each round, it is shown that a defective chip is detected quickly in the initial round, the corresponding failure rate is shown to decrease from round to round, and after the preset round of cycle test, excessive loss caused by the cycle test is generated on the test chip, and then the rule that the detected amount of the defective chip is increased from round to round in the later round is generated.

Referring to the failure rate example diagrams of the corresponding rounds under different preset conditions in fig. 3, it can be seen that the failure rate of G3 decreases from round to round in the initial round, and increases from round to round in the later round, so that it can be determined that the preset test condition F3 corresponding to G3 is too high.

Based on this, step S23 may include:

step S232: judging whether the failure rate of the defective chip in the first round group is reduced round by round;

and if so, further executing the step S233, judging the failure rate in the second round group, and further determining whether the preset test working condition is too high.

Step S233: judging whether the failure rate of the defective chip in the second round group is increased round by round or not;

and judging whether the failure rate of the defect chip in the second round group is increased round by round or not based on the fact that the second round group is the later round group so as to judge whether the detected quantity of the defect chip of the later round accords with the performance of whether the preset test working condition is too high or not and further determine whether the preset test working condition is too high or not.

If yes, the preset test condition is too high, and step S24 is executed.

Step S24: and acquiring a test working condition to be tested with the test working condition lower than the preset test working condition as the preset test working condition.

In yet another optional embodiment of the present invention, the method for determining a test condition of a chip may further perform a determination process on the test condition for a plurality of preset test conditions at the same time. Specifically, referring to an optional flowchart of determining a test condition of a chip shown in fig. 8, as shown in fig. 8, the method may include:

step S30: acquiring a plurality of groups of test chips;

wherein, a set of test chip is used for corresponding to a preset test operating mode. The step S30 can be understood as an alternative to the step S10. Accordingly, the process of obtaining the test chip in step S30 can refer to the description of step S10.

It can be understood that, in step S30, the obtained test chips are further grouped, and a group of test chips is used to correspond to one preset test condition, so that this step provides a basis for implementing a plurality of preset test conditions to execute the determination process simultaneously.

Step S31: circularly executing the test and screening corresponding to preset test working conditions on the plurality of groups of test chips until a preset turn is circularly executed;

and circularly executing the test and the screening corresponding to the preset test working condition for the plurality of groups of test chips based on one group of test chips corresponding to one preset test working condition until the preset round is circularly performed so as to determine the test data of each group of test chips and further obtain the statistical data of the defective chips determined by each group of test chips under the preset round.

It is understood that the step S31 can be understood as an alternative embodiment of the step S11. Accordingly, the execution process of step S31 can refer to the description of step S11.

Step S32: judging whether the statistical data of the defective chips in each group of test chips meet the detection rule of the defective chips in the corresponding round one by one according to the statistical data of the defective chips determined under the preset round;

if yes, executing step S33, and determining a preset test working condition corresponding to the test chip as an alternative test working condition; if not, determining that the preset test working condition corresponding to the test chip is not the alternative test working condition.

It is understood that the step S32 can be understood as an alternative embodiment of the step S12. Accordingly, the execution process of step S32 can refer to the description of step S12.

Step S33: determining a preset test working condition corresponding to the test chip as an alternative test working condition;

it is understood that the step S33 can be understood as an alternative embodiment of the step S13. Accordingly, the execution process of step S33 can refer to the description of step S13.

In an optional example, after the preset test condition is determined to be the alternative test condition, verification of the service life of the chip may be further performed. Specifically, the method further comprises:

step S34: performing a chip life test on the test chip;

the execution of step S34 can refer to the description of step S14.

When the candidate test conditions are multiple, the chip life test can be performed on each group of test chips one by one, or the chip life test can be performed on multiple groups of test chips simultaneously. In a preferred embodiment, chip life testing may be performed on multiple groups of test chips simultaneously to save testing time.

If the test chip passes the chip life test, step S35 is executed.

Step S35: and determining the alternative test working condition as a target test working condition.

The execution of step S35 can refer to the description of step S15.

It should be noted that, when there are a plurality of candidate test conditions, there may be a plurality of corresponding target test conditions. In the failure test, any target test condition may be selected as a test condition of the chip, or in an optional example, the target test condition with the shortest test time among the target test conditions may be selected as an optimal test condition, and the optimal test condition is used as a test condition of the chip to perform the test.

The following describes a device for determining a chip test condition provided in the embodiment of the present application, where the device content described below may be considered as a chip test device or a computer device, and is a functional module required to implement the method for determining a chip test condition provided in the embodiment of the present application. The device content described below may be referred to in correspondence with the method content described above.

FIG. 9 is a block diagram illustrating an apparatus for determining a test condition of a chip according to an embodiment of the present disclosure. As shown in fig. 9, the apparatus may include:

a chip obtaining module 200, configured to obtain a test chip;

the cyclic test module 210 is configured to cyclically execute testing and screening of the test chips under a preset test condition until a preset cycle is cyclically executed; the testing of the test chips is used for determining the defective chips in the test chips, and the screening of the test chips is used for selecting and removing the defective chips in the test chips;

the data judgment module 220 is configured to judge whether the statistical data of the defective chips meet the detection rule of the defective chips in the corresponding round according to the statistical data of the defective chips determined in the preset round;

and an alternative determining module 230, configured to determine the preset test condition as an alternative test condition if the statistical data of the defective chip meets the detection rule of the defective chip in the corresponding round.

Optionally, in the preset rounds, at least one round at the initial stage of the test is a first round group, and a plurality of rounds at the later stage of the test are second round groups, the data judgment module 220 is configured to judge whether the statistical data of the defect chip conforms to the detection rule of the defect chip in the corresponding round, and includes:

Optionally, the apparatus further comprises:

and the working condition obtaining module 240 is configured to obtain a test working condition to be tested, and return to the step of obtaining the test chip with the test working condition to be tested as a preset test working condition.

Optionally, if the statistical data of the defective chips does not conform to the detection rule of the defective chips in the corresponding round, the working condition obtaining module 240 is configured to obtain the testing working conditions to be tested, and includes:

Optionally, the working condition obtaining module 240 is configured to determine whether the preset test working condition is too low, and includes:

if yes, the preset test working condition is too low.

Optionally, the working condition obtaining module 240 is configured to obtain a test working condition to be tested, and includes:

Optionally, the working condition obtaining module 240 is configured to determine whether the preset test working condition is too high, and includes:

if so, the preset test working condition is too high.

Optionally, fig. 10 shows a block diagram of another apparatus for determining a chip test condition according to an embodiment of the present application. As shown in fig. 10, the apparatus may include:

the device further comprises:

a life test module 250, configured to perform a chip life test on the test chip;

and the target determination module 260 is configured to determine that the candidate test condition is a target test condition if the test chip passes the chip life test.

Optionally, the life test module 250 is configured to perform a chip life test on the test chip, and includes:

Optionally, the apparatus further comprises:

and an optimal determining module 270, configured to select, as the optimal testing condition, the target testing condition that requires the shortest testing time among the multiple target testing conditions.

Optionally, a plurality of preset test working conditions are provided;

the chip obtaining module 200 is configured to obtain test chips, specifically, obtain a plurality of groups of test chips;

the cycle testing module 210 is configured to cyclically execute testing and screening of the test chips under a preset testing condition until a preset cycle is cycled, and specifically, to cyclically execute testing and screening of the plurality of groups of test chips corresponding to the preset testing condition until the preset cycle is cycled; the group of test chips are used for corresponding to a preset test working condition;

the data determining module 220 is configured to determine whether the statistical data of the defective chips conforms to the detection rule of the defective chips in the corresponding round according to the statistical data of the defective chips determined in the preset round, specifically, determine whether the statistical data of the defective chips in each group of test chips conforms to the detection rule of the defective chips in the corresponding round one by one according to the statistical data of the defective chips determined in the preset round;

and an alternative determining module 230, configured to determine, if the statistical data of the defective chip conforms to the detection rule of the defective chip in the corresponding round, that the preset test condition corresponding to the test chip is an alternative test condition.

Optionally, the preset test condition includes at least one of the following conditions: temperature, voltage, duration, and test vector.

Optionally, the cycle testing module 210 is configured to select and remove a defective chip in the test chips, and includes:

and removing the defective chip.

Embodiments of the present application further provide a test system, and in some embodiments, the test system may include a chip test device, where the structure of the chip test device may be as shown in fig. 1, and the chip test device may be configured to execute the method for determining a chip test condition provided in the embodiments of the present application.

An embodiment of the present application further provides a computer device, where the computer device may include: at least one memory and at least one processor; the memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the method for determining the chip test condition provided by the embodiment of the application.

The embodiment of the application provides a storage medium, wherein the storage medium stores one or more computer-executable instructions, and the one or more computer-executable instructions are used for executing the method for determining the chip test working condition.

While various embodiments have been described above in connection with what are presently considered to be the embodiments of the disclosure, the various alternatives described in the various embodiments can be readily combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered to be the disclosed and disclosed embodiments of the disclosure.

Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and it is intended that the scope of the present disclosure be defined by the appended claims.

Claims

1. A method for determining a test condition of a chip, comprising:

obtaining a test chip;

2. The method according to claim 1, wherein the determining whether the statistical data of the defective chips conforms to the detection rule of the defective chips in the corresponding round comprises:

3. The method for determining the test condition of the chip as claimed in claim 1, wherein the method further comprises:

4. The method for determining the testing condition of the chip according to claim 3, wherein if the statistical data of the defective chip does not conform to the detection rule of the defective chip in the corresponding round, the obtaining the testing condition to be tested comprises:

5. The method of claim 4, wherein the determining whether the predetermined testing condition is too low comprises:

if yes, the preset test working condition is too low.

6. The method of claim 4, wherein the determining whether the predetermined testing condition is too low comprises:

if yes, the preset test working condition is too low.

7. The method for determining the testing condition of the chip according to claim 3, wherein the obtaining the testing condition to be tested comprises:

8. The method of claim 7, wherein the determining whether the predetermined testing condition is too high comprises:

if so, the preset test working condition is too high.

9. The method of claim 7, wherein the determining whether the predetermined testing condition is too high comprises:

if so, the preset test working condition is too high.

10. The method for determining the test condition of the chip according to claim 1, wherein after determining the preset test condition as the alternative test condition, the method further comprises:

performing a chip life test on the test chip;

11. The method for determining the chip testing condition according to claim 10, wherein the performing a chip life test on the test chip comprises:

12. The method according to claim 10, wherein if there are a plurality of target test conditions, the target test condition with the shortest test time among the target test conditions is selected as an optimal test condition.

13. The method for determining the test condition of the chip according to claim 1, wherein the preset test condition is a plurality of test conditions;

14. The method for determining the test condition of the chip according to claim 1, wherein the preset test condition comprises at least one of the following conditions:

temperature, voltage, duration, and test vector.

15. The method for determining the test condition of the chip according to claim 1, wherein the selecting and removing the defective chip from the test chip comprises:

and removing the defective chip.

16. An apparatus for determining a test condition of a chip, the apparatus comprising:

the chip acquisition module is used for acquiring a test chip;

17. A test system, characterized in that the test system comprises a chip test device configured to execute the method for determining the chip test condition as claimed in any one of claims 1 to 15.

18. A computer device, comprising: at least one memory and at least one processor; the memory stores one or more computer-executable instructions that are invoked by the processor to perform the method of determining chip test conditions of any of claims 1 to 15.

19. A storage medium storing one or more computer-executable instructions for performing a method of determining a chip test condition as claimed in any one of claims 1 to 15.