CN113739992B - Air tightness detection method for semiconductor machine - Google Patents
Air tightness detection method for semiconductor machine Download PDFInfo
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- CN113739992B CN113739992B CN202110928992.4A CN202110928992A CN113739992B CN 113739992 B CN113739992 B CN 113739992B CN 202110928992 A CN202110928992 A CN 202110928992A CN 113739992 B CN113739992 B CN 113739992B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 137
- 238000001514 detection method Methods 0.000 title abstract description 18
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- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000009257 reactivity Effects 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000001603 reducing effect Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
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- 229910052751 metal Inorganic materials 0.000 claims description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
- G01M3/00—Investigating fluid-tightness of structures
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The application relates to an air tightness detection method of a semiconductor machine. The method for detecting the air tightness of the semiconductor machine comprises the following steps: forming a test chip, wherein the test chip comprises a substrate and a test film layer positioned on the substrate, the test film layer is provided with a test pattern, and the test film layer is provided with chemical reactivity; acquiring a first feature size of the test pattern; placing the test chip into the semiconductor machine; establishing a vacuum environment in the semiconductor machine; obtaining a second characteristic size of the test pattern taken out from the inside of the semiconductor machine; judging whether the first characteristic size is larger than the second characteristic size, and if so, confirming that the air tightness of the semiconductor machine is poor. The method shortens the time for detecting the air tightness of the semiconductor machine, reduces the cost for detecting the air tightness of the semiconductor machine, and improves the accuracy of detecting the air tightness of the semiconductor machine.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for detecting air tightness of a semiconductor machine.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor structure commonly used in electronic devices such as computers and is composed of a plurality of memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected with the word line, the source is electrically connected with the bit line, the drain is electrically connected with the capacitor, and the word line voltage on the word line can control the on and off of the transistor, so that the data information stored in the capacitor can be read through the bit line or written into the capacitor.
The semiconductor machine such as furnace tube machine is one of the important machines in the process of preparing semiconductor devices such as dynamic random access memories, and is used for forming a film layer on the surface of a semiconductor structure. The air tightness of the semiconductor machine such as the furnace machine has great influence on the semiconductor manufacturing process. When the gas tightness of the semiconductor machine such as the furnace tube machine is poor, defects can be generated in the film layer deposited on the surface of the semiconductor structure. Therefore, the inspection of the gas tightness of the semiconductor machine such as the furnace machine is an important step for ensuring the continuous and stable progress of the semiconductor process and the yield of the semiconductor structure. However, the current method for detecting the air tightness of the semiconductor machine such as the furnace tube machine is high in cost, long in test time, narrow in application range and low in detection accuracy.
Therefore, how to improve the accuracy of the air tightness detection of the semiconductor machine, reduce the cost of the air tightness detection of the semiconductor machine, shorten the time of the air tightness detection of the semiconductor machine, and ensure the yield of the semiconductor structure is a technical problem to be solved currently.
Disclosure of Invention
Some embodiments of the present application provide a method for detecting air tightness of a semiconductor machine, which is used for solving the problem of lower accuracy of air tightness detection of a current semiconductor machine, reducing the cost of air tightness detection of the semiconductor machine, and shortening the time of air tightness detection of the semiconductor machine, so as to ensure the yield of semiconductor products.
According to some embodiments of the present application, the present application provides a method for detecting air tightness of a semiconductor machine, including the following steps:
forming a test chip, wherein the test chip comprises a substrate and a test film layer positioned on the substrate, the test film layer is provided with a test pattern, and the test film layer is provided with chemical reactivity;
acquiring a first feature size of the test pattern;
placing the test chip into the semiconductor machine;
establishing a vacuum environment in the semiconductor machine;
obtaining a second characteristic size of the test pattern taken out from the inside of the semiconductor machine;
and judging whether the difference between the first characteristic size and the second characteristic size is larger than a preset value, and if so, confirming that the air tightness of the semiconductor machine is poor.
In some embodiments, the specific steps of forming the test chip include:
providing a substrate;
forming a dielectric layer covering the surface of the substrate;
and forming the test film layer covered on the surface of the dielectric layer.
In some embodiments, the specific step of forming the test film layer overlying the dielectric layer surface includes:
depositing a reducing material on the surface of the dielectric layer to form the test film layer;
and etching the test film layer to form a groove extending along the direction of the dielectric layer pointing to the substrate, and taking the groove as the test pattern.
In some embodiments, the material of the test film layer is any one or a combination of two or more of metal, metal compound, polysilicon.
In some embodiments, the material of the test film layer is polysilicon.
In some embodiments, the test film layer has a thickness of 10nm to 50nm.
In some embodiments, the number of test chips is multiple; the specific step of obtaining the first feature size of the test pattern includes:
and acquiring a plurality of first feature sizes corresponding to the plurality of test chips one by one.
In some embodiments, the specific step of placing the test chip inside the semiconductor device includes:
and a plurality of test chips are arranged in the reaction cavity in the semiconductor machine at intervals.
In some embodiments, the specific step of placing a plurality of test chips in a reaction chamber inside the semiconductor machine at intervals includes:
and placing a plurality of test chips in the reaction chamber in parallel along the axis direction of the reaction chamber.
In some embodiments, the number of test chips is 2; the specific steps of placing a plurality of test chips in a reaction chamber in the semiconductor machine at intervals include:
and respectively placing two test chips at the bottom and the top of the reaction chamber.
In some embodiments, the specific step of establishing a vacuum environment inside the machine includes:
reducing the pressure inside the semiconductor machine to be lower than a preset pressure;
and heating the inside of the semiconductor machine.
In some embodiments, the specific step of determining whether the difference between the first feature size and the second feature size is greater than a preset value comprises:
and judging that the difference value between the first characteristic size and the second characteristic size of each test chip is larger than the preset value, and if not, confirming that the air tightness of the semiconductor machine is poor.
In some embodiments, the specific step of determining whether the difference between the first feature size and the second feature size is greater than a preset value comprises:
judging whether the first characteristic size is larger than the second characteristic size, and judging whether the difference value between the first characteristic size and the second characteristic size is larger than a preset value, if so, confirming that the air tightness of the semiconductor machine is poor.
In some embodiments, the preset value is 0.1nm to 2nm.
In some embodiments, after obtaining the second feature size of the test pattern after being taken out from the semiconductor machine, the method further includes the following steps:
and removing the test film layer on the substrate.
According to the air tightness detection method for the semiconductor machine provided by the embodiments of the application, the test chip comprising the substrate and the test film layer is formed, the test film layer is provided with the test pattern, and the change condition of the characteristic size of the test pattern before and after the test chip enters the semiconductor machine is obtained, so that the air tightness of the semiconductor machine is judged. The method for detecting the air tightness of the semiconductor machine provided by some embodiments of the application is not limited to the type of the semiconductor machine, and has a wide application range.
Drawings
FIG. 1 is a flow chart of a method for detecting the air tightness of a semiconductor machine in the specific embodiment of the application;
FIG. 2A is a schematic diagram of a test chip prior to entering a semiconductor device in an embodiment of the present application;
FIG. 2B is a schematic diagram of the test chip according to the embodiment of the present application after being removed from the semiconductor device;
fig. 3 is a schematic structural diagram of a test chip placed in a semiconductor machine according to an embodiment of the present application.
Detailed Description
The following describes in detail the specific embodiments of the method for detecting the air tightness of the semiconductor machine provided in the present application with reference to the accompanying drawings.
In the embodiment, fig. 1 is a flowchart of a method for detecting air tightness of a semiconductor machine in the embodiment of the application, fig. 2A is a schematic structural diagram of a test chip before entering the semiconductor machine in the embodiment of the application, fig. 2B is a schematic structural diagram of the test chip after being taken out from the semiconductor machine in the embodiment of the application, and fig. 3 is a schematic structural diagram of the test chip after being placed inside the semiconductor machine in the embodiment of the application. As shown in fig. 1, 2A-2B and 3, the method for detecting the air tightness of the semiconductor machine comprises the following steps:
in step S11, a test chip 30 is formed, where the test chip 30 includes a substrate 20 and a test film layer 22 disposed on the substrate 20, the test film layer 22 has a test pattern 221 therein, and the test film layer 22 has chemical reactivity.
In this embodiment, the test film 22 has chemical reactivity, which means that the test film 22 is capable of chemically reacting with air, for example, capable of undergoing a redox reaction or other type of chemical reaction with one or more components in air. The test pattern 221 may be a hole, slot, or the like structure located in the test film layer 22.
In some embodiments, the specific steps of forming test chip 30 include:
providing a substrate 20;
forming a dielectric layer 21 covering the surface of the substrate 20;
the test film layer 22 is formed to cover the surface of the dielectric layer 21.
In some embodiments, the specific step of forming the test film layer 22 covering the surface of the dielectric layer 21 includes:
depositing a reducing material on the surface of the dielectric layer 21 to form the test film layer 22;
and etching the test film layer 22 to form a groove extending along the direction of the dielectric layer 21 pointing to the substrate 20, and taking the groove as the test pattern.
Specifically, the substrate 20 may be, but is not limited to, a silicon substrate, and this embodiment is described by taking the substrate 20 as a silicon substrate as an example. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The dielectric layer 21 and the test film layer 22 are both formed outside the semiconductor device under test. The dielectric layer 21 and the test film layer 22 may be sequentially deposited on the surface of the substrate 20 by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. And then, the dielectric layer 21 is used as an etching stop layer to etch the test film layer 22, so as to form the groove penetrating through the test film layer 22 along the direction perpendicular to the top surface of the substrate 20 (i.e. the surface of the substrate 20 facing the test film layer 22). The material of the dielectric layer 21 may be, but is not limited to, an oxide material, such as silicon dioxide. In order to avoid over-etching, which affects the accuracy of the measurement of the feature size of the test pattern, the dielectric layer 21 and the test film layer 22 should have a high etching selectivity, for example, the etching selectivity between the dielectric layer 21 and the test film layer 22 is greater than 3.
According to the method, the forming process of the test chip 30 is completed outside the semiconductor machine to be tested, and the forming process of the test chip 30 or the test film layer 22 does not need to be performed inside the semiconductor machine, so that on one hand, the time for testing the air tightness of the semiconductor machine is shortened, the efficiency of testing the air tightness of the semiconductor machine is improved, the shutdown time of the semiconductor machine caused by the air tightness test is reduced, and the productivity of the semiconductor machine is improved; on the other hand, the raw material gas for forming the test chip 30 or the test film layer 22 does not need to be transmitted to the inside of the semiconductor machine, so that the probability of polluting the inside of the semiconductor machine is reduced, and the time for cleaning the semiconductor machine is saved.
In this embodiment, the test film layer 22 has a single-layer structure, so as to simplify the process of forming the test chip 30. In other examples, the test film 22 may also be a multi-layer structure, for example, the test film 22 includes a plurality of sub-films stacked in a direction perpendicular to the top surface of the substrate 20 (i.e., the surface of the substrate 20 facing the test film 22), so as to improve the chemical reactivity of the test film 22, and thus improve the accuracy of the air tightness detection of the semiconductor device under test.
The reason why the test film 22 is formed of the reducing material is that if the semiconductor device is less airtight, the external air enters the semiconductor device, and the oxygen in the air is liable to react with the sidewall of the test pattern 221 having a higher reducing property, so that the feature size of the test pattern 221 is changed.
In some embodiments, the material of the test film layer 22 is any one or a combination of two or more of metal, metal compound, polysilicon. Wherein the metal compound may be, but is not limited to, a metal nitride, such as TiN.
In some embodiments, the material of the test film layer 22 is polysilicon.
The thickness of the test film 22 should not be too large, otherwise, small variations in the feature size of the test film 22 are not easily detected, thereby affecting the accuracy of the air tightness detection result. The thickness of the test film 22 is not too small, otherwise, the amount of the product generated after the reaction with the air entering the semiconductor machine is small, which also results in small variation of the feature size of the test film 22 and is not easy to be detected, thereby affecting the accuracy of the air tightness detection result. In some embodiments, the thickness H2 of the test film layer 22 is 10nm to 50nm. For example, the thickness H2 of the test film layer 22 is 10nm, 15nm, 25nm, 30nm, or 40nm. The thickness H1 of the dielectric layer 21 is 20nm to 80nm. For example, the thickness H1 of the dielectric layer 21 is 20nm, 35nm, 50nm, 60nm or 75nm.
Step S12, acquiring a first feature size CD1 of the test pattern 221.
Specifically, after the test chip 30 is formed, the first feature size CD1 of the test pattern 221 in the test chip 30 is acquired outside the semiconductor device. The specific method for obtaining the first feature size CD1 of the test pattern 221 in the test chip 30 may be selected by those skilled in the art according to actual needs, as long as a specific value of the first feature size CD1 is obtained.
In some embodiments, the number of test chips 30 is multiple; the specific step of obtaining the first feature size CD1 of the test pattern 221 includes:
a plurality of first feature sizes CD1 corresponding to a plurality of test chips 30 one by one are acquired.
Specifically, by forming a plurality of test chips 30, a plurality of test chips 30 can be simultaneously placed in the semiconductor machine, so that the air tightness of a plurality of positions in the semiconductor machine can be synchronously detected, which is helpful for further improving the efficiency of the air tightness detection of the semiconductor machine. The plural sheets in this embodiment means two or more sheets.
Step S13, placing the test chip 30 into the semiconductor machine.
The semiconductor tool may be, but is not limited to, a furnace tool. The present embodiment will be described by taking the semiconductor machine as a furnace tube machine as an example. The structure of the furnace platen is shown in fig. 3, and includes a housing 33, a furnace chamber 31 formed by surrounding the housing 33, a plurality of wafer slots located in the furnace chamber 31, and a bottom cover 32 located at the bottom of the furnace chamber 31 for closing the furnace chamber 31. The wafer grooves are used for bearing wafers, and a plurality of wafer grooves are arranged in parallel along the axis direction of the furnace tube chamber 31. The test chip 30 may be transferred into the furnace chamber 31 of the furnace platen by a transfer mechanism such as a robot arm, and placed on the wafer bath.
In some embodiments, the specific steps of placing the test chip 30 inside the semiconductor device include:
a plurality of test chips 30 are placed in a reaction chamber inside the semiconductor machine at intervals.
In some embodiments, the steps of placing a plurality of test chips 30 in a reaction chamber inside the semiconductor device at intervals include:
a plurality of test chips 30 are placed in parallel in the reaction chamber along the axis direction of the reaction chamber.
In some embodiments, the number of test chips 30 is 2; the specific steps of placing a plurality of test chips 30 in a reaction chamber inside the semiconductor machine at intervals include:
two test chips 30 are placed on the bottom and top of the reaction chamber, respectively.
The following description will take the semiconductor machine as a furnace tube machine and the number of the test chips 30 as 2 as an example. One of the test chips 30 is placed in the wafer groove at the bottom layer in the furnace chamber 31, and the other test chip 30 is placed in the wafer groove at the top layer in the furnace chamber 31 by a transmission structure such as a mechanical arm, as shown in fig. 3. The bottom of the furnace chamber 31 is a passage for the wafer to enter and exit, and after the wafer enters the furnace chamber 31, the bottom cover 32 closes the furnace chamber 31, so that the bottom of the furnace chamber 31 is a portion that is liable to affect the air tightness of the whole furnace chamber. The top of the furnace chamber 31 is a channel for discharging waste gas, and is also a portion that is liable to affect the air tightness of the whole furnace chamber. Two test chips 30 are respectively arranged at the bottom and the top of the furnace tube chamber 31, so that the air tightness conditions of a plurality of positions in the furnace tube chamber 31 can be synchronously detected, and the efficiency of detecting the air tightness of the semiconductor machine is further improved.
Step S14, a vacuum environment is established inside the semiconductor machine.
In some embodiments, the specific step of establishing a vacuum environment inside the machine includes:
reducing the pressure inside the semiconductor machine to be lower than a preset pressure;
and heating the inside of the semiconductor machine.
For example, after the test chip 30 is placed in the furnace chamber 31, the furnace chamber 31 is closed by the bottom cover 32. Then, the furnace tube chamber 31 is pumped down, so that the pressure in the furnace tube chamber 31 is reduced below the preset pressure. Wherein the preset pressure is 1torr. Then, the pumping of the furnace chamber 31 is stopped, the furnace chamber 31 is heated, all valve elements connected to the furnace chamber 31 are closed, and the furnace chamber is maintained for a predetermined time (for example, 1to 10 minutes).
Step S15, obtaining the second feature size CD2 of the test pattern 221 after being taken out from the semiconductor device.
Step S16, determining whether the difference between the first feature size CD1 and the second feature size CD2 is greater than a preset value, if yes, determining that the air tightness of the semiconductor machine is poor.
In some embodiments, the specific step of determining whether the difference between the first feature size CD1 and the second feature size CD2 is greater than a preset value includes:
judging whether the difference between the first feature size CD1 and the second feature size CD2 of each test chip 30 is larger than the preset value, and if not, confirming that the air tightness of the semiconductor machine is poor.
In some embodiments, the specific step of determining whether the difference between the first feature size CD1 and the second feature size CD2 is greater than a preset value includes:
judging whether the first feature size CD1 is larger than the second feature size CD2 or not, and determining that the difference between the first feature size CD1 and the second feature size CD2 is larger than a preset value, if yes, determining that the air tightness of the semiconductor machine is poor.
In some embodiments, the preset value is 0.1nm to 2nm. For example, the preset value is 0.1nm, 0.5nm, 1nm, or 1.5nm.
The following description will take the example in which the material of the test film layer 22 is polysilicon and the semiconductor machine is a furnace machine. When the air tightness of the furnace platen is good, the step of establishing a vacuum environment inside the furnace platen is equivalent to heating the test film layer 22, and the feature size of the test pattern 221 is not changed, or the feature size is slightly changed due to the removal of impurities in the polysilicon or the difference in precision of measurement, for example, the difference between the first feature size CD1 and the second feature size CD2 is smaller than 0.1nm.
When the air tightness of the furnace platen is poor, in the process of establishing a vacuum environment inside the furnace platen and heating the furnace platen, oxygen entering the furnace platen will react with the test patterns 221 in the test film layer 22 as follows:
Si+O 2 ＝SiO 2
SiO 2 the generation of the test pattern 221 may reduce the feature size, for example, the difference between the first feature size CD1 and the second feature size CD2 may be greater than a predetermined value.
And if the air tightness of the semiconductor machine is determined to be poor, maintaining the semiconductor machine after the semiconductor machine is subjected to gas purging. After maintenance, detecting the air tightness of the semiconductor machine by a resistance value detection mode again until the first characteristic dimension CD1 is larger than the second characteristic dimension CD2 and the difference between the first characteristic dimension CD1 and the second characteristic dimension CD2 is larger than the preset value.
In some embodiments, after obtaining the second feature size CD2 of the test pattern 221 after being taken out from the semiconductor device, the method further includes the following steps:
the test film layer 22 on the substrate 20 is removed.
Specifically, after the air tightness detection of the semiconductor machine is completed, the test film layer 22 on the substrate 20 can be removed by adopting a wet cleaning manner, so that the substrate 20 can be recycled, and the cost of the air tightness detection of the semiconductor machine is further reduced. For example, when the material of the test film 22 is polysilicon, an alkaline solution (such as an ammonia solution) may be used to remove the test film 22 on the substrate 20 after the air tightness test of the semiconductor device is completed.
According to the method for detecting the air tightness of the semiconductor machine provided by the embodiment of the invention, the test chip comprising the substrate and the test film layer is formed, the test film layer is provided with the test pattern, and the change condition of the characteristic dimension of the test pattern before and after the test chip enters the semiconductor machine is obtained, so that the air tightness of the semiconductor machine is judged. The method for detecting the air tightness of the semiconductor machine provided by some embodiments of the application is not limited to the type of the semiconductor machine, and has a wide application range.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.
Claims (13)
1. The method for detecting the air tightness of the semiconductor machine is characterized by comprising the following steps:
providing a substrate;
forming a dielectric layer covering the surface of the substrate;
forming a test film layer covering the surface of the dielectric layer to form a test chip comprising a substrate and the test film layer positioned on the substrate, wherein the thickness of the test film layer is 10-50 nm, the test film layer is provided with a test pattern, the test pattern is a groove penetrating through the test film layer along the direction of the dielectric layer to the substrate, the test film layer has chemical reactivity, and the test film layer has chemical reactivity, namely, the test film layer can react with air chemically;
acquiring a first feature size of the test pattern;
placing the test chip into the semiconductor machine;
establishing a vacuum environment in the semiconductor machine;
obtaining a second characteristic size of the test pattern taken out from the inside of the semiconductor machine;
and judging whether the difference between the first characteristic size and the second characteristic size is larger than a preset value, and if so, confirming that the air tightness of the semiconductor machine is poor.
2. The method for inspecting air tightness of a semiconductor device according to claim 1, wherein the step of forming the test film layer covering the surface of the dielectric layer comprises:
depositing a reducing material on the surface of the dielectric layer to form the test film layer;
and etching the test film layer to form a groove extending along the direction of the dielectric layer pointing to the substrate, and taking the groove as the test pattern.
3. The method for detecting the air tightness of a semiconductor machine according to claim 1, wherein the material of the test film layer is any one or a combination of more than two of metal, metal compound and polysilicon.
4. The method for detecting air tightness of a semiconductor machine according to claim 1, wherein the material of the test film layer is polysilicon.
5. The method for inspecting the air tightness of a semiconductor machine according to claim 1, wherein the number of the test chips is plural; the specific step of obtaining the first feature size of the test pattern includes:
and acquiring a plurality of first feature sizes corresponding to the plurality of test chips one by one.
6. The method for inspecting the air tightness of a semiconductor device according to claim 5, wherein the step of placing the test chip inside the semiconductor device comprises:
and a plurality of test chips are arranged in the reaction cavity in the semiconductor machine at intervals.
7. The method for inspecting the air tightness of a semiconductor device according to claim 6, wherein the step of disposing the plurality of test chips at intervals in the reaction chamber inside the semiconductor device comprises:
and placing a plurality of test chips in the reaction chamber in parallel along the axis direction of the reaction chamber.
8. The method for inspecting the air tightness of a semiconductor machine according to claim 6, wherein the number of the test chips is 2; the specific steps of placing a plurality of test chips in a reaction chamber in the semiconductor machine at intervals include:
and respectively placing two test chips at the bottom and the top of the reaction chamber.
9. The method for detecting the air tightness of a semiconductor machine according to claim 1, wherein the specific step of establishing a vacuum environment inside the machine comprises:
reducing the pressure inside the semiconductor machine to be lower than a preset pressure;
and heating the inside of the semiconductor machine.
10. The method for inspecting an air tightness of a semiconductor device according to claim 6, wherein the step of determining whether the difference between the first feature size and the second feature size is greater than a predetermined value comprises:
and judging that the difference value between the first characteristic size and the second characteristic size of each test chip is larger than the preset value, and if not, confirming that the air tightness of the semiconductor machine is poor.
11. The method for inspecting the air tightness of a semiconductor machine according to claim 1, wherein the specific step of determining whether the difference between the first feature size and the second feature size is greater than a preset value comprises:
judging whether the first characteristic size is larger than the second characteristic size, and judging whether the difference value between the first characteristic size and the second characteristic size is larger than a preset value, if so, confirming that the air tightness of the semiconductor machine is poor.
12. The method for detecting the air tightness of a semiconductor machine according to claim 1, wherein the preset value is 0.1 nm-2 nm.
13. The method of claim 1, further comprising the steps of, after obtaining the second feature size of the test pattern after being extracted from the semiconductor device,:
and removing the test film layer on the substrate.
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