CN115704730A - Airtightness detection method for semiconductor machine - Google Patents

Airtightness detection method for semiconductor machine Download PDF

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Publication number
CN115704730A
CN115704730A CN202110928850.8A CN202110928850A CN115704730A CN 115704730 A CN115704730 A CN 115704730A CN 202110928850 A CN202110928850 A CN 202110928850A CN 115704730 A CN115704730 A CN 115704730A
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test
semiconductor machine
resistance
semiconductor
test chip
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钱龙
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Abstract

The application relates to the technical field of semiconductor manufacturing, in particular to a method for detecting air tightness of a semiconductor machine. The method for detecting the air tightness of the semiconductor machine comprises the following steps: forming a test chip, wherein the test chip comprises a substrate and a test film layer positioned on the substrate, and the test film layer has chemical reaction activity; acquiring a first resistance of the test chip; placing the test chip into the semiconductor machine; establishing a vacuum environment inside the semiconductor machine; obtaining a second resistor of the test chip taken out from the inside of the semiconductor machine; and judging whether the second resistance is larger than the first resistance or not, and if so, determining that the airtightness of the semiconductor machine is poor. According to the method and the device, the time for detecting the air tightness of the semiconductor machine is shortened, the cost for detecting the air tightness of the semiconductor machine is reduced, and the accuracy for detecting the air tightness of the semiconductor machine is improved.

Description

Airtightness detection method for semiconductor machine
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for detecting air tightness of a semiconductor machine.
Background
Dynamic Random Access Memory (DRAM) is a commonly used semiconductor structure in electronic devices such as computers, and is composed of a plurality of Memory cells, each of which typically includes a transistor and a capacitor. The transistor has a gate electrically connected to a word line, a source electrically connected to a bit line, and a drain electrically connected to the capacitor, wherein a word line voltage on the word line can control the transistor to be turned on and off, so that data information stored in the capacitor can be read or written into the capacitor through the bit line.
A semiconductor machine such as a furnace machine is one of important machines in the manufacturing process of semiconductor devices such as a dynamic random access memory, and is used for forming a film layer on the surface of a semiconductor structure. The airtightness of semiconductor machines such as furnace tools has a great influence on the semiconductor process. When the gas tightness of the furnace tube machine is not good, defects will be generated in the film deposited on the surface of the semiconductor structure. Therefore, the inspection of the gas tightness of the semiconductor equipment such as the furnace equipment is an important step for ensuring the continuous and stable semiconductor process and the yield of the semiconductor structure. However, the current method for detecting the gas tightness of semiconductor machines such as furnace tube machines has high cost, long testing time, narrow application range and low detection accuracy.
Therefore, how to improve the accuracy of the hermeticity test of the semiconductor device, reduce the cost of the hermeticity test of the semiconductor device, shorten the time for the hermeticity test of the semiconductor device, and ensure the yield of the semiconductor structure is a technical problem to be solved.
Disclosure of Invention
Some embodiments of the present application provide a method for detecting the air tightness of a semiconductor machine, which is used to solve the problem of low accuracy of the air tightness detection of the current semiconductor machine, reduce the cost of the air tightness detection of the semiconductor machine, and shorten the time of the air tightness detection of the semiconductor machine, so as to ensure the yield of semiconductor products.
According to some embodiments of the present application, a method for detecting the air tightness of a semiconductor machine is provided, which includes the following steps:
forming a test chip, wherein the test chip comprises a substrate and a test film layer positioned on the substrate, and the test film layer has chemical reaction activity;
acquiring a first resistance of the test chip;
placing the test chip into the semiconductor machine;
establishing a vacuum environment inside the semiconductor machine;
obtaining a second resistor of the test chip taken out from the inside of the semiconductor machine;
and judging whether the second resistance is larger than the first resistance or not, and if so, determining that the air tightness of the semiconductor machine is poor.
In some embodiments, the specific steps of forming the test chip include:
providing the substrate;
and depositing a reducing material on the surface of the substrate to form the test film layer.
In some embodiments, the reducing material is a metal material or a metal compound material.
In some embodiments, the test film layer has a thickness of 10nm to 50nm.
In some embodiments, the material of the test film layer is TiN.
In some embodiments, the step of obtaining the first resistance of the test chip includes:
and acquiring a first resistance of the test film layer in the test chip.
In some embodiments, the number of test chips is multiple; the specific steps of obtaining the first resistance of the test chip include:
and acquiring a plurality of first resistors which are in one-to-one correspondence with the plurality of test chips.
In some embodiments, the step of placing the test chip inside the semiconductor machine includes:
and placing a plurality of test chips in a reaction chamber inside the semiconductor machine at intervals.
In some embodiments, the specific steps of placing a plurality of the test chips at intervals in a reaction chamber inside the semiconductor machine include:
and placing a plurality of test chips in the reaction chamber in parallel along the axial direction of the reaction chamber.
In some embodiments, the number of test chips is 2; the specific steps of placing a plurality of test chips in a reaction chamber inside the semiconductor machine at intervals comprise:
two test chips are respectively placed at the bottom and the top of the reaction chamber.
In some embodiments, the step of establishing a vacuum environment within the tool comprises:
reducing the pressure inside the semiconductor machine to be below a preset pressure;
and heating the inside of the semiconductor machine.
In some embodiments, the preset pressure is 1torr.
In some embodiments, the specific step of determining whether the second resistance is greater than the first resistance comprises:
and judging whether the second resistance of each test chip is larger than the first resistance or not, and if not, determining that the air tightness of the semiconductor machine is poor.
In some embodiments, further comprising:
and judging whether the second resistance is larger than the first resistance or not, and if not, determining that the air tightness of the semiconductor machine is good.
In some embodiments, after obtaining the second resistance of the test chip taken out from the inside of the semiconductor machine, the method further includes the following steps:
and removing the test film layer on the substrate.
According to the method for detecting the air tightness of the semiconductor machine, the test chip comprising the substrate and the test film layer is formed, the change conditions of the resistance values of the test chip before and after entering the semiconductor machine are obtained, the air tightness of the semiconductor machine is judged, the method is simple to operate and low in test cost, the time for detecting the air tightness of the semiconductor machine is shortened, the cost for detecting the air tightness of the semiconductor machine is reduced, the accuracy for detecting the air tightness of the semiconductor machine is improved, and a foundation is laid for ensuring the yield of semiconductor products. The method for detecting the airtightness of the semiconductor machine, provided in some embodiments of the present application, is not limited by the type of the semiconductor machine, and has a wide application range.
Drawings
FIG. 1 is a flowchart of a method for detecting the air tightness of a semiconductor machine according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a test chip according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a semiconductor device after a test chip is placed inside the semiconductor device in the embodiment of the present application.
Detailed Description
The following describes in detail a specific embodiment of the method for detecting the air tightness of a semiconductor machine according to the present application with reference to the accompanying drawings.
The present embodiment provides a method for detecting the air tightness of a semiconductor machine, where fig. 1 is a flowchart of a method for detecting the air tightness of a semiconductor machine in the present embodiment, fig. 2 is a schematic structural diagram of a test chip in the present embodiment, and fig. 3 is a schematic structural diagram of a test chip placed inside a semiconductor machine in the present embodiment. As shown in fig. 1-3, the method for detecting the hermeticity of a semiconductor machine comprises the following steps:
step S11, forming a test chip 30, wherein the test chip 30 comprises a substrate 20 and a test film layer 21 positioned on the substrate 20, and the test film layer 21 has chemical reactivity.
In this embodiment, the test film layer 21 is chemically reactive, which means that the test film layer 21 can chemically react with air, for example, can react with one or more components in air by oxidation-reduction reaction or other types of chemical reaction.
In some embodiments, the specific steps of forming the test chip 30 include:
providing the substrate 20;
and depositing a reducing material on the surface of the substrate 20 to form the test film layer 21.
Specifically, the substrate 20 may be, but is not limited to, a silicon substrate, and the substrate 20 is exemplified as the silicon substrate in the present embodiment. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. Before the test chip 30 enters the inside of the semiconductor machine to be tested, depositing a reducing material on the surface of the substrate 20 by adopting a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process outside the semiconductor machine to be tested to form the test film layer 21.
In the present embodiment, the formation process of the test chip 30 is completed outside the semiconductor machine to be tested, and the formation process of the test chip 30 or the test film 21 is not required to be performed inside the semiconductor machine, so that on one hand, the time for the airtightness test of the semiconductor machine is shortened, the efficiency for the airtightness test of the semiconductor machine is improved, the downtime of the semiconductor machine due to the airtightness test is reduced, and the productivity of the semiconductor machine is improved; on the other hand, raw material gas for forming the test chip 30 or the test film 21 does not need to be transmitted to the inside of the semiconductor machine, so that the probability of pollution to the inside of the semiconductor machine is reduced, and the time for cleaning the semiconductor machine is saved.
In the present embodiment, the testing film 21 has a single-layer structure to simplify the formation process of the testing chip 30. In other examples, the testing film 21 may also be a multi-layer structure, for example, the testing film 21 includes a plurality of sub-films stacked along a direction perpendicular to the top surface of the substrate 20 (i.e., the surface of the substrate 20 facing the testing film 21), so as to improve the chemical reactivity of the testing film 21, and thus improve the accuracy of the hermetic sealing detection of the semiconductor machine to be tested.
In some embodiments, the reducing material is a metal material or a metal compound material.
Specifically, the metal material or the metal compound material has high reducibility, and if the airtightness of the semiconductor machine is poor, external air enters the semiconductor machine, and oxygen in the air easily reacts with the metal material or the metal compound material having high reducibility, so that the resistance of the test chip 30 or the test film layer 21 is changed. Wherein the metal compound material may be, but is not limited to, a metal nitride material.
In some embodiments, the material of the test film layer 21 is TiN.
The thickness of the test film layer 21 should not be too large, otherwise, the small change of the resistance of the test film layer 21 is not easy to detect, thereby affecting the accuracy of the air tightness detection result. The thickness of the testing film layer 21 is not too small, otherwise, the amount of the product generated after the reaction with the air entering the semiconductor machine is small, the resistance change of the testing film layer 21 is small and is difficult to detect, and the accuracy of the air tightness detection result is also affected. In some embodiments, the thickness of the test film layer 21 is 10nm to 50nm. For example, the thickness H of the test film layer 21 is 10nm, 15nm, 25nm, 35nm, or 40nm.
Step S12, obtain the first resistance of the test chip 30.
In some embodiments, the specific step of obtaining the first resistance of the test chip 30 includes:
a first resistance of the test film layer 21 in the test chip 30 is obtained.
Specifically, after the test chip 30 is formed, the sheet resistance of the test film 21 in the test chip 30 is obtained outside the semiconductor machine as the first resistance. The specific method for obtaining the square resistance of the test film layer 21 in the test chip 30 can be selected by those skilled in the art according to actual needs, as long as the resistance of the first resistor can be obtained.
In other embodiments, the resistance of the test chip 30 may be directly obtained, and the resistance of the entire test chip 30 may be used as the first resistance, so as to simplify the obtaining operation of the first resistance.
In some embodiments, the number of test chips 30 is multiple; the specific steps of obtaining the first resistance of the test chip 30 include:
a plurality of the first resistors corresponding to the plurality of test chips 30 one to one are obtained.
Specifically, by forming a plurality of test chips 30, a plurality of test chips 30 can be subsequently placed inside the semiconductor machine at the same time, so that the airtightness of a plurality of positions inside the semiconductor machine can be synchronously detected, which is beneficial to further improving the airtightness detection efficiency of the semiconductor machine. The plurality of sheets in the present embodiment means two or more sheets.
Step S13, placing the test chip 30 into the semiconductor machine.
The semiconductor machine may be, but is not limited to, a furnace machine. The present embodiment is described by taking the semiconductor machine as a furnace machine as an example. The furnace tube platform has a structure as shown in fig. 3, and includes a shell 33, a furnace tube chamber 31 formed by the shell 33, a plurality of wafer grooves located in the furnace tube chamber 31, and a bottom cover 32 located at the bottom of the furnace tube chamber 31 and used for sealing the furnace tube chamber 31. The wafer grooves are used for bearing wafers, and the wafer grooves are arranged in parallel along the axis direction of the furnace tube chamber 31. The test chip 30 may be transferred to the furnace chamber 31 of the furnace platform by a transfer structure such as a robot arm, and placed on the wafer groove.
In some embodiments, the specific steps of placing the test chip 30 inside the semiconductor machine include:
a plurality of test chips 30 are placed in the reaction chamber inside the semiconductor machine at intervals.
In some embodiments, the specific steps of placing a plurality of test chips 30 at intervals in a reaction chamber inside the semiconductor machine include:
a plurality of test chips 30 are placed in parallel in the reaction chamber along the axial direction of the reaction chamber.
In some embodiments, the number of test chips 30 is 2; the specific steps of placing a plurality of test chips 30 at intervals in the reaction chamber inside the semiconductor machine include:
two pieces of the test chip 30 are placed at the bottom and the top of the reaction chamber, respectively.
The semiconductor machine is a furnace machine, and the number of the test chips 30 is 2. One of the test chips 30 is placed in the wafer groove at the bottommost layer in the furnace tube chamber 31, and the other test chip 30 is placed in the wafer groove at the topmost layer in the furnace tube chamber 31 by a transmission structure such as a mechanical arm, as shown in fig. 3. This is because the bottom of the furnace chamber 31 is a passage for wafer to enter and exit, and after the wafer enters the furnace chamber 31, the bottom cover 32 closes the furnace chamber 31, so the bottom of the furnace chamber 31 is a part that is liable to affect the airtightness of the whole furnace chamber. The top of the furnace tube chamber 31 is a channel for discharging the waste gas, and is also a part which is liable to affect the air tightness of the whole furnace tube chamber. The two test chips 30 are respectively placed at the bottom and the top of the furnace tube chamber 31, so that the airtightness conditions of multiple positions in the furnace tube chamber 31 can be synchronously detected, and the airtightness detection efficiency of the semiconductor machine table can be further improved.
Step S14, establishing a vacuum environment inside the semiconductor machine.
In some embodiments, the step of establishing a vacuum environment within the tool comprises:
reducing the pressure inside the semiconductor machine to be below a preset pressure;
and heating the inside of the semiconductor machine.
In some embodiments, the preset pressure is 1torr.
For example, after the test chip 30 is placed in the furnace chamber 31, the furnace chamber 31 is closed by the bottom cover 32. Then, the furnace chamber 31 is evacuated, so that the pressure in the furnace chamber 31 is reduced below the preset pressure. Next, the furnace tube chamber 31 is stopped from being evacuated, the furnace tube chamber 31 is heated, all the valves connected to the furnace tube chamber 31 are closed, and a preset time (for example, 1 minute to 10 minutes) is maintained.
Step S15, obtaining the second resistor of the test chip 30 taken out from the inside of the semiconductor machine.
And S16, judging whether the second resistor is larger than the first resistor or not, and if so, confirming that the air tightness of the semiconductor machine is poor.
In some embodiments, the specific step of determining whether the second resistance is greater than the first resistance includes:
and judging whether the second resistance of each test chip 30 is greater than the first resistance, and if not, determining that the airtightness of the semiconductor machine is poor.
In some embodiments, the method for detecting the hermeticity of the semiconductor machine further comprises:
and judging whether the second resistance is larger than the first resistance or not, and if not, determining that the air tightness of the semiconductor machine is good.
The following description will be given by taking the example that the material of the test film layer 21 is TiN and the semiconductor machine is a furnace machine. When the furnace tube stage has good gas tightness, the step of establishing a vacuum environment inside the furnace tube stage is equivalent to heating the test film layer 21, and removing impurity elements in the test film layer 21, such as one or more of chlorine, carbon, and oxygen, so that the resistance of the test film layer 21 is reduced, i.e., the second resistance is smaller than the first resistance. If the purity of the test film layer 21 is high and the test film layer does not contain impurity elements, the second resistance is equal to the first resistance.
When the gas tightness of the furnace tube platform is poor, in the process of establishing a vacuum environment inside the furnace tube platform and heating the furnace tube platform, oxygen entering the furnace tube platform and the test film layer 21 react as follows:
2TiN+2O 2 ＝2TiO 2 +N 2
TiO 2 is generated such that the resistance of the test film layer 21 isIncreasing, i.e. making the second resistance larger than the first resistance.
And if the gas tightness of the semiconductor machine is determined to be poor, maintaining the semiconductor machine after performing gas purging on the semiconductor machine. After maintenance, the airtightness of the semiconductor machine is detected again in a resistance value detection mode until the second resistor is equal to or smaller than the first resistor.
In some embodiments, after obtaining the second resistance of the test chip taken out from the inside of the semiconductor machine, the method further includes the following steps:
the test film layer 21 on the substrate 20 is removed.
Specifically, after the airtightness detection of the semiconductor machine is completed, the test film layer 21 on the substrate 20 may be removed by wet cleaning, so as to realize the recycling of the substrate 20, thereby further reducing the cost of the airtightness detection of the semiconductor machine. For example, when the material of the test film layer 21 is TiN, an acid solution (e.g., H) may be used after the hermetic sealing test of the semiconductor machine is completed 2 SO 4 Solution) to remove the test film layer 21 on the substrate 20.
In the method for detecting the gas tightness of the semiconductor machine, the gas tightness of the semiconductor machine is judged by forming the test chip comprising the substrate and the test film layer and obtaining the change conditions of the resistance values of the test chip before and after entering the semiconductor machine, the method is simple to operate and low in test cost, the gas tightness detection time of the semiconductor machine is shortened, the gas tightness detection cost of the semiconductor machine is reduced, the gas tightness detection accuracy of the semiconductor machine is improved, and a foundation is laid for ensuring the yield of semiconductor products. The method for detecting the airtightness of the semiconductor machine, provided in some embodiments of the present application, is not limited by the type of the semiconductor machine, and has a wide application range.
The foregoing is only a preferred embodiment of the present application and it should be noted that, for a person skilled in the art, several modifications and refinements can be made without departing from the principle of the present application, and these modifications and refinements should also be regarded as the protection scope of the present application.

Claims (15)

1. A method for detecting the air tightness of a semiconductor machine is characterized by comprising the following steps:
forming a test chip, wherein the test chip comprises a substrate and a test film layer positioned on the substrate, and the test film layer has chemical reaction activity;
acquiring a first resistance of the test chip;
placing the test chip into a semiconductor machine;
establishing a vacuum environment inside the semiconductor machine;
obtaining a second resistor of the test chip taken out from the inside of the semiconductor machine;
and judging whether the second resistance is larger than the first resistance or not, and if so, determining that the airtightness of the semiconductor machine is poor.
2. The method of claim 1, wherein the step of forming the test chip comprises:
providing the substrate;
and depositing a reducing material on the surface of the substrate to form the test film layer.
3. The method of claim 2, wherein the reducing material is a metal material or a metal compound material.
4. The method of claim 1, wherein the thickness of the test film is 10nm to 50nm.
5. The method of claim 1, wherein the test film is TiN.
6. The method of claim 1, wherein the step of obtaining the first resistance of the test chip comprises:
and acquiring a first resistance of the test film layer in the test chip.
7. The method of claim 1, wherein the number of the test chips is plural; the specific steps of obtaining the first resistance of the test chip include: and acquiring a plurality of first resistors which correspond to the plurality of test chips one by one.
8. The method of claim 7, wherein the step of placing the test chip inside the semiconductor tool comprises:
and placing a plurality of test chips in a reaction chamber inside the semiconductor machine table at intervals.
9. The method as claimed in claim 8, wherein the step of placing the plurality of test chips at intervals in a reaction chamber inside the semiconductor machine comprises:
and placing a plurality of test chips in the reaction chamber in parallel along the axial direction of the reaction chamber.
10. The method as claimed in claim 8, wherein the number of the test chips is 2; the specific steps of placing a plurality of test chips in a reaction chamber inside the semiconductor machine at intervals comprise:
two test chips are respectively placed at the bottom and the top of the reaction chamber.
11. The method of claim 1, wherein the step of establishing a vacuum environment within the tool comprises:
reducing the pressure inside the semiconductor machine to be below a preset pressure;
and heating the inside of the semiconductor machine.
12. The method of claim 11, wherein the predetermined pressure is 1torr.
13. The method of claim 8, wherein the step of determining whether the second resistance is greater than the first resistance comprises:
and judging whether the second resistance of each test chip is larger than the first resistance or not, and if not, determining that the air tightness of the semiconductor machine is poor.
14. The method of claim 1, further comprising:
and judging whether the second resistance is larger than the first resistance or not, and if not, determining that the airtightness of the semiconductor machine is good.
15. The method of claim 1, further comprising the following steps after obtaining the second resistance of the test chip taken out from the inside of the semiconductor machine:
and removing the test film layer on the substrate.
CN202110928850.8A 2021-08-13 2021-08-13 Airtightness detection method for semiconductor machine Pending CN115704730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110928850.8A CN115704730A (en) 2021-08-13 2021-08-13 Airtightness detection method for semiconductor machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110928850.8A CN115704730A (en) 2021-08-13 2021-08-13 Airtightness detection method for semiconductor machine

Publications (1)

Publication Number Publication Date
CN115704730A true CN115704730A (en) 2023-02-17

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Application Number Title Priority Date Filing Date
CN202110928850.8A Pending CN115704730A (en) 2021-08-13 2021-08-13 Airtightness detection method for semiconductor machine

Country Status (1)

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