CN113726159A

CN113726159A - Buck converter and electronic device

Info

Publication number: CN113726159A
Application number: CN202110996099.5A
Authority: CN
Inventors: 王强; 王侠; 刘富梅; 张树春; 李润德
Original assignee: Silicon Content Technology Beijing Co ltd
Current assignee: Silicon Content Technology Beijing Co ltd
Priority date: 2021-08-27
Filing date: 2021-08-27
Publication date: 2021-11-30
Anticipated expiration: 2041-08-27
Also published as: CN113726159B

Abstract

The present disclosure provides a buck converter and an electronic apparatus. The buck converter includes: a step-down circuit including a first switch and a second switch connected in series between an input voltage and a first reference voltage, and configured to step down the input voltage to an output voltage by alternately turning on the first switch and the second switch; a current detector coupled to the voltage-reducing circuit and configured to detect a current flowing through the voltage-reducing circuit and generate a current detection signal indicative of the current; and a control circuit coupled to the current detector and the voltage-dropping circuit and configured to control the first switch and the second switch based on the current detection signal; and reducing a number of times the first switch is turned on before the buck converter enters a pulse-skip mode in response to a change in the output voltage, wherein during the pulse-skip mode the first switch remains off. By reducing the number of times the first switch is turned on before the buck converter enters the pulse skipping mode, ripple of the output voltage can be effectively reduced.

Description

Buck converter and electronic device

Technical Field

The present disclosure relates to electronic circuits, and more particularly, to buck converters.

Background

Buck converters are widely used in various electronic devices. These electronic devices as loads have increasingly high requirements for the stability of the operating voltage, and therefore ripple control of the output voltage of the buck converter is particularly important. The buck converter converts an input voltage of the power supply into an output voltage suitable for the load to work so that the load works normally.

Buck converters generally achieve the purpose of stabilizing the output voltage of the power converter by means of a negative feedback control loop. When the current through the load is small, i.e., light, the buck converter operates in Discontinuous Conduction Mode (DCM) to achieve the purpose of stabilizing the output voltage. For example, the buck converter may employ a Pulse Frequency Modulation (PFM) mode or a pulse skip cycle modulation (PSM) mode. In a buck converter employing PSM mode, the buck converter may enter a pulse skipping mode in response to a control signal to stabilize the output voltage by skipping one or more switching operations. Compared with PFM, PSM has faster response speed and higher conversion efficiency. However, since the compensation network of the system loop may cause a phase delay, the buck converter may have an additional switching operation before switching to the pulse skipping mode, resulting in a large ripple of the output voltage, which is undesirable for the electronic device.

Disclosure of Invention

In order to reduce ripple of an output voltage of a buck converter, the present disclosure provides a buck converter.

In one aspect of the present disclosure, a buck converter is provided. The buck converter includes a buck circuit, a current detector, and a control circuit. The step-down circuit includes a first switch and a second switch connected in series between an input voltage and a first reference voltage, and is configured to step down the input voltage to an output voltage by alternately turning on the first switch and the second switch. The current detector is coupled to the voltage-reducing circuit and configured to detect a current flowing through the voltage-reducing circuit and generate a current detection signal indicative of the current. A control circuit is coupled to the current detector and the buck circuit, the control circuit configured to reduce a number of times the first switch is turned on before the buck converter enters a pulse-skip mode in response to a change in the output voltage, wherein the first switch (Q1) remains off during the pulse-skip mode.

In a second aspect of the present disclosure, an electronic device is provided. The electronic device comprises a power supply device and a buck converter according to the first aspect, the buck converter being powered by the power supply device.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Drawings

The above and other objects, structures and features of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

FIG. 1 shows a schematic waveform timing diagram of a conventional buck converter;

FIG. 2 illustrates an environmental schematic in which a buck converter may be implemented in accordance with an embodiment of the present disclosure;

FIG. 3 shows a schematic block diagram of a buck converter according to one embodiment of the present disclosure;

FIG. 4 shows a schematic circuit diagram of a voltage step-down circuit and a current detector according to one embodiment of the present disclosure;

fig. 5 shows a schematic circuit diagram of a control circuit according to a first embodiment of the present disclosure;

FIG. 6 shows a schematic circuit diagram of a regulated current generating circuit and an oscillator circuit according to a first embodiment of the present disclosure;

fig. 7 shows a schematic circuit diagram of a control circuit according to a second embodiment of the present disclosure;

fig. 8 shows a schematic circuit diagram of a control circuit according to a third embodiment of the present disclosure;

fig. 9 shows a schematic circuit diagram of an oscillator circuit according to a third embodiment of the present disclosure; and

fig. 10 shows a schematic waveform timing diagram of a buck converter according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure. It may be evident in some or all instances that any of the embodiments described below may be practiced without the specific design details described below. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

In the description of the embodiments of the present disclosure, the words "comprise" and variations such as "comprises" and "comprising" should be understood to be open-ended, i.e., "including but not limited to. The expression "based on" should be understood as "based at least in part on". The expression "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The expressions "first", "second", etc. may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As described above, the ripple of the output voltage of the buck converter is related to the switching operation of the buck converter. The conventional buck converter may have an extra switching operation before switching to the pulse skipping mode, which may result in a large ripple of the output voltage, which is not favorable for the normal operation of the load. For example, fig. 1 shows a schematic waveform timing diagram of a conventional buck converter. At normal step-down conversionIn the apparatus, a clock signal CLK inside a control system has a fixed frequency. There may be one or more additional switching operations 110 of the switch for controlling the buck conversion before the buck converter enters the pulse skipping mode, which will result in the output voltage V_OUTUnstable, deviated from the predetermined output voltage V_REF0. For example, it may result in an output voltage V_OUTA ripple 120 is generated.

In an embodiment of the present disclosure, an improved buck converter is provided that is capable of adjusting the frequency of a clock signal based on a signal that varies with changes in the output voltage. By reducing the frequency of the clock signal in response to an increase in the output voltage, embodiments of the present disclosure can reduce the number of additional switching operations of the buck converter before entering the pulse skipping mode, thereby reducing the ripple of the output voltage for the load to operate properly.

Fig. 2 shows an environmental schematic of the buck converter 10 according to one embodiment of the present disclosure. The electronic device 1 includes a power supply device 2 and a buck converter 10. In one embodiment, the buck converter 10 may be configured to provide an operating voltage to a load 6, such as a smart meter. The buck converter 10 may be powered by the power supply 2. The supply device 2 may be, for example, a transformer connected to the mains and outputting a substantially constant direct supply voltage V_IN. Supply voltage V_INIs stepped down to a dc output voltage V via a buck converter 10_OUT. When the switch 4 is turned on, the voltage V is output_OUTIs supplied to the load 6. In some cases, the load 6 may have a high requirement for stability of the operating voltage. For example, as shown in fig. 1 above, it is desirable to reduce ripple. Therefore, it is desirable for the buck converter 10 to provide a stable output voltage V_OUT。

Fig. 3 shows a schematic block diagram of the buck converter 10 according to an embodiment. The buck converter 10 includes a buck circuit 12, a current detector 14, a control circuit 16, and a reference voltage generation circuit 18.

In one embodiment, the voltage reduction circuit 12 is configured to reduce the input voltage V from the power supply 2_INReduced pressure to be provided to the negativeOutput voltage V of load 6_OUT. The current detector 14 is coupled to the voltage-reducing circuit 12, and is configured to detect a current flowing through the voltage-reducing circuit 12 and generate a current detection signal, such as a sampling voltage V, representing the current_S. It can be understood that the sampling voltage V_SMay be proportional to the current flowing through the voltage dropping circuit 12 and may reach the peak of the sampled voltage when the current reaches the peak current. Although here the voltage V is sampled_SThe current sensing is shown in form, but this is merely illustrative and not limiting on the scope of the disclosure. Proportional current may also be used, for example, by proportionally sampling a portion of the current flowing through the buck circuit 12 for detection.

The control circuit 16 is coupled to the current detector 14 and the voltage reduction circuit 12, and is configured to be based on the sampled voltage V_SAnd with the output voltage V_OUTProportional feedback voltage V_FBTo control the step-down of the step-down circuit 12. Reference voltage generation circuit 18 is coupled to control circuit 16 and is configured to provide a reference voltage required by control circuit 16.

Fig. 4 shows a schematic circuit diagram of the voltage step-down circuit 12 and the current detector 14 according to one embodiment of the present disclosure. In the embodiment of fig. 4, the voltage step-down circuit 12 includes a first switch Q1, a second switch Q2, an inductor L, and a capacitor C1. In one embodiment, the first switch Q1 may be a field effect transistor. Alternatively, the first switch Q1 may be a bipolar transistor. In some embodiments, the first switch Q1 may also include a diode connected in parallel with a bipolar transistor or a field effect transistor. In one embodiment, the second switch Q2 may be a field effect transistor. Alternatively, the second switch Q2 may be a diode, a bipolar transistor, or a field effect transistor, or a switch formed by a combination of one or more of the above. An inductor L is coupled between an intermediate point between the first switch Q1 and the second switch Q2 and the output voltage V_OUTIn the meantime. Capacitor C1 is coupled at output voltage V_OUTAnd ground GND. The inductor L and the capacitor C1 constitute a filter circuit, and are connected to the output terminal of the voltage-reducing circuit 12 to supply the output voltage V to the load_OUT. The first switch Q1 and the second switch Q2 are on one cycleResponsive to control signals SW from control circuit 16₁And SW₂And alternately turned on to achieve voltage reduction.

Specifically, when the first switch Q1 is turned on, the input voltage V_INCharging inductor L and capacitor C1 and supplying power to the load. During this time, the second switch Q2 is turned off, and the current flowing through the inductor L is equal to the current flowing through the first switch Q1, and gradually increases as time passes. The current detector 14 supplies a sampling voltage V proportional to the current to the control circuit 16_S. Control circuit 16 is based on sampled voltage V_SAnd with the output voltage V_OUTProportional feedback voltage V_FBWhile leaving the first switch Q1 off and the second switch Q2 on. When the second switch Q2 is turned on, the inductor L and the capacitor C1 supply power to the load, and the current flowing through the inductor L gradually decreases.

When passing through the current I of the load_LOADAt larger, i.e. heavy loads, the buck converter 10 operates in Continuous Conduction Mode (CCM). Specifically, the first switch Q1 has an on time D x T, D indicating the duty cycle and T indicating the cycle time. In one switching cycle, the first switch Q1 and the second switch Q2 are in a complementary relationship in terms of conduction logic, so that the second switch Q1 is on for (1-D) × T. In the case where the step-down operation reaches the steady state, when the first switch Q1 is turned on, the current through the inductor L increases linearly, and the voltage drop across the inductor L is V_IN-V_OUT(ii) a When the second switch Q2 is turned on, the current through the inductor L decreases linearly and the voltage drop across the inductor L is V_OUT. The voltage-second balance is reached across the inductor L, in which case the input voltage V_INAnd an output voltage V_OUTHas the following relationship:

(V_IN-V_OUT)*D＝V_OUT*(1-D) (1)

where D represents the duty cycle of the first switch Q1.

Equation (1) can be rewritten as the following equation (2)

V_OUT＝D*V_IN (2)

In the continuous conduction mode, the switching frequency of the switches Q1 and Q2 is controlled by the control system 16The frequency of the clock signal of the section. The peak current of the current through the inductor L is IL_PEAKThe on-time D × T of the first switch Q1 and the peak current IL_PEAKIs in direct proportion. With a fixed frequency of the clock signal, when the current I through the load is constant_LOADWhen decreasing, the duty cycle D of the first switch Q1 decreases, resulting in a peak current IL_PEAKAnd decreases.

Since the peak current of the current through the inductor L is IL_PEAKThere is a minimum value, therefore when the current I through the load is_LOADWhen the peak current IL is reduced below a certain value_PEAKRemains unchanged, resulting in an output voltage V_OUTDeviates from the preset output voltage V_REF0. At this time, the buck converter 10 in PSM mode may enter pulse skipping mode. Specifically, the control circuit 16 may be based on the feedback voltage V_FBAnd a reference voltage V_REF1The difference between to determine whether it is necessary to skip several clock cycles (i.e., to keep both switches Q1 and Q2 off) to stabilize the output voltage V_OUT. Specifically, during a first period, the first switch Q1 is on and the second switch Q2 is off for a duration D₁T, where T represents cycle time; during a second period, the first switch Q1 is off and the second switch Q2 is on for a duration D₂T; during the third period, the buck converter 10 enters the pulse-skip mode, the first switch Q1 and the second switch Q2 are both off, the voltage drop across the inductor L is zero, the capacitor C1 supplies power to the load, and the pulse-skip mode has a duration of (1-D)₁-D₂)*T。

In a conventional buck converter, due to a certain signal response delay inside the control circuit, the buck converter may not be switched to the pulse skipping mode in time, so that additional first and second periods occur. In other words, there may be one or more additional switching operations, such as switching operation 110 in fig. 1, before the buck converter enters the pulse-skipping mode, which will result in the output voltage V_OUTIs unstable. When the frequency of the clock signal inside the control system is high, the output voltage V_OUTThe ripple of (a) will be more pronounced.

By the embodiments of the present disclosure described below in conjunction with fig. 5-9, the output voltage V can be significantly reduced_OUTThe ripple of (3).

Fig. 5 shows a schematic circuit diagram of the control circuit 16 according to the first embodiment of the present disclosure. The control circuit 16 includes a mode control circuit 31 and a control signal generator 32, and is configured to respond to the output voltage V_OUTTo reduce the number of times the first switch Q1 is turned on before the buck converter 10 enters the pulse skipping mode. The mode control circuit 31 is coupled to the step-down circuit 12 and the current detector 14, and is configured to detect the output voltage V based on the current detection signal and the output voltage V_OUTGenerating a clock signal CLK and a pulse width modulation signal S_PWMAnd a pulse skipping signal SKIP. In one embodiment, the mode control circuit 31 is further configured to respond to the output voltage V_OUTChanges in the clock signal CLK to change the frequency of the clock signal CLK. The control signal generator 32 is coupled to the voltage-reducing circuit 12 and the mode control circuit 31, and is configured to modulate the signal S based on the clock signal CLK and the pulse width modulation signal S_PWMAnd the pulse skipping signal SKIP to generate the first control signal SW₁And a second control signal SW₂To control the on and off of the first switch Q1 and the second switch Q2, respectively. The first switch control signal SW1 is used to control the first switch Q1 to turn on and off, and the second switch control signal SW2 is used to control the second switch Q2 to turn on and off. The control signal generator 32 may be further configured to cause the buck converter 10 to enter the pulse-SKIP mode in response to the pulse-SKIP signal SKIP being high, thereby causing the first switch Q1 to remain off.

The mode control circuit 31 includes a compensation voltage generation circuit 36, an oscillator circuit 33, a Pulse Width Modulation (PWM) signal generator 37, a pulse skipping signal generator 35, and a regulation current generation circuit 34.

The compensation voltage generation circuit 36 is coupled to the step-down circuit 12 and is configured to output a voltage V based on the sum_OUTProportional feedback voltage V_FBAnd a first reference voltage V_REF1The difference between them to generate a compensation voltage V_COMP. For example, by a voltage divider networkObtain a feedback voltage V_FB. In one example, the voltage divider network includes a voltage divider coupled at an output voltage V_OUTAnd a first resistor R1 and a second resistor R2 between ground. Feedback voltage V_FBFor example, the voltage drop across the second resistor R2. By setting the resistance values of the first resistor R1 and the second resistor R2, the feedback voltage V can be set_FBAnd an output voltage V_OUTTo each other. A first reference voltage V_REF1And a predetermined output voltage V_REF0Proportional and may be generated by the reference voltage generation circuit 18.

In one embodiment, the compensation voltage generation circuit 36 may include an operational amplifier. When passing through the current I of the load_LOADAt larger, the buck converter 10 operates in Continuous Conduction Mode (CCM) with an output voltage V_OUTIs equal to the preset output voltage V_REF0The current through the load is I_LOADFeedback voltage V_FBIs equal to the first reference voltage V_REF1At this time, the compensation voltage V_COMPRemain unchanged. When passing through the current I of the load_LOADLower, may result in an output voltage V_OUTDeviates from the preset output voltage V_REF0. For example, when the output voltage V_OUTHigher than a predetermined output voltage V_REF0Time, feedback voltage V_FBHigher than the first reference voltage V_REF1The compensation voltage generation circuit 36 discharges the capacitor C2 to generate the compensation voltage V_COMPAnd correspondingly decreases. When the output voltage V is_OUTLower than a predetermined output voltage V_REF0Time, feedback voltage V_FBLower than the first reference voltage V_REF1The compensation voltage generation circuit 36 discharges the capacitor C2 to generate the compensation voltage V_COMPAnd correspondingly increases. Resistor R3 and capacitor C2 may improve the stability of the compensation loop and improve noise immunity.

The oscillator circuit 33 is configured to generate a clock signal CLK. In one embodiment, the control signal generator 32 may turn on the first switch Q1 and turn off the second switch Q2 in response to a rising edge of the clock signal CLK from the oscillator circuit 33. In one embodiment, oscillator circuit 33 may also generate a slope compensation signal V_ramp. SlopeCompensation signal V_rampIs a triangular wave signal having the same frequency and phase as the clock signal CLK. Slope compensation signal V_rampMay be added in whole or in part to the sampled voltage V_STo avoid sub-harmonic oscillations at high duty cycles and to improve noise immunity.

The PWM signal generator 37 is coupled to the current detector 14, the compensation voltage generation circuit 36, and the control signal generator 32, and may be configured to detect a signal (e.g., the sampling voltage V) based on the current from the current detector 14_S) And the compensation voltage V from the compensation voltage generating circuit 36_COMPGenerating a pulse width modulated signal S_PWM. In one embodiment, the PWM signal generator 37 may include a comparator. As shown in FIG. 5, the non-inverting input of the PWM signal generator 37 is the compensation voltage V_COMPAnd the inverting input terminal is a sampling voltage V_SAnd slope compensation signal V_rampAnd (4) summing. In other embodiments, the non-inverting input of the PWM signal generator 37 may be the sampled voltage V_SAnd slope compensation signal V_rampSum, and the inverting input is a compensation voltage V_COMP. On the rising edge of the clock signal CLK, the slope compensation signal V_rampStarts increasing with a certain slope and the first switch Q1 is turned on, so that the sampled voltage V_SAnd gradually increases. For example, when sampling the voltage V_SAnd slope compensation signal V_rampThe sum reaches a compensation voltage V_COMPTime, pulse width modulation signal S_PWMBecomes low.

In one embodiment, the control signal generator 32 may be based on the pulse width modulation signal S from the PWM signal generator 37_PWMThe first switch Q1 is turned off and the second switch Q2 is turned on. For example, when the non-inverting input terminal of the PWM signal generator 37 is the compensation voltage V_COMPAnd the inverting input terminal thereof is a sampling voltage V_SAnd slope compensation signal V_rampIn sum, the control signal generator 32 is configured to respond to the pulse width modulation signal S_PWMThe falling edge of (b) turns off the first switch Q1 and turns on the second switch Q2.

Pulse skipping signalingThe generator 35 is coupled to the compensation voltage generation circuit 36 and the control signal generator 32, and is configured to generate the compensation voltage V_COMPAnd a second reference voltage V_REF2Generates the pulse skipping signal SKIP. In one embodiment, the pulse skipping signal generator 35 may comprise a comparator having two input terminals receiving the compensation voltage V respectively_COMPAnd a second reference voltage V_REF2And its output provides a pulse skipping signal SKIP. Second reference voltage V_REF2May be generated by the reference voltage generating circuit 18.

In one embodiment, the control signal generator 32 may cause the buck converter 10 to enter the pulse-skipping mode based on the pulse-skipping signal SKIP from the pulse-skipping signal generator 35. During the pulse skipping mode, the control signal generator 32 stops the operation of turning on the first switch Q1 based on the rising edge of the clock signal CLK. In one embodiment, when compensating for voltage V_COMPHigher than the second reference voltage V_REF2At this time, the pulse skipping signal generator 35 generates the pulse skipping signal SKIP having a low level so that the control signal generator 32 is based on the pulse width modulation signal S_PWMAnd a clock signal CLK to control the turning on and off of the first switch Q1 and the second switch Q2. For example, as described above, the control signal generator 32 turns on the first switch Q1 and turns off the second switch Q2 in response to the rising edge of the clock signal CLK from the oscillator circuit 33; and is responsive to a pulse width modulated signal S_PWMThe falling edge of (b) turns off the first switch Q1 and turns on the second switch Q2. In one embodiment, when compensating for voltage V_COMPLower than the second reference voltage V_REF2At this time, the pulse skipping signal generator 35 generates the pulse skipping signal SKIP having a high level, so that the buck converter 10 enters the pulse skipping mode. When the current through the inductor L decreases to zero, the second switch Q2 is turned off. Since the pulse skipping signal SKIP has a high level, the control of the switches by the clock signal CLK is blocked, and thus both the first switch Q1 and the second switch Q2 remain off until the pulse skipping signal SKIP goes low.

A regulated current generating circuit 34 is coupled to the oscillator circuit 33 anda compensation voltage generation circuit 36, and is configured to generate a compensation voltage V based on the compensation voltage_COMPGenerating a first current I₁. In one embodiment, oscillator circuit 33 is configured to be based on first current I₁To adjust the clock signal CLK.

Fig. 6 shows a schematic circuit diagram of the adjustment current generation circuit 34 and the oscillator circuit 33 according to the first embodiment of the present disclosure. In one embodiment, the adjustment current generation circuit 34 includes a voltage-to-current conversion circuit 41, a first current source 42, and a first current mirror circuit 43.

The voltage-to-current conversion circuit 41 is configured to compensate the voltage V_COMPIs converted into a second current I₂. In one embodiment, the compensation voltage V_COMPCan be adjusted to the second current I₂The amount of the solvent is proportional, for example,

V_COMP＝I₂*R (3)

where R is the resistance value of resistor R4. The first current source 42 is configured to provide a first reference current I_ref1. The first current mirror circuit 43 is coupled to the voltage-to-current conversion circuit 41, the first current source 42, and the oscillator circuit 33, and is configured to be based on the first reference current I_ref1And a second current I₂Generating a first current I₁. When V is_COMP＞I_ref1R, first current I₁With compensation voltage V_COMPDecrease of (c); and when V_COMP≤I_ref1R, first current I₁Is zero. In one embodiment, the first current mirror circuit 43 is an m: n current mirror. In one embodiment, the first current mirror circuit 43 is a 1:1 current mirror when V is greater than V_COMP＞I_ref1R, first current I₁Can be expressed as:

I₁＝I₂-I_ref1＝V_COMP/R-I_ref1 (4)

in one embodiment, the oscillator circuit 33 includes a second current source 44, a second current mirror circuit 45, a third current source 46, a third current mirror circuit 47, and a clock signal generation circuit 49.

The second current source 44 is configured to provideFor supplying a second reference current I_ref2. The second current mirror circuit 45 is coupled to the first current mirror circuit 43 and the second current source 44, and is configured to be based on the second reference current I_ref2And a first current I₁Generating a third current I₃. When I is₁≥I_ref2While, the third current I₃Is zero. When I is₁＜I_ref2While, the third current I₃Has a non-zero value. In one embodiment, the second current mirror circuit 45 is an m: n current mirror. In one embodiment, the second current mirror circuit 45 is a 1:1 current mirror when I₁＜I_ref2While, the third current I₃Can be expressed as:

I₃＝I_ref2-I₁ (5)

the third current source 46 is configured to provide a third reference current I_ref3. The third current mirror circuit 47 is coupled to the second current mirror circuit 45 and the third current source 46, and is configured to be based on the third reference current I_ref3And a third current I₃Generating a clock generation current I_C. In one embodiment, the third current mirror circuit 47 is an m: n current mirror. In one embodiment, the third current mirror circuit 47 is a 1:1 current mirror, clocked by the current I_CCan be expressed as:

I_C＝I_ref3-I₃ (6)

in conjunction with equations (3) - (5), equation (6) can be rewritten as follows:

when V is_COMP≥(I_ref1+I_ref2) R is, I₃Clock generating current I ═ 0_CWith the maximum value:

I_C＝I_ref3 (7)

when I is_ref1*R＜V_COMP＜(I_ref1+I_ref2) At R, the clock generates a current I_CCan follow the compensation voltage V_COMPDecrease of (c) and decrease:

I_C＝I_ref3-I_ref2-I_ref1+V_COMP/R (8)

when V is_COMP≤I_ref1At the time of R, the total of the R,I₁clock generating current I ═ 0_CWith the minimum:

I_C＝I_ref3-I_ref2 (9)

clock generation current I_CMay be based on the third current I₃And is adjusted to adjust the clock signal CLK. Specifically, the clock signal generation circuit 49 is coupled to the third current mirror circuit 47, and is configured to generate the current I based on the clock_CA clock signal CLK is generated. In one embodiment, the clock signal generation circuit 49 may include a capacitor C3, a comparator 48, and a third switch Q3. The capacitor C3 is coupled to the third current mirror circuit 47 and generates the current I from the clock_CAnd charging is carried out. The comparator 48 is coupled to the third current mirror circuit 47 and the capacitor C3, and is configured to generate the current I based on the clock_CGenerating the clock signal CLK when the voltage across the capacitor C3 is higher than the third reference voltage V_REF3When, the clock signal CLK has a high level; and when the voltage across the capacitor C3 is lower than the third reference voltage V_REF3When, the clock signal CLK has a low level. The third switch Q3 is connected in parallel with the capacitor C3 and is configured to be turned on in response to the clock signal CLK having a high level to discharge the capacitor C3, whereby the periodic clock signal CLK may be generated. The frequency of the clock signal CLK generating a current I with the clock_CIs reduced.

When compensating voltage V_COMPAt a higher time, the first current I₁Greater than or equal to the second reference current I_ref2The clock signal generation circuit 49 may generate the clock signal CLK having a preset frequency. When compensating voltage V_COMPAt a smaller time, the first current I₁Is less than the second reference current I_ref2The clock signal generation circuit 49 may generate the clock signal CLK with a reduced frequency. As the frequency of the clock signal CLK decreases, the control circuit 16 may decrease the number of times the first switch Q1 is turned on before the buck converter 10 enters the pulse-skipping mode, thereby effectively decreasing the output voltage V_OUTThe ripple of (3).

FIG. 7 shows a schematic circuit of a control circuit 16' according to a second embodiment of the present disclosureFigure (a). The control circuit 16' of fig. 7 is similar to the control circuit 16 of fig. 5, except that: the mode control circuit 31' further includes a peak detection circuit 62. The peak detection circuit 62 is coupled to the current detector 14 and is configured to generate a peak voltage signal, e.g., a sampled voltage V, based on the current detection signal_SThe peak voltage signal of (a). In fig. 7, the adjustment current generation circuit 34 is coupled to the oscillator circuit 33 and the peak detection circuit 62, and is configured to generate the first current I based on the peak voltage signal₁. In one embodiment, the regulation current generation circuit 34 and the oscillator circuit 33 of fig. 7 may be implemented as the regulation current generation circuit 34 and the oscillator circuit 33 of fig. 5, wherein the voltage-to-current conversion circuit 41 in the regulation current generation circuit 34 is configured to convert the peak voltage signal into the second current I₂For generating a first current I₁。

When the peak voltage signal is large, the first current I₁Greater than or equal to the second reference current I_ref2The oscillator circuit 33 may generate a clock signal CLK having a preset frequency. When compensating voltage V_COMPAt a smaller time, the first current I₁Is less than the second reference current I_ref2The oscillator circuit 33 may generate a clock signal CLK of reduced frequency. As the frequency of the clock signal CLK decreases, the control circuit 16' may decrease the number of times the first switch Q1 is turned on before the buck converter 10 enters the pulse-skipping mode, thereby effectively decreasing the output voltage V_OUTThe ripple of (3).

Fig. 8 shows a schematic circuit diagram of a control circuit 16 "according to a third embodiment of the present disclosure. The control circuit 16 "of fig. 8 is similar to the control circuit 16 of fig. 5, except that: mode control circuit 31 of fig. 5 includes a regulated current generation circuit 34 coupled between oscillator circuit 33 and compensation voltage generation circuit 36, while mode control circuit 31 ″ of fig. 8 includes a voltage selector 72 coupled between oscillator circuit 33' and compensation voltage generation circuit 36. The voltage selector 72 is configured to be based on the compensation voltage V_COMPGenerating an oscillator voltage V_OSC. Specifically, the voltage selector 72 is configured to: when compensating voltage V_COMPGreater than or equal to a first threshold voltage V_MAXIs equal to the first threshold voltage V_MAXVoltage V of the oscillator_OSC(ii) a When compensating voltage V_COMPLess than a first threshold voltage V_MAXAnd is greater than a second threshold voltage V_MINGenerating a voltage equal to the compensation voltage V_COMPVoltage V of the oscillator_OSC(ii) a And when compensating the voltage V_COMPIs less than or equal to the second threshold voltage V_MINIs equal to the second threshold voltage V_MINVoltage V of the oscillator_OSCWherein the first threshold voltage V_MAXGreater than a second threshold voltage V_MIN。

The oscillator circuit 33' is configured to be based on the oscillator voltage V generated by the voltage selector 72_OSCTo generate the clock signal CLK.

Fig. 9 shows a schematic circuit diagram of an oscillator circuit 33' according to a third embodiment of the present disclosure.

The oscillator circuit 33' includes a voltage-to-current conversion circuit 41, a current mirror circuit 47, and a clock signal generation circuit 49. The voltage-to-current conversion circuit 41, the current mirror circuit 47, and the clock signal generation circuit 49 of fig. 9 are similar to the voltage-to-current conversion circuit 41, the third current mirror circuit 47, and the clock signal generation circuit 49 of fig. 5, except that: in fig. 9, the voltage-to-current conversion circuit 41 is configured to convert the oscillator voltage V_OSCConversion to an oscillator current I₄And the oscillator current I is adjusted₄Is supplied to the current mirror circuit 47. In one embodiment, the voltage-to-current conversion circuit 41 is coupled to the voltage selector 72 and is configured to generate and compensate the voltage V_OSCProportional second current I₄E.g. V_OSC＝I₄R, where R is the resistance value of resistor R4. The current mirror circuit 47 is coupled to the voltage-to-current conversion circuit 41 and is configured to be based on the oscillator current I₄Generating a clock generation current I_C. In one embodiment, the third current mirror circuit 47 is an m: n current mirror. In one embodiment, the third current mirror circuit 47 is a 1:1 current mirror, where I_C＝I₄. Specifically, when V_COMP≥V_MAXTime of day, clock generation current I_CHaving a maximum value of I_C＝V_MAXR; when V is_MIN＜V_COMP＜V_MAXWhen, I_C＝V_COMP/R, clock generation current I_CWith compensation voltage V_COMPDecrease of (c); when V is_COMP≤V_MINTime of day, clock generation current I_CHas a minimum value of I_C＝V_MIN/R。

The clock signal generation circuit 49 is coupled to the current mirror circuit 47 and configured to generate the current I based on the clock_CA clock signal CLK is generated. When compensating voltage V_COMPAt larger times, the clock generates a current I_CHaving the maximum value, the clock signal generation circuit 49 can generate the clock signal CLK having a preset frequency. When compensating voltage V_COMPWhen small, the clock generates a current I_CTo reduce, the clock signal generation circuit 49 may generate the clock signal CLK with a reduced frequency. As the frequency of the clock signal CLK decreases, the control circuit 16 ″ may cause the first switch Q1 to turn on less often before the buck converter 10 enters the pulse-skipping mode, thereby effectively decreasing the output voltage V_OUTThe ripple of (3).

Fig. 5 to 9 show examples of control circuits according to three embodiments of the present disclosure, but it is understood that the control circuits are not limited thereto, but may have other control circuits as long as they can be based on the follow-up output voltage V_OUTThe clock signal CLK is adjusted by the varying signal.

Fig. 10 shows a schematic waveform timing diagram of a buck converter according to an embodiment of the present disclosure. In the buck converter of the embodiment of the present disclosure, the voltage may be based on the output voltage V_OUTThe clock signal CLK is adjusted by the varying signal. With output voltage V_OUTSuch as, but not limited to, a compensation voltage V_COMPOr sampling voltage V_SThe peak voltage signal of (a). For example, in the control circuit 16' shown in FIG. 7, when the voltage V is output_OUTExceeds a predetermined output voltage V_REF0Based on the sampled voltage V_SWill go low so that the frequency of the clock signal CLK will be lowDecreasing, the number of times the first switch Q1 is turned on before the buck converter 10 enters the pulse-skipping mode is decreased, thereby effectively decreasing the output voltage V_OUTThe ripple of (3). Only one switching operation is shown in fig. 10 without additional switching operations. It will be appreciated that when the buck converter is operated at a high frequency, there may also be a reduced number of additional switching operations before entering the pulse skipping mode, so that the ripple of the output voltage is relatively reduced.

The technical scheme of the embodiment of the disclosure is based on the voltage V along with the output voltage_OUTThe varying and varying signal automatically adjusts the frequency of the clock signal CLK, reducing the number of times a switch in the buck converter is turned on before the buck converter enters a pulse skipping mode, thereby effectively reducing ripple of the output voltage. Compared with a conventional buck converter, the technical scheme of the embodiment of the disclosure has a simple structure, can reduce switching loss, and realizes reduction of ripple of output voltage under the condition of hardly increasing the occupied area of a PCB.

The embodiments may be further described using the following clauses:

1. a buck converter (10), comprising:

a step-down circuit (12) comprising a series connection of an input voltage (V)_IN) And a first switch (Q1) and a second switch (Q2) between a first reference voltage, and is configured to couple the input voltage (V) by alternately turning on the first switch (Q1) and the second switch (Q2)_IN) Step-down to an output voltage (V)_OUT)；

A current detector (14) coupled to the voltage-dropping circuit (12) and configured to detect a current flowing through the voltage-dropping circuit (12) and generate a current detection signal representative of the current; and

a control circuit (16) coupled to the voltage-reduction circuit (12) and the current detector (14) and configured to:

controlling the first switch (Q1) and the second switch (Q2) based on the current detection signal; and

in response to the output voltage (V)_OUT) Is controlled such that the first switch (Q1) is at the dropThe number of times the voltage converter (10) is switched on before entering a pulse skipping mode is reduced, wherein during said pulse skipping mode said first switch (Q1) remains switched off.

2. The buck converter (10) of clause 1, wherein the control circuit (16) includes:

a mode control circuit (31) coupled to the voltage reduction circuit (12) and the current detector (14) and configured to detect the output voltage (V) based on the current detection signal and the output voltage (V)_OUT) Generates a clock signal (CLK) and a pulse width modulation signal (S)_PWM) And a pulse SKIP Signal (SKIP); and

a control signal generator (32) coupled to the voltage reduction circuit (12) and the mode control circuit (31) and configured to modulate the signal (S) based on the clock signal (CLK), the pulse width modulation signal (S)_PWM) And the pulse skipping Signal (SKIP) to generate a first switch control signal (SW1) and a second switch control signal (SW2), wherein the first switch control signal (SW1) is used to control the first switch (Q1) to turn on and off, and the second switch control signal (SW2) is used to control the second switch (Q2) to turn on and off;

wherein the control signal generator (32) is further configured to: -causing the buck converter (10) to enter the pulse-skipping mode in response to the pulse-skipping Signal (SKIP) being high.

3. The buck converter (10) of clause 2, wherein the mode control circuit (31) includes:

a compensation voltage generation circuit (36) coupled to the voltage reduction circuit (12) and configured to generate a compensation voltage based on the output voltage (Vv)_OUT) Proportional feedback voltage (V)_FB) And a first reference voltage (V)_REF1) The difference between them to generate a compensation voltage (V)_COMP)；

A pulse width modulation signal generator (37) coupled to the current detector (14), the compensation voltage generation circuit (36) and the control signal generator (32) and configured to generate the compensation voltage (V) based on the current detection signal and the compensation voltage (V)_COMP) Generating the pulse width modulated signal (S)_PWM)；

A pulse skipping signal generator (35) coupled to the compensation voltage generation circuit (36) and the control signal generator (32) and configured to generate a compensation voltage (Vv) based on the compensation voltage (Vv)_COMP) And a second reference voltage (V)_REF2) Generating the pulse skipping Signal (SKIP); and

an oscillator circuit coupled to the control signal generator (32) and configured to generate the clock signal (CLK).

4. The buck converter (10) of clause 2, wherein the mode control circuit (31) is further configured to be responsive to the output voltage (V)_OUT) Causes a change in the frequency of the clock signal (CLK).

5. The buck converter (10) of clause 3, wherein the compensation voltage generation circuit (36) is configured to:

in response to the feedback voltage (V)_FB) Is lower than the first reference voltage (V)_REF1) Charging a capacitor (C2) to increase the compensation voltage (V)_COMP) (ii) a And

in response to the feedback voltage (V)_FB) Higher than the first reference voltage (V)_REF1) Discharging the capacitor (C2) to reduce the compensation voltage (V)_COMP)。

6. The buck converter (10) of clause 3, wherein the mode control circuit (31) further includes:

a regulation current generation circuit (34) coupled to the oscillator circuit and the compensation voltage generation circuit (36) and configured to generate a compensation voltage (Vd) based on the compensation voltage (Vd)_COMP) Generating a first current (I)₁)；

And wherein the oscillator circuit is configured to be based on the first current (I)₁) To adjust the clock signal (CLK).

7. The buck converter (10) of clause 6, wherein the regulation current generation circuit (34) includes:

a voltage-to-current conversion circuit (41) configured to convert the compensation voltage (V)_COMP) Is converted into a second current (I)₂)；

A first current source (42) configured to provide a first reference current (I)_ref1) (ii) a And

a first current mirror circuit (43) coupled to the voltage-to-current conversion circuit (41), the first current source (42) and the oscillator circuit (33) and configured to be based on the first reference current (I |)_ref1) And the second current (I)₂) Generating the first current (I)₁)。

8. The buck converter (10) of clause 6, wherein the oscillator circuit is configured to:

when the first current (I)₁) Greater than or equal to the second reference current (I)_ref2) Generating said clock signal (CLK) having a preset frequency; and

when the first current (I)₁) Is less than the second reference current (I)_ref2) Generating said clock signal (CLK) with a reduced frequency.

9. The buck converter (10) of clause 6, wherein the oscillator circuit comprises:

a second current source (44) configured to provide a second reference current (I)_ref2)；

A second current mirror circuit (45) coupled to the regulation current generation circuit (34) and the second current source (44) and configured to be based on the second reference current (I)_ref2) And the first current (I)₁) Generating a third current (I)₃)，

Wherein when the first current (I) is applied₁) Is less than the second reference current (I)_ref2) While the third current (I)₃) Having a non-zero value, the clock signal (CLK) being based on the third current (I)₃) And is adjusted.

10. The buck converter (10) of clause 9, wherein the oscillator circuit further comprises:

a third current source (46) configured to provide a third reference current (I)_ref3)；

A third current mirror circuit (47) coupled to the second current mirror circuit (45) and the third currentA source (46) and is configured to be based on the third reference current (I)_ref3) And the third current (I)₃) Generating a clock generation current (I)_C) (ii) a And

a clock signal generation circuit (49) coupled to the third current mirror circuit (47) and configured to generate a current (I) based on the clock_C) Generating the clock signal (CLK).

11. The buck converter (10) of clause 10, wherein the clock signal generation circuit (49) includes:

a capacitor (C3) coupled to the third current mirror circuit (47) and generating a current (I) from the clock_C) Charging is carried out;

a comparator (48) coupled to the third current mirror circuit (47) and the capacitor (C3) and configured to generate a current (I) based on the clock_C) Generating the clock signal (CLK) when the voltage across the capacitor (C3) is higher than a third reference voltage (V)_REF3) -the clock signal (CLK) has a high level; and

a third switch (Q3) connected in parallel with the capacitor (C3) and configured to turn on in response to the clock signal (CLK) having a high level to discharge the capacitor (C3).

12. The buck converter (10) of clause 3, wherein the mode control circuit further comprises:

a peak detection circuit (62) coupled to the current detector (14) and configured to generate a peak voltage signal based on the current detection signal; and

a regulated current generation circuit (34) coupled to the oscillator circuit and the peak detection circuit (62) and configured to generate a first current (I) based on the peak voltage signal₁)；

13. The buck converter (10) of clause 3, wherein the mode control circuit further comprises:

a voltage selector (72) coupled to the oscillator circuit and the compensation voltage generation circuit (36) and configured to be based on the compensation voltage (Vv)_COMP) Generating an oscillator voltage (V)_OSC)；

And wherein the oscillator circuit is configured to be based on the oscillator voltage (V)_OSC) Generating the clock signal (CLK).

14. The buck converter (10) of clause 13, wherein the voltage selector (72) is further configured to:

when the compensation voltage (V)_COMP) Greater than or equal to a first threshold voltage (V)_MAX) Is equal to the first threshold voltage (V)_MAX) Of said oscillator voltage (V)_OSC)；

When the compensation voltage (V)_COMP) Less than the first threshold voltage (V)_MAX) And is greater than the second threshold voltage (V)_MIN) Generating a voltage equal to said compensation voltage (V)_COMP) Of said oscillator voltage (V)_OSC) (ii) a And is

When the compensation voltage (V)_COMP) Less than or equal to the second threshold voltage (V)_MIN) Is equal to the second threshold voltage (V)_MIN) Of said oscillator voltage (V)_OSC)；

Wherein the first threshold voltage (V)_MAX) Greater than the second threshold voltage (V)_MIN)。

15. The buck converter (10) of clause 13, wherein the oscillator circuit comprises:

a voltage-to-current conversion circuit (41) coupled to the voltage selector (72) and configured to convert the oscillator voltage (V)_OSC) Conversion to oscillator current (I)₄)；

A current mirror circuit coupled to the voltage-to-current conversion circuit (41) and configured to be based on the oscillator current (I)₄) Generating a clock generation current (I)_C) (ii) a And

a clock signal generation circuit (49) coupled to the current mirror circuit and configured to generate a current based on the clock(I_C) Generating the clock signal (CLK).

16. The buck converter (10) of clause 1, wherein the buck circuit (12) further includes:

an inductor (L) coupled between an intermediate point between the first switch (Q1) and the second switch (Q2) and the output voltage (V)_OUT) To (c) to (d); and

a capacitor (C1) coupled at the output voltage (V)_OUT) And the first reference voltage.

17. An electronic device (1) comprising:

a power supply device (2); and

the buck converter (10) of any one of clauses 1-16, powered by the power supply (2).

Further, the present disclosure provides various example embodiments, as described and as shown in the accompanying drawings. However, the present disclosure is not limited to the embodiments described and illustrated herein, but may extend to other embodiments, as known or as would be known to those skilled in the art. Reference in the specification to "one embodiment," "the embodiment," "these embodiments," or "some embodiments" means that a particular feature, structure, or characteristic described is included in at least one embodiment, and the appearances of the phrases in various places in the specification are not necessarily all referring to the same embodiment.

Finally, although various embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended drawings is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claimed subject matter.

Claims

1. A buck converter (10), comprising:

a step-down circuit (12) comprising a series connection of an input voltage (V)_IN) And a first switch (Q1) and a second switch (Q2) between a first reference voltage, and configured to switch on the first switch (Q1) and the second switch (Q2) alternatelyApplying the input voltage (V)_IN) Step-down to an output voltage (V)_OUT)；

in response to the output voltage (V)_OUT) To reduce the number of times the first switch (Q1) is turned on before the buck converter (10) enters a pulse-skip mode, wherein during the pulse-skip mode the first switch (Q1) remains off.

2. The buck converter (10) of claim 1, wherein the control circuit (16) includes:

3. The buck converter (10) of claim 2, wherein the mode control circuit (31) includes:

4. The buck converter (10) of claim 2, wherein the mode control circuit (31) is further configured to be responsive to the output voltage (V ™)_OUT) Causes a change in the frequency of the clock signal (CLK).

5. The buck converter (10) of claim 3, wherein the compensation voltage generation circuit (36) is configured to:

6. The buck converter (10) of claim 3, wherein the mode control circuit (31) further comprises:

7. The buck converter (10) of claim 6, wherein the regulation current generation circuit (34) includes:

8. The buck converter (10) of claim 6, wherein the oscillator circuit is configured to:

9. The buck converter (10) of claim 6, wherein the oscillator circuit includes:

a second current source (44) configured to provide a second reference current (I)_ref2) (ii) a And

10. The buck converter (10) of claim 9, wherein the oscillator circuit further comprises:

A third current mirror circuit (47) coupled to the second current mirror circuit (45) and the third current source (46) and configured to be based on the third reference current (I)_ref3) And the third current (I)₃) Generating a clock generation current (I)_C) (ii) a And

11. The buck converter (10) of claim 10, wherein the clock signal generation circuit (49) includes:

a comparator (48) coupled to the third current mirror circuit (47) and the capacitor (C3) and configured to generate a current (I) based on the clock_C) Generation placeThe clock signal (CLK), wherein when the voltage across the capacitor (C3) is higher than a third reference voltage (V)_REF3) -the clock signal (CLK) has a high level; and

12. The buck converter (10) of claim 3, wherein the mode control circuit further comprises:

13. The buck converter (10) of claim 3, wherein the mode control circuit further comprises:

14. The buck converter (10) of claim 13, wherein the voltage selector (72) is further configured to:

when the compensation voltage (V)_COMP) Greater than or equal to a first threshold voltage (V)_MAX) Is equal to the first threshold voltage (V)_MAX) Said vibratorOscillator voltage (V)_OSC)；

15. The buck converter (10) of claim 13, wherein the oscillator circuit includes:

a clock signal generation circuit (49) coupled to the current mirror circuit and configured to generate a current (I) based on the clock_C) Generating the clock signal (CLK).

16. The buck converter (10) of claim 1, wherein the buck circuit (12) further comprises:

17. An electronic device (1) comprising:

a power supply device (2); and

the buck converter (10) according to any one of claims 1 to 16, powered by the power supply means (2).