CN113725199A - Low inductance crimping type semiconductor module - Google Patents
Low inductance crimping type semiconductor module Download PDFInfo
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- CN113725199A CN113725199A CN202110850662.8A CN202110850662A CN113725199A CN 113725199 A CN113725199 A CN 113725199A CN 202110850662 A CN202110850662 A CN 202110850662A CN 113725199 A CN113725199 A CN 113725199A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000002788 crimping Methods 0.000 title claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 59
- 230000017525 heat dissipation Effects 0.000 claims description 16
- 239000012212 insulator Substances 0.000 claims description 4
- 230000000712 assembly Effects 0.000 claims description 3
- 238000000429 assembly Methods 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000006835 compression Effects 0.000 description 5
- 238000007906 compression Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000000110 cooling liquid Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003570 air Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses a low inductance crimping type semiconductor module, comprising: the module comprises a module upper bridge arm P pole, a module lower bridge arm N pole, a first chip drain conductor, a second chip drain conductor, a first chip source conductor (8), a second chip source conductor, a pressure-bearing limiting structure, a module output end and at least one group of power chip unit groups, wherein each power chip unit group comprises a first power chip unit and a second power chip unit; the module upper bridge arm P pole, the first chip drain electrode conductor, the first power chip unit, the first chip source electrode conductor and the module output end are connected in sequence; the N pole of the lower bridge arm of the module, the source electrode conductor of the second chip, the unit of the second power chip, the drain electrode conductor of the second chip and the output end of the module are sequentially connected. The advantages are that: the chip is connected through the structural design inside the module, the longitudinal and short-distance flow of current is realized, and then the semiconductor module with low inductance, low thermal resistance and high current and a bridge function is realized.
Description
Technical Field
The invention relates to a low-inductance crimping type semiconductor module, and belongs to the technical field of power semiconductor module packaging.
Background
While power device technology continues to advance, more stringent requirements are placed on the heat dissipation performance and inductance of device packaging technology. At present, the packaging of a high-power semiconductor module has two main forms, one is a bottom plate insulation module type packaging which comprises a chip, a bottom plate, a copper-coated ceramic substrate, a bonding wire, a sealing material, an insulation shell, a power terminal and the like, and the inside of the module is filled with insulation materials such as silica gel or epoxy resin to isolate the chip from the external environment (water, air and dust), so that the service life of the device is shortened.
The other type is compression joint type packaging, the thermal resistance of the chip is reduced through a compression joint mode, the electrical performance and the current capacity are improved, and the chip sub-units are modularized, so that the purposes of parallel connection use of a plurality of chips and improvement of the power density and the current grade of the module are achieved.
In the prior art, because of the circuit and design concept of the bottom plate insulation modular package, current generally flows transversely through binding wires to generate larger inductance, and meanwhile, single-side heat dissipation is generally adopted, so that lower thermal resistance is difficult to realize, and the through-current capacity of the module is further improved. Although the press-fit type package can realize longitudinal flow of current and is easy to realize double-sided heat dissipation, a plurality of chips are generally used in parallel, namely, the whole module is equivalent to a high-power single tube, and convenient circuit connection is difficult to realize.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a low-inductance crimping type semiconductor module, which is characterized in that chips are connected through the structural design inside the module, so that the longitudinal and short-distance flow of current is realized, and further, the semiconductor module which is low in inductance, low in thermal resistance and high in current and has a bridge function is realized.
In order to solve the above-mentioned technical problem, the present invention provides a low inductance crimp-type semiconductor module, comprising: the module comprises a module upper bridge arm P pole, a module lower bridge arm N pole, a first chip drain conductor, a second chip drain conductor (11), a first chip source conductor, a second chip source conductor, a pressure-bearing limiting structure, a module output end and at least one group of power chip unit groups, wherein each power chip unit group comprises a first power chip unit and a second power chip unit;
the upper bridge arm P pole and the lower bridge arm N pole of the module are arranged on the same plane and are isolated by an insulator, and the upper bridge arm P pole and the lower bridge arm N pole of the module are tightly pressed and conducted with chips in the power chip unit group through pressure with the output end of the module;
the pressure-bearing limiting structure is arranged between the P pole of the upper bridge arm of the module and the output end of the module as well as between the N pole of the lower bridge arm of the module and the output end of the module;
the module upper bridge arm P pole, the first chip drain electrode conductor, the first power chip unit, the first chip source electrode conductor and the module output end are connected in sequence;
the N pole of the lower bridge arm of the module, the source electrode conductor of the second chip, the unit of the second power chip, the drain electrode conductor of the second chip and the output end of the module are sequentially connected.
Furthermore, the first chip drain conductor and the first power chip unit are connected through the first chip and drain conductor connecting layer;
and the second chip drain conductor is connected with the second power chip unit through the second chip and drain conductor connecting layer.
Furthermore, the first power chip unit is connected with the first chip source electrode conductor through the first chip and source electrode conductor connecting layer;
and the second power chip unit is connected with the second chip source electrode conductor through the second chip and source electrode conductor connecting layer.
Furthermore, the first power chip unit and the second power chip unit are units containing a plurality of power chips.
Furthermore, the chips in the unit containing a plurality of power chips are connected in parallel, and the control electrode of each chip is connected and PIN PINs are led out from two sides or one side of the module for connecting an external controller.
And the two spring assemblies are respectively connected with the source electrode conductor of the first chip and the output end of the module in a guiding manner, and connected with the N pole of the lower bridge arm of the module, the connecting layer of the second chip and the source electrode conductor in a guiding manner.
Furthermore, a gap is arranged between the pressure-bearing limiting structure and the output end of the module under the natural state of the spring assembly.
Furthermore, one or more of the upper bridge arm P pole of the module, the lower bridge arm N pole of the module and the output end of the module are provided with heat dissipation channels.
The invention achieves the following beneficial effects:
the chip unit in the module is connected through coupling type crimping, current can pass through a longitudinal short current path, low inductance design is achieved, according to the fact that delta U = Ldi/dt in the switching process of a semiconductor device, voltage overshoot of the module is reduced through reduction of L through the structure, the service life of the module is prolonged, and the advantage is obvious particularly in wide-bandgap semiconductors with high di/dt.
Meanwhile, as the current path of the compression joint device is vertical to the direction of the chips, the current balance degree between the chips is high, and the service life of the module can be well prolonged
In addition, the semiconductor module provided by the invention can conveniently realize double-sided heat dissipation effect, reduce the thermal resistance of the module, improve the heat dissipation performance of the module and further improve the electrical performance and power density of the module.
Finally, compared with the traditional double-sided heat dissipation module, the scheme cancels a ceramic lining plate structure, thereby reducing the voltage breakdown problem caused by the cracking of the lining plate caused by vibration and improving the design redundancy of the system.
Drawings
FIG. 1 is a schematic diagram of the structure of one embodiment of the present invention (with the dashed lines representing the current paths);
FIG. 2 is an equivalent schematic diagram of a half-bridge circuit in the embodiment of FIG. 1;
FIG. 3 is a schematic structural diagram of another embodiment of the present invention;
FIG. 4 is a schematic diagram of a multi-chip configuration of a first power chip unit and a second power chip unit;
FIG. 5 is a top view of a multi-cell cascaded three-phase full bridge module of the present invention;
FIG. 6 is a schematic bottom electrode connection of the three-phase full bridge module of FIG. 5;
FIG. 7 is an equivalent circuit diagram of the three-phase full bridge module of FIG. 5;
FIG. 8 is a schematic view of a first configuration of a heat dissipation channel;
FIG. 9 is a second structural view of a heat dissipation channel;
fig. 10 is a third structural diagram of the heat dissipation channel.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
Specifically, as shown in fig. 1 and 2, a low inductance press-fit type semiconductor module structure of the present invention includes: the module comprises a module upper bridge arm P pole 1, a module lower bridge arm N pole 2, a first chip drain conductor 4, a second chip drain conductor 11, a first chip and drain conductor connecting layer 5, a second chip and drain conductor connecting layer 15, a first power chip unit 6, a second power chip unit 12, a first chip and source conductor connecting layer 7, a second chip and source conductor connecting layer 14, a first chip source conductor 8, a second chip source conductor 13, a pressure-bearing limit structure 10 and a module output end O pole 3. The upper bridge arm P pole 1 and the lower bridge arm N pole 2 of the module are arranged on the same plane and are isolated by an insulator, and the upper bridge arm P pole and the lower bridge arm N pole are tightly pressed and conducted with a chip in the power chip unit group through pressure with the output end 3 of the module; the lower end of the pressure-bearing limiting structure 10 is respectively and fixedly connected with the upper bridge arm P pole 1 of the module and the lower bridge arm N pole 2 of the module; the module upper bridge arm P pole 1, the first chip drain electrode conductor 4, the first power chip unit 6, the first chip source electrode conductor 8 and the module output end 3 are sequentially connected from bottom to top; the module lower bridge arm N pole 2, the second chip source electrode conductor 13, the second power chip unit 12, the second chip drain electrode conductor 11 and the module output end 3 are sequentially connected from bottom to top.
The P pole 1 of the upper bridge arm of the module and the N pole 2 of the lower bridge arm of the module are isolated by an insulator; the number of the power chip units can be several; the pressure-bearing limiting structure 10 is respectively connected and fixed with the P pole 1 of the upper bridge arm and the N pole 2 of the lower bridge arm of the module, the P pole 1 of the upper bridge arm and the N pole 2 of the lower bridge arm of the module are positioned on the same plane and tightly press the chip with the O pole 3 of the output end of the module through pressure, so that a current and heat dissipation path is realized, and the larger the pressure is, the smaller the contact resistance and the contact thermal resistance in a current loop are; meanwhile, as the pressure is increased, partial pressure exceeding the designed chip threshold pressure is borne through the pressure-bearing limiting structure, so that the purpose of protecting the chip is achieved.
As shown in fig. 4, 6 power chips are arranged in the first power chip unit 6 and the second power chip unit 12, control electrodes of the power chips are connected, PIN PINs are led out from the side edges of the modules, and are used for controlling the turn-on of G/S electrodes (gates/sources) of the chips and connected to an external controller;
a heat dissipation channel is designed for the P pole 1 of the upper bridge arm of the module, the N pole 2 of the lower bridge arm of the module and the output end 3 of the module;
fig. 8 belongs to a liquid-cooled radiator, a flow channel is arranged in an upper module bridge arm P pole 1, a lower module bridge arm N pole 2 and a module output end 3, cooling liquid is input through an inlet of the flow channel, and an outlet of the flow channel is output, so that heat of a module can be taken away in the flow channel;
FIG. 9 belongs to micro-channel heat dissipation, wherein micro-scale micro-channels are arranged in an upper bridge arm P pole 1, a lower bridge arm N pole 2 and a module output end 3 of a module, and heat is taken away through cooling liquid;
fig. 10 belongs to PinFin heat dissipation, and turbulence columns are additionally arranged at the bottoms of a module upper bridge arm P pole 1 and a module lower bridge arm N pole 2 and at the upper part of a module output end 3, so that cooling liquid laminar flow is disturbed into turbulence, and heat is fully absorbed and taken away.
The module structure reduces the loop stray inductance by the following 3 ways: as shown in fig. 1, the designed current loop path is a straight-up, straight-down, horizontal, flat and vertical current path, and the path is shorter and has no bend, so that the stray inductance is reduced; 2. the stray inductance is reduced by adopting the magnetic field cancellation effect of the reverse loop when viewed from the current direction; 3. according to the scheme, a busbar is omitted, the electrode leading-in and leading-out are realized by the module upper bridge arm P pole 1, the module lower bridge arm N pole 2 and the module output end 3 which are provided with the heat dissipation channels, and stray inductance caused by the busbar can be avoided.
The crimping mode proposed by the technical scheme is rigid crimping, as shown in fig. 3, as another embodiment, elastic crimping is adopted, and the difference from the previous embodiment is that the spring assembly 9 is further included, wherein one spring assembly 9 is in conductive connection with a first chip source electrode conductor 8 and a module output end 3, the other spring assembly 9 is in conductive connection with a module lower bridge arm N pole 2 and a second chip source electrode conductor 13, a gap is reserved between a pressure-bearing limiting structure (10) and the module output end 3 in a natural state of the spring assembly 9, the spring assembly realizes pressure through compression, and the gap is used for providing a spring compression stroke; the elastic component replaces a rigid source electrode/drain electrode conductor, so that uneven stress caused by thickness tolerance of parts is absorbed, and the reliability of the product is improved.
As shown in fig. 5 to 7, the semiconductor module disclosed in the present invention can be extended to an H-bridge or a three-phase full-bridge module by adding the first power chip unit 6 and the second power chip unit 12 according to the requirement.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A low inductance crimp-type semiconductor module, comprising: the circuit comprises a module upper bridge arm P pole (1), a module lower bridge arm N pole (2), a first chip drain conductor (4), a second chip drain conductor (11), a first chip source conductor (8), a second chip source conductor (13), a pressure-bearing limiting structure (10), a module output end (3) and at least one group of power chip unit group, wherein the power chip unit group comprises a first power chip unit (6) and a second power chip unit (12);
the upper bridge arm P pole (1) and the lower bridge arm N pole (2) of the module are arranged on the same plane and are isolated by an insulator, and the upper bridge arm P pole and the lower bridge arm N pole of the module are tightly pressed and conducted with the output end (3) of the module through pressure to the chips in the power chip unit group;
the bearing limiting structure (10) is arranged between the upper bridge arm P pole (1) and the module output end (3) of the module and between the lower bridge arm N pole (2) and the module output end (3) of the module;
the module upper bridge arm P pole (1), the first chip drain electrode conductor (4), the first power chip unit (6), the first chip source electrode conductor (8) and the module output end (3) are sequentially connected;
the N pole (2) of the lower bridge arm of the module, a second chip source electrode conductor (13), a second power chip unit (12), a second chip drain electrode conductor (11) and the module output end (3) are sequentially connected.
2. The low inductance crimp-type semiconductor module according to claim 1,
the first chip drain conductor (4) is connected with the first power chip unit (6) through the first chip and drain conductor connecting layer (5);
the second chip drain conductor (11) and the second power chip unit (12) are connected through a second chip and drain conductor connecting layer (15).
3. The low inductance crimp-type semiconductor module according to claim 1,
the first power chip unit (6) is connected with the first chip source electrode conductor (8) through the first chip and source electrode conductor connecting layer (7);
the second power chip unit (12) and the second chip source conductor (13) are connected through a second chip and source conductor connecting layer (14).
4. The low inductance crimp-type semiconductor module according to claim 1, wherein the first power chip unit (6) and the second power chip unit (12) are units containing a plurality of power chips.
5. The low inductance crimp-type semiconductor module according to claim 4, wherein the chips in the unit containing the plurality of power chips are connected in parallel, and a control electrode of each chip is connected and a PIN is led out from both sides or one side of the module for connecting an external controller.
6. The low inductance crimping type semiconductor module according to claim 1, further comprising spring assemblies (9), two of the spring assemblies (9) respectively conducting the first chip source conductor (8) and the module output terminal (3), and conducting the module lower arm N-pole (2) and the second chip and source conductor connection layer (14).
7. A low inductance crimp-type semiconductor module according to claim 6, wherein a gap is provided between the pressure-bearing limit structure (10) and the module output end (3) in a natural state of the spring assembly (9).
8. The low inductance crimp-type semiconductor module according to claim 1, wherein one or more of the module upper arm P pole (1), the module lower arm N pole (2) and the module output terminal (3) is provided with a heat dissipation channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110850662.8A CN113725199B (en) | 2021-07-27 | 2021-07-27 | Low-inductance crimping type semiconductor module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110850662.8A CN113725199B (en) | 2021-07-27 | 2021-07-27 | Low-inductance crimping type semiconductor module |
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| Publication Number | Publication Date |
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| CN113725199A true CN113725199A (en) | 2021-11-30 |
| CN113725199B CN113725199B (en) | 2023-11-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116759388A (en) * | 2023-08-18 | 2023-09-15 | 合肥阿基米德电子科技有限公司 | Welding-free module packaging structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060044772A1 (en) * | 2004-08-31 | 2006-03-02 | Kabushiki Kaisha Toshiba | Semiconductor module |
| JP2009071329A (en) * | 2008-12-15 | 2009-04-02 | Hitachi Ltd | Intergrated circuit for driving semiconductor device and power converter |
| CN103123919A (en) * | 2011-10-31 | 2013-05-29 | 英飞凌科技股份有限公司 | Low inductance power module |
| CN106537753A (en) * | 2014-09-05 | 2017-03-22 | 丰田自动车株式会社 | Power module |
| CN113013147A (en) * | 2021-04-16 | 2021-06-22 | 南瑞联研半导体有限责任公司 | Semiconductor module |
-
2021
- 2021-07-27 CN CN202110850662.8A patent/CN113725199B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060044772A1 (en) * | 2004-08-31 | 2006-03-02 | Kabushiki Kaisha Toshiba | Semiconductor module |
| JP2009071329A (en) * | 2008-12-15 | 2009-04-02 | Hitachi Ltd | Intergrated circuit for driving semiconductor device and power converter |
| CN103123919A (en) * | 2011-10-31 | 2013-05-29 | 英飞凌科技股份有限公司 | Low inductance power module |
| CN106537753A (en) * | 2014-09-05 | 2017-03-22 | 丰田自动车株式会社 | Power module |
| CN113013147A (en) * | 2021-04-16 | 2021-06-22 | 南瑞联研半导体有限责任公司 | Semiconductor module |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116759388A (en) * | 2023-08-18 | 2023-09-15 | 合肥阿基米德电子科技有限公司 | Welding-free module packaging structure |
| CN116759388B (en) * | 2023-08-18 | 2023-10-27 | 合肥阿基米德电子科技有限公司 | Welding-free module packaging structure |
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| Publication number | Publication date |
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| CN113725199B (en) | 2023-11-28 |
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