CN113725161A - Processing technique method of 3D wafer - Google Patents
Processing technique method of 3D wafer Download PDFInfo
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- CN113725161A CN113725161A CN202111027384.2A CN202111027384A CN113725161A CN 113725161 A CN113725161 A CN 113725161A CN 202111027384 A CN202111027384 A CN 202111027384A CN 113725161 A CN113725161 A CN 113725161A
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
The invention relates to the technical field of 3D wafer processing, in particular to a processing method of a 3D wafer, which comprises the following steps: pasting a protective film on the upper surface of the 3D wafer; grinding the lower surface of the 3D wafer for the first time; the upper surface of the 3D wafer is subjected to laser to remove the cutting channel metal circuit layer, and a cutting channel area is formed; carrying out invisible cutting on the inner part of the 3D wafer at the position of the cutting path area to form a modified layer; carrying out second grinding on the lower surface of the 3D wafer; and separating the 3D wafer to form a plurality of monomer crystal grains. According to the invention, the metal circuit layer on the wafer cutting channel is removed by laser before the internal invisible cutting process of the 3D wafer, so that the interference of the metal circuit layer on the crystal grains of the 3D wafer is removed in the cold and hot expanding process, the effective separation is achieved, the grinding, thinning and separating yield of the ultrathin 3D wafer is realized, and the reliability of the product is improved.
Description
Technical Field
The invention relates to the technical field of 3D wafer processing, in particular to a processing method of a 3D wafer.
Background
Because the thickness of the 3D wafer circuit layer is larger than that of the 2D wafer, the metal circuit layer on the 3D wafer cutting channel cannot be effectively separated in the cold and hot expanding process after laser invisible cutting and grinding thinning by using the traditional processing method, so that serious edge breakage, crystal cracking and connected crystal grains occur, and the yield loss is large.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a processing method of a 3D wafer.
In order to solve the technical problems, the invention adopts the following technical scheme:
a processing technique method of a 3D wafer comprises the following steps:
pasting a protective film on the upper surface of the 3D wafer;
grinding the lower surface of the 3D wafer for the first time;
the upper surface of the 3D wafer is subjected to laser to remove the cutting channel metal circuit layer, and a cutting channel area is formed;
carrying out invisible cutting on the inner part of the 3D wafer at the position of the cutting path area to form a modified layer;
carrying out second grinding on the lower surface of the 3D wafer;
and separating the 3D wafer to form a plurality of monomer crystal grains.
The further technical scheme is as follows: the 3D wafer comprises a wafer body and a metal layer; the metal layer is located on the upper surface of the wafer body.
The further technical scheme is as follows: the protective film is attached to the upper surface of the metal layer and is a UV film or a blue film.
The further technical scheme is as follows: the thickness of the wafer body is more than 750 microns, and the thickness of the metal layer is 10 microns-30 microns.
The further technical scheme is as follows: and in the step of grinding the lower surface of the 3D wafer for the first time, grinding the lower surface of the wafer body for the first time, wherein the first grinding thickness is more than 40 microns.
The further technical scheme is as follows: and in the step of performing laser treatment on the upper surface of the 3D wafer to remove the cutting path metal circuit layer to form a cutting path area, the depth of the cutting path area is the same as the thickness of the metal layer.
The further technical scheme is as follows: the laser power is 0.5W-4W.
The further technical scheme is as follows: and in the step of carrying out invisible cutting on the inside of the 3D wafer at the position of the cutting channel to form the modified layer, carrying out invisible cutting on the inside of the wafer body, wherein the distance between the depth of the invisible cutting and the surface of the wafer body is 35-100 micrometers.
The further technical scheme is as follows: and in the step of grinding the lower surface of the 3D wafer for the second time, grinding the lower surface of the wafer body for the second time, wherein the thickness of the grinding for the second time is more than 600 microns.
The further technical scheme is as follows: and in the step of separating the 3D wafer to form a plurality of monomer crystal grains, the 3D wafer is separated in a cold-hot expansion mode.
Compared with the prior art, the invention has the beneficial effects that: before the internal invisible cutting process of the 3D wafer, the metal circuit layer on the wafer cutting channel is removed through laser, so that the interference of the metal circuit layer on the crystal grains of the 3D wafer is removed in the cold and hot expanding process, effective separation is achieved, the grinding, thinning and separating yield of the ultrathin 3D wafer is realized, and the reliability of the product is improved.
The invention is further described below with reference to the accompanying drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a flow chart of a 3D wafer processing method according to the present invention;
FIG. 2 is a schematic structural diagram of a 3D wafer;
fig. 3 is a schematic view of an application scenario of processing of a 3D wafer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and the detailed description.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be connected or detachably connected or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above should not be understood to necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by one skilled in the art.
As shown in fig. 1 to 3, the present invention discloses a processing method of a 3D wafer, which includes the following steps:
s1, pasting a protective film on the upper surface of the 3D wafer;
in this embodiment, the 3D wafer includes a wafer body and a metal layer; the metal layer is located on the upper surface of the wafer body. The protective film is attached to the upper surface of the metal layer, and the protective film is a UV film, a blue film or other films and plays a role in protecting the metal layer.
The thickness of the wafer body is more than 750 microns, the thickness of the metal layer is 10-30 microns, and specific thickness values can be selected according to actual needs so as to be suitable for different application scenes.
S2, grinding the lower surface of the 3D wafer for the first time;
in the step of grinding the lower surface of the 3D wafer for the first time, the lower surface of the wafer body is ground for the first time, the first grinding thickness is larger than 40 micrometers, and specific thickness values can be selected according to actual needs so as to be suitable for different application scenarios.
S3, performing laser treatment on the upper surface of the 3D wafer to remove the cutting path metal circuit layer to form a cutting path area;
in the step of forming the cutting track area, the metal layer is subjected to laser to form a plurality of cutting track areas, and the depth of each cutting track area is the same as the thickness of the metal layer.
The laser power is 0.5W-4W, and the specific power value can be selected according to actual needs so as to be suitable for different application scenes.
S4, carrying out invisible cutting on the inside of the 3D wafer at the position of the cutting track area to form a modified layer;
in the step of performing invisible cutting on the inside of the 3D wafer at the position of the cutting track area to form the modified layer, the inside of the wafer body is subjected to invisible cutting, the distance between the depth of the invisible cutting and the surface (including the upper surface and the lower surface) of the wafer body is 35-100 micrometers, and specific depth values can be selected according to actual needs so as to be suitable for different application scenes.
The laser invisible cutting is that a single pulse of pulse laser is focused in the material through the surface of the material by optical shaping, the energy density is higher in a focal region to form a multi-photon absorption nonlinear absorption effect, so that the material is modified to form cracks, each laser pulse acts at equal intervals to form equal-interval damage, namely a modified layer can be formed in the material, the molecular bond of the material is broken at the position of the modified layer, and the connection of the materials is fragile and easy to separate.
After the modified layer is formed inside the 3D wafer, the edge is removed through circular cutting.
S5, carrying out secondary grinding on the lower surface of the 3D wafer;
in the step of grinding the lower surface of the 3D wafer for the second time, the lower surface of the wafer body is ground for the second time, the grinding thickness for the second time is more than 600 microns, and specific thickness values can be selected according to actual needs so as to be suitable for different application scenes.
And S6, separating the 3D wafer to form a plurality of monomer crystal grains.
And in the step of separating the 3D wafer to form a plurality of single crystal grains, the 3D wafer is separated in a cold-hot expansion mode.
The crystal grains are separated from each other in a cold-hot expanding mode, and the metal circuit layer in the cutting path area is removed, so that other stress interference is avoided, the crystal grains can be effectively separated from each other, the yield is improved, and the hidden danger is reduced.
As shown in fig. 2 to 3, in the application scenario of the 3D wafer processing of the present invention, a plurality of cutting streets (i.e., 20) are transversely and longitudinally distributed between the grains (i.e., 40) of the 3D wafer (i.e., 10), and since the metal layer (i.e., 30) of the cutting streets of the 3D wafer is thick, the grains 1 and 2 cannot be effectively separated in the cold-hot expanding process after the modified layer (i.e., 50) is formed, a laser grooving process is added, and the metal layer at the position of the cutting street region (i.e., 70) is removed by the laser head (i.e., 60), so that the grains 1 and 2 are successfully separated in the cold-hot expanding process.
According to the invention, before the lower surface of the 3D wafer is ground for the second time, laser grooving is firstly carried out on the cutting channel position of the 3D wafer, and the metal line layer of the cutting channel of the 3D wafer is burnt off by laser, so that the problem that the metal line layer cannot be expanded in the cold-hot expanding process after the 3D wafer is subjected to internal invisible cutting and secondary grinding and thinning is avoided, the problems of crystal grain connection, cracking and the like caused by the fact that the stress of the metal line layer cannot be released in the cold-hot expanding process after the 3D wafer is subjected to internal invisible cutting and grinding and thinning are solved, the thinning and separation yield of the 3D wafer can be improved, and the reliability of the product is improved.
The above embodiments are preferred implementations of the present invention, and the present invention can be implemented in other ways without departing from the spirit of the present invention.
Claims (10)
1. A processing technique method of a 3D wafer is characterized by comprising the following steps:
pasting a protective film on the upper surface of the 3D wafer;
grinding the lower surface of the 3D wafer for the first time;
the upper surface of the 3D wafer is subjected to laser to remove the cutting channel metal circuit layer, and a cutting channel area is formed;
carrying out invisible cutting on the inner part of the 3D wafer at the position of the cutting path area to form a modified layer;
carrying out second grinding on the lower surface of the 3D wafer;
and separating the 3D wafer to form a plurality of monomer crystal grains.
2. The processing method of the 3D wafer according to claim 1, wherein the 3D wafer comprises a wafer body and a metal layer; the metal layer is located on the upper surface of the wafer body.
3. The method as claimed in claim 2, wherein the protective film is attached to the upper surface of the metal layer, and the protective film is a UV film or a blue film.
4. The method as claimed in claim 2, wherein the wafer body has a thickness of 750 μm or more, and the metal layer has a thickness of 10-30 μm.
5. The method as claimed in claim 4, wherein in the step of polishing the lower surface of the 3D wafer for the first time, the lower surface of the wafer body is polished for the first time, and the thickness of the first polishing is greater than 40 μm.
6. The method as claimed in claim 2, wherein in the step of forming the scribe line region by laser-etching the top surface of the 3D wafer to remove the scribe line metal circuit layer, the depth of the scribe line region is the same as the thickness of the metal layer.
7. The method as claimed in claim 6, wherein the laser power is 0.5W-4W.
8. The processing method of the 3D wafer as claimed in claim 2, wherein in the step of forming the modified layer by invisibly cutting the inside of the 3D wafer at the position of the scribe line region, the invisibly cutting the inside of the wafer body is 35 to 100 microns deep from the surface of the wafer body.
9. The method as claimed in claim 2, wherein in the step of polishing the lower surface of the 3D wafer for the second time, the lower surface of the wafer body is polished for the second time, and the thickness of the second polishing is 600 μm or more.
10. The method as claimed in claim 2, wherein in the step of separating the 3D wafer into a plurality of single crystal grains, the 3D wafer is separated by cold-heat expansion.
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| CN202111027384.2A CN113725161A (en) | 2021-09-02 | 2021-09-02 | Processing technique method of 3D wafer |
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| CN202111027384.2A CN113725161A (en) | 2021-09-02 | 2021-09-02 | Processing technique method of 3D wafer |
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| CN114512412A (en) * | 2022-04-20 | 2022-05-17 | 苏州科阳半导体有限公司 | Surface acoustic wave filter wafer packaging method and chip |
| CN114551303A (en) * | 2022-02-24 | 2022-05-27 | 江苏京创先进电子科技有限公司 | Wafer cleaning device, wafer cleaning method and Taizhou ring cutting equipment |
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