CN113724595B - display panel - Google Patents
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- CN113724595B CN113724595B CN202111003332.1A CN202111003332A CN113724595B CN 113724595 B CN113724595 B CN 113724595B CN 202111003332 A CN202111003332 A CN 202111003332A CN 113724595 B CN113724595 B CN 113724595B
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- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000003990 capacitor Substances 0.000 claims abstract description 16
- 238000005538 encapsulation Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 230000008878 coupling Effects 0.000 description 14
- 238000010168 coupling process Methods 0.000 description 14
- 238000005859 coupling reaction Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The embodiment of the invention provides a display panel, which comprises a substrate base plate, a public electrode layer, a pixel electrode layer and an insulating layer arranged between the public electrode layer and the pixel electrode layer; the common electrode layer comprises a plurality of first electrodes which are distributed at intervals; the pixel electrode layer comprises a plurality of second electrodes which are distributed at intervals; the display panel also comprises a data line, wherein the data line is positioned between two adjacent second electrodes in the direction parallel to the substrate, and the distance from the edge of the data line to the edges of the second electrodes positioned at two sides of the data line is a first distance; orthographic projections on the substrate of the first electrode are overlapped with orthographic projection parts of the second electrodes positioned at two sides of the data line on the substrate so as to form a pixel storage capacitor between the first electrode and the second electrode; the first distance satisfies that the pixel storage capacitance can reach a specified capacitance value. The display panel provided by the invention can effectively improve the pixel storage capacitance so as to ensure the discharge duration of each pixel of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel.
Background
Currently, large-sized display panels are favored by a large number of users by virtue of large picture size, high resolution, and the like. Specifically, the large-sized display panel generally refers to a display panel of 27 inches and more. The existing large-size display panel generally has the characteristics of short charging time and long holding time. Therefore, in order to meet the charging requirement, a large-sized display panel generally needs to use a large-sized Thin Film Transistor (TFT) to increase the on-current (Ion) of the whole display panel so as to increase the charging rate of the whole display panel.
However, a large parasitic capacitance often exists between the scan line (Gate) and the source in the large-sized thin film transistor, so if the pixel storage capacitance (Cst) in the display panel is too small, the problem that the pixel voltage (Vpixel) is affected by the capacitive coupling effect when the scan line or the Data line (Data) is turned on and off to cause the display panel to flicker is easily caused, and if the pixel storage capacitance in the display panel is too small, the voltage charged in the display panel cannot be kept for a long enough time for displaying the picture.
Disclosure of Invention
The embodiment of the invention aims at solving at least one of the technical problems in the prior art, and provides a display panel which can effectively improve pixel storage capacitance so as to ensure the discharge duration of each pixel of the display panel and avoid flickering of the display panel due to capacitive coupling.
A display panel according to the present invention includes a substrate, a common electrode layer and a pixel electrode layer provided on the substrate, and an insulating layer provided between the common electrode layer and the pixel electrode layer; wherein,,
the public electrode layer comprises a plurality of first electrodes which are distributed at intervals; the pixel electrode layer comprises a plurality of second electrodes which are distributed at intervals;
the display panel further comprises a data line, wherein the data line is positioned between two adjacent second electrodes in the direction parallel to the substrate, and the distance from the edge of the data line to the edges of the second electrodes positioned at two sides of the data line is a first distance;
orthographic projections of the first electrode on the substrate are overlapped with orthographic projection parts of the second electrodes on the two sides of the data line on the substrate, so that a pixel storage capacitor is formed between the first electrode and the second electrode;
the first distance satisfies that the pixel storage capacitance can reach a specified capacitance value.
Optionally, the first distance is less than or equal to 2.3um.
Optionally, the display device further comprises a scanning line, wherein the scanning line is positioned on one side of the common electrode layer, which is far away from the pixel electrode layer, and orthographic projections of the scanning line in the direction of the substrate are positioned between orthographic projections of two adjacent second electrodes in the direction of the substrate;
in the direction parallel to the substrate, the distance between the edges of two adjacent second electrodes and the edge of the scanning line is a second distance.
Optionally, the second distance is less than or equal to 1.8um.
Optionally, the common electrode layer further includes a plurality of third electrodes, the third electrodes are distributed at intervals, and orthographic projections of the third electrodes in the substrate direction overlap orthographic projections of the second electrodes in the substrate direction.
Optionally, the pixel electrode further comprises an encapsulation layer, wherein the encapsulation layer is located on one side of the pixel electrode layer, which is far away from the insulation layer.
Optionally, the display device further comprises a buffer layer, wherein the buffer layer is positioned on one side of the packaging layer away from the pixel electrode layer;
the data line is formed on a surface of the buffer layer, which is far away from the encapsulation layer.
Optionally, the packaging structure further comprises an active layer, wherein the active layer is positioned on one side of the buffer layer away from the packaging layer;
the data line is formed between opposite surfaces of the active layer and the buffer layer.
Optionally, the gate insulating layer is located at a side of the active layer away from the data line;
the scan line is formed on a surface of the gate insulating layer on a side thereof remote from the active layer.
Optionally, the pixel electrode layer and the common electrode layer are made of indium tin oxide material.
The embodiment of the invention has the following beneficial effects:
in the display panel provided by the embodiment of the invention, the data line is positioned between two adjacent second electrodes in the direction parallel to the substrate, so that if the distance from the edges of two sides of the data line to the edges of the second electrodes positioned at two sides of the data line is smaller, the overlapping area of the first electrodes and the second electrodes positioned at two sides of the data line is larger, and vice versa. Therefore, the first distance is set to meet the condition that the pixel storage capacitor can reach the specified capacitance value, and the capacitance value of the pixel storage capacitor formed between the first electrode and the second electrode can be adjusted to the expected specified capacitance value, so that the charging voltage of the display panel can be kept for a sufficient time for displaying a picture.
Drawings
Fig. 1 is a partial sectional view of a display panel according to an embodiment of the present invention;
FIG. 2 is a partial cross-sectional view of a display panel according to an embodiment of the present invention;
FIG. 3 is a partial top view of a display panel according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for forming a plurality of films in a display panel according to an embodiment of the present invention;
fig. 5 is a plot of test data for the correspondence between (Cpd-Cpd')/Cst values and pull voltages between pixel electrodes and data lines for a plurality of display panels at different first distances L1.
Detailed Description
In order to enable those skilled in the art to better understand the technical scheme of the present invention, the following describes the display panel provided by the present invention in detail with reference to the accompanying drawings.
Referring to fig. 1, the present embodiment provides a display panel, which includes a substrate 1, a common electrode layer 2 and a pixel electrode layer 3 disposed on the substrate 1, and an insulating layer 4 disposed between the common electrode layer 2 and the pixel electrode layer 3, wherein the insulating layer 4 is SiN, for example x A material layer; the common electrode layer 2 includes a plurality of first electrodes 21 spaced apart from each other, the first electrodes 21 serving as common electrodes of the display panel; the pixel electrode layer 3 includes a plurality of second electrodes 31 spaced apart from each other, and the second electrodes 31 serve as pixel electrodes of the display panel. Specifically, the display panel is, for example, a large-size Thin Film Transistor (TFT) display panel, and accordingly, in order to achieve a large-scale and high-resolution display effect, the number of pixels included in the large-size display panel is large and the density is high, so that the charge and discharge capacity of the large-size display panel in the display process is large, and therefore, a large enough pixel storage capacitor is required.
In order to solve the above-mentioned technical problem, the display panel provided in this embodiment further includes a data line 5, and in a direction parallel to the substrate 1, the data line 5 is located between two adjacent second electrodes 31, that is, two second electrodes 31 located at both sides of the data line 5 are not overlapped with the data line 5; the distance from the edge of the data line 5 to the edge of the second electrode 31 on both sides thereof is the first distance L1.
The orthographic projections of the first electrode 21 on the substrate 1 overlap with orthographic projection portions of the second electrode 31 on the substrate 1 on both sides of the data line 5 to form a pixel storage capacitance between the first electrode 21 and the second electrode 31 for storing a pixel voltage. As is apparent from the sectional view shown in fig. 1, the smaller the first distance L1 is, the larger the area where the first electrode 21 and the two second electrodes 31 located on both sides of the data line 5 overlap with each other, with the data line 5 and the first electrode 21 being fixed in size.
As shown in fig. 1, the first electrode 21 and the second electrode 31 can be regarded as one parallel plate capacitor, i.e., a portion where the first electrode 21 and the second electrode 31 overlap each other forms a pixel storage capacitor for storing a pixel voltage. The capacitance of the parallel plate capacitor is defined as:
wherein ε r K is the static constant, S is the facing area of the two plates, and d is the distance between the two plates. As can be seen from the above formula, the smaller the thickness of the insulating layer 4 between the first electrode 21 and the second electrode 31, the larger the pixel storage capacitance; further, the larger the overlapping area of the first electrode 21 and the second electrode 31 in the direction parallel to the substrate 1, the larger the pixel storage capacitance. However, in the case of the conventional film formation technique, the thickness of the insulating layer 4 between the first electrode 21 and the second electrode 31 cannot be infinitely small, and specifically, the distance in the vertical direction between the first electrode 21 and the second electrode 31 is generally equal to or lessFor example +.>Therefore, the overlapping area of the first electrode 21 and the second electrode 31 can be increasedThe pixel storage capacitance is improved. As is clear from the above, the smaller the first distance L1, the larger the area where the first electrode 21 and the two second electrodes 31 located on both sides of the data line 5 overlap, and therefore, by setting the first distance L1 to a desired specified distance, the desired specified area can be reached at the portion where the first electrode 21 and the two second electrodes 31 overlap, so that the pixel storage capacitance between the first electrode 21 and the second electrode 31 can reach the desired specified capacitance value to satisfy the charge and discharge requirements of the large-sized display panel: the charge in the pixel storage capacitor can be maintained for a sufficient period of time for the display of the picture.
Based on the above theory, in order to make the pixel storage capacitance of the display panel sufficiently large, the larger the overlapping area of the first electrode 21 and the second electrode 31 is, the better, and accordingly, the smaller the first distance L1 is, the better. However, as shown in fig. 1, although the data line 5 and the two second electrodes 31 adjacent thereto do not overlap in the direction parallel to the substrate 1, a coupling capacitance (Cpd) is formed between the data line 5 and the second electrodes 31 due to the distributed capacitance effect; when the data line 5 transmits high frequency data signals, the coupling capacitor interferes with the signals transmitted in the data line 5, and when the data line 5 is turned on and off, the coupling capacitor affects the pixel voltage, thereby causing flickering of the display panel. The closer the distance between the data line 5 and the second electrode 31 is, the larger the coupling capacitance formed between the two is, and the larger the influence on the pixel voltage is; however, if the two first distances L1 from the data line 5 to the two second electrodes 31 adjacent thereto are completely equal, the influence of the coupling capacitance generated between the data line 5 and the two second electrodes 31 on the pixel voltage can be canceled out, so that the signal crosstalk (crosstalk) between the data line 5 and the pixel electrode can be avoided. However, in the actual production process, the distance between the data line 5 and the second electrodes 31 on both sides, i.e., the first distance L1, inevitably has an error, and therefore, the first distance L1 between the data line 5 and the second electrodes 31 on both sides thereof is difficult to be equal, which results in that the coupling capacitances formed between the data line 5 and the second electrodes 31 on both sides thereof cannot be mutually offset, and thus signal crosstalk occurs. In a practical production process, the severity of signal crosstalk is generally characterized by (Cpd-Cpd ')/Cst, where Cpd and Cpd' refer to the capacitance values of the coupling capacitances formed by the data line 5 and the second electrodes 31 on both sides thereof, respectively, so that it can be seen that the greater the difference between the coupling capacitances formed by the data line 5 and the second electrodes 31 on both sides thereof, the more serious the signal crosstalk; and the smaller the pixel storage capacitance between the first electrode 21 and the second electrode 31, the more serious the signal crosstalk.
As can be seen from this, the first distance L1 cannot be too large to cause the pixel storage capacitance to be too small, nor cannot the first distance L1 be too small to cause the coupling capacitance (Cpd) to be too large, and thus the signal crosstalk between the data line 5 and the pixel electrode is likely to occur. In some preferred embodiments, the first distance L1 is less than or equal to 2.3um. As shown in fig. 5, the inventors performed multiple simulation tests on the correspondence between (Cpd-Cpd ')/Cst values of display panels having different first distances L1 and the pull voltages between the pixel electrodes and the data lines, specifically, the broken line a shown in fig. 5 represents a display panel having a first distance L1 of 2.3um, and the broken lines b, c, d respectively represent display panels having a first distance L1 gradually greater than 2.3um, as can be seen from fig. 5, as the pull voltages between the pixel electrodes and the data lines increase, the value of (Cpd-Cpd')/Cst of the display panel having a first distance L1 of 2.3um represented by the broken line a is the smallest, and accordingly, the signal crosstalk phenomenon is least likely to occur.
Moreover, although the larger the overlapping area of the first electrode 21 and the second electrode 31, the larger the pixel storage capacitance, the width of the data line 5 disposed between the two second electrodes 31 cannot be too small in order to ensure stable transmission of the data signal, specifically, in some embodiments, the width of the data line 5 is, for example, 3um.
In some embodiments, as shown in fig. 2, the display panel further includes scan lines 6. The scanning line 6 is located on a side of the common electrode layer 2 remote from the pixel electrode layer 3. Moreover, the orthographic projection of the scanning line 6 in the direction of the substrate 1 is located between orthographic projections of the adjacent two second electrodes 31 in the direction of the substrate 1, and the distances from the edges of the adjacent two second electrodes 31 to the edges of the scanning line 6 in the direction parallel to the substrate 1 are both the second distances L2. As can be seen from the figure, the smaller the second distance L2, the larger the area where the first electrode 21 and the two second electrodes 31 located at both sides of the data line 5 overlap, so that the pixel storage capacitance formed between the first electrode 21 and the second electrodes 31 is larger.
As shown in fig. 3, the scanning lines 6 extend laterally and are arranged at intervals in a direction parallel to the surface of the display panel; the data lines 5 extend longitudinally and are arranged at intervals. Specifically, fig. 1 is a sectional view perpendicular to the extending direction of the data line 5, fig. 2 is a sectional view perpendicular to the extending direction of the scanning line 6, and referring to fig. 1 and 2 in combination, based on the same principle, by reducing the first distance L1 and the second distance L2, the overlapping area of the first electrode 21 and the second electrode 31 can be increased from the extending direction of the data line 5 and from the extending direction of the scanning line 6, that is, the overlapping area of the first electrode 21 and the second electrode 31 can be increased from two mutually perpendicular directions, respectively, so that the pixel storage capacitance formed between the first electrode 21 and the second electrode 31 can be made as large as possible. Moreover, the same is based on the distributed capacitance effect, i.e. a distributed capacitance is formed between any two insulated conductors with a voltage difference, a coupling capacitance is also formed between the second electrode 31 and the scan line 6, and when the scan line 6 transmits a high frequency scan signal, the coupling capacitance also interferes with the signal transmitted in the scan line 6, and when the scan line 6 is turned on and off, the coupling capacitance affects the pixel voltage, thereby causing flicker of the display panel. Therefore, the second distance L2 cannot be too large to cause the pixel storage capacitance to be too small, and the second distance L2 cannot be too small to cause the coupling capacitance to be too large.
In some preferred embodiments, the second distance L2 is less than or equal to 1.8um. Moreover, in order to ensure stable transmission of the scan signal, the width of the scan line 6 disposed between the two second electrodes 31 cannot be too small, specifically, in some embodiments, the width of the data line 5 is, for example, 3.5um.
After testing a plurality of pixel storage capacitors of a plurality of different display panels, the inventor finds that, under the condition that the thicknesses of the insulating layers are equal, compared with the display panel in the prior art in which the first distance L1 is set to 5.0um and the second distance L2 is set to 3.0um, the pixel storage capacitor of the display panel in which the first distance L1 is set to 2.3um and the second distance L2 is set to 1.8um can be improved by 33.5%.
In some embodiments, the common electrode layer 2 further includes a plurality of third electrodes 22 serving as a common electrode of the display panel. The third electrodes 22 are spaced apart, for example, in the display panel shown in fig. 3, and each of the third electrodes 22 is in the form of a stripe and is spaced apart between the scan lines 6 and the data lines 5, i.e., is distributed in a plurality of regions framed by the staggered scan lines 6 and data lines 5. The orthographic projection of the third electrode 22 in the direction of the substrate 1 overlaps with the orthographic projection of the second electrode 31 in the direction of the substrate 1 to form a pixel storage capacitance between the second electrode 31 and the third electrode 22.
In some embodiments, the display panel further comprises an encapsulation layer 7, the encapsulation layer 7 being located on a side of the pixel electrode layer 3 remote from the insulating layer 4. Specifically, the encapsulation layer 7 is, for example, a resin substrate, and the resin substrate is provided between the data line and the pixel electrode layer, so that the load on the data line can be reduced, and the power consumption of the display panel can be reduced, and particularly, the power consumption of a large-sized display panel can be effectively reduced.
In some embodiments, the display panel further includes a buffer layer 8, the buffer layer 8 being located on a side of the encapsulation layer 7 away from the pixel electrode layer 3; the data line 5 is formed on a side surface of the buffer layer 8 remote from the encapsulation layer 7.
In some embodiments, the display panel further comprises an active layer 9 (ACT), the active layer 9 being located on a side of the buffer layer 8 remote from the encapsulation layer 7; the data line 5 is formed between opposite surfaces of the active layer 9 and the buffer layer 8.
In some embodiments, the aforementioned gate insulating layer 10 is located on a side of the active layer 9 remote from the data line 5. The scanning line 6 is formed on a side surface of the gate insulating layer 10 remote from the active layer 9.
In some embodiments, the pixel electrode layer 3 and the common electrode layer 2 are both made of an Indium Tin Oxide (ITO) material to improve light transmittance of the display panel.
As another technical solution, as shown in fig. 4, the present embodiment further provides a method for forming multiple film layers in a display panel, which specifically includes the following steps:
s1: forming a pattern of scanning lines 6 on a substrate 1;
s2: forming a gate insulating layer 10 on the substrate 1 on which the pattern of the scanning lines 6 is formed;
s3: forming an active layer 9 on the gate insulating layer 10;
s4: forming a pattern of signal lines 5 on the active layer 9;
s5: forming a buffer layer 8 on the active layer 9 on which the pattern of the signal line 5 is formed;
s6: forming an encapsulation layer 7 on the buffer layer 8;
s7: forming a pixel electrode layer 3 including a pattern of a plurality of second electrodes 31 on the encapsulation layer 7;
s8: forming an insulating layer 4 on the pixel electrode layer 3;
s9: a common electrode layer 2 including a plurality of patterns of first electrodes 21 and third electrodes 22 is formed on the insulating layer 4.
In the display panel provided in this embodiment, the data line is located between two adjacent second electrodes in a direction parallel to the substrate, so if the distance from the edges of two sides of the data line to the edges of the second electrodes located at two sides of the data line is smaller, the overlapping area between the first electrodes and the second electrodes located at two sides of the data line is larger, and vice versa. Therefore, the first distance is set to meet the condition that the pixel storage capacitor can reach the specified capacitance value, and the capacitance value of the pixel storage capacitor formed between the first electrode and the second electrode can be adjusted to the expected specified capacitance value, so that the charging voltage of the display panel can be kept for a sufficient time for displaying a picture.
In the description of the embodiments of the present invention, it should be understood that the terms "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely to facilitate description of the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In describing embodiments of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (9)
1. A display panel characterized by comprising a substrate base, a common electrode layer and a pixel electrode layer provided on the substrate base, and an insulating layer provided between the common electrode layer and the pixel electrode layer; wherein,,
the public electrode layer comprises a plurality of first electrodes which are distributed at intervals; the pixel electrode layer comprises a plurality of second electrodes which are distributed at intervals;
the display panel further comprises a data line, wherein the data line is positioned between two adjacent second electrodes in the direction parallel to the substrate, and the distance from the edge of the data line to the edges of the second electrodes positioned at two sides of the data line is a first distance;
orthographic projections of the first electrode on the substrate are overlapped with orthographic projection parts of the second electrodes on the two sides of the data line on the substrate, so that a pixel storage capacitor is formed between the first electrode and the second electrode;
the first distance satisfies that the pixel storage capacitance can reach a specified capacitance value; the first distance is less than or equal to 2.3um.
2. The display panel according to claim 1, further comprising a scanning line which is located on a side of the common electrode layer close to the pixel electrode layer, and an orthographic projection of the scanning line in the substrate direction is located between orthographic projections of adjacent two of the second electrodes in the substrate direction;
in the direction parallel to the substrate, the distance between the edges of two adjacent second electrodes and the edge of the scanning line is a second distance.
3. The display panel of claim 2, wherein the second distance is less than or equal to 1.8um.
4. The display panel of claim 1, wherein the common electrode layer further comprises a plurality of third electrodes, the third electrodes are spaced apart and an orthographic projection of the third electrodes in the substrate direction overlaps an orthographic projection of the second electrodes in the substrate direction.
5. The display panel according to claim 2, further comprising an encapsulation layer located on a side of the pixel electrode layer remote from the insulating layer.
6. The display panel according to claim 5, further comprising a buffer layer located on a side of the encapsulation layer away from the pixel electrode layer;
the data line is formed on a surface of the buffer layer, which is far away from the encapsulation layer.
7. The display panel of claim 6, further comprising an active layer located on a side of the buffer layer remote from the encapsulation layer;
the data line is formed between opposite surfaces of the active layer and the buffer layer.
8. The display panel according to claim 7, further comprising a gate insulating layer on a side of the active layer remote from the data line;
the scan line is formed on a surface of the gate insulating layer on a side thereof remote from the active layer.
9. The display panel according to claim 1, wherein the pixel electrode layer and the common electrode layer are each made of an indium tin oxide material.
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