CN113724595A

CN113724595A - Display panel

Info

Publication number: CN113724595A
Application number: CN202111003332.1A
Authority: CN
Inventors: 唐亮珍; 王建; 张勇; 秦相磊; 段智龙; 边若梅; 金红贵; 张武霖; 许星; 俞兆虎; 段金帅
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2021-08-30
Filing date: 2021-08-30
Publication date: 2021-11-30
Anticipated expiration: 2041-08-30
Also published as: CN113724595B

Abstract

The embodiment of the invention provides a display panel, which comprises a substrate, a common electrode layer, a pixel electrode layer and an insulating layer arranged between the common electrode layer and the pixel electrode layer; the common electrode layer comprises a plurality of first electrodes distributed at intervals; the pixel electrode layer comprises a plurality of second electrodes distributed at intervals; the display panel also comprises a data line, wherein in the direction parallel to the substrate base plate, the data line is positioned between two adjacent second electrodes, and the distance from the edge of the data line to the edge of the second electrode positioned at two sides of the data line is a first distance; orthographic projections on the first electrode substrate are overlapped with orthographic projections, on the substrate, of the second electrodes positioned on two sides of the data line, so that pixel storage capacitors are formed between the first electrodes and the second electrodes; the first distance satisfies that the pixel storage capacitance can reach a specified capacitance value. The display panel provided by the invention can effectively improve the pixel storage capacitance so as to ensure the discharge time of each pixel of the display panel.

Description

Display panel

Technical Field

The invention relates to the technical field of display, in particular to a display panel.

Background

At present, a large-sized display panel is favored by users due to advantages of large picture size, high resolution and the like. Specifically, the large-sized display panel generally refers to a display panel of 27 inches or more. The existing large-size display panel generally has the characteristics of short charging time and long holding time. Therefore, in order to meet the charging requirement, a large-sized Thin Film Transistor (TFT) is usually selected to increase the on current (Ion) of the entire display panel, so as to increase the overall charging rate of the display panel.

However, in the large-sized thin film transistor, a large parasitic capacitance is often present between the scan line (Gate) and the source electrode, and therefore, if the pixel storage capacitance (Cst) in the display panel is too small, the pixel voltage (Vpixel) is easily affected by the capacitive coupling effect when the scan line or the Data line (Data) is turned on and off, and the display panel flickers.

Disclosure of Invention

Embodiments of the present invention are directed to at least one of the technical problems in the prior art, and provide a display panel, which can effectively improve a pixel storage capacitor, so as to ensure a discharge time of each pixel of the display panel, and can prevent the display panel from flickering due to capacitive coupling.

The display panel is characterized by comprising a substrate, a common electrode layer and a pixel electrode layer which are arranged on the substrate, and an insulating layer arranged between the common electrode layer and the pixel electrode layer; wherein the content of the first and second substances,

the common electrode layer comprises a plurality of first electrodes distributed at intervals; the pixel electrode layer comprises a plurality of second electrodes distributed at intervals;

the display panel further comprises a data line, the data line is positioned between two adjacent second electrodes in the direction parallel to the substrate base plate, and the distance from the edge of the data line to the edge of the second electrode positioned on the two sides of the data line is a first distance;

orthographic projections of the first electrodes on the substrate are overlapped with orthographic projections of the second electrodes on the substrate, wherein the orthographic projections of the second electrodes are positioned on two sides of the data lines, so that pixel storage capacitors are formed between the first electrodes and the second electrodes;

the first distance satisfies that the pixel storage capacitor can reach a specified capacitance value.

Optionally, the first distance is less than or equal to 2.3 um.

Optionally, the scanning line is located on one side of the common electrode layer far away from the pixel electrode layer, and an orthographic projection of the scanning line in the substrate direction is located between orthographic projections of two adjacent second electrodes in the substrate direction;

in the direction parallel to the substrate base plate, the distance between the edge of each two adjacent second electrodes and the edge of each scanning line is a second distance.

Optionally, the second distance is less than or equal to 1.8 um.

Optionally, the common electrode layer further includes a plurality of third electrodes, the third electrodes are distributed at intervals, and an orthogonal projection of the third electrodes in the substrate direction overlaps with an orthogonal projection of the second electrodes in the substrate direction.

Optionally, the display device further comprises an encapsulation layer, wherein the encapsulation layer is located on one side of the pixel electrode layer, which is far away from the insulating layer.

Optionally, the liquid crystal display further comprises a buffer layer, wherein the buffer layer is located on one side of the encapsulation layer, which is far away from the pixel electrode layer;

the data line is formed on one side surface of the buffer layer far away from the packaging layer.

Optionally, the package structure further comprises an active layer, wherein the active layer is located on one side of the buffer layer away from the package layer;

the data line is formed between opposite surfaces of the active layer and the buffer layer.

Optionally, the gate insulating layer is located on one side of the active layer away from the data line;

the scanning line is formed on one side surface of the gate insulating layer far away from the active layer.

Optionally, the pixel electrode layer and the common electrode layer are both made of an indium tin oxide material.

The embodiment of the invention has the following beneficial effects:

in the display panel provided by the embodiment of the invention, the data line is located between two adjacent second electrodes in a direction parallel to the substrate, so that if the distance from the two side edges of the data line to the edges of the second electrodes located at the two sides of the data line is smaller, the overlapping area between the first electrode and the second electrode located at the two sides of the data line is larger, and vice versa. Therefore, the embodiment of the invention can adjust the capacitance value of the pixel storage capacitor formed between the first electrode and the second electrode to a desired specified capacitance value by setting the first distance to satisfy the condition that the pixel storage capacitor can reach the specified capacitance value, thereby enabling the voltage charged by the display panel to be maintained for a sufficient period of time for the display of the picture.

Drawings

Fig. 1 is a partial cross-sectional view of a display panel according to an embodiment of the present invention;

FIG. 2 is a partial cross-sectional view of another display panel according to an embodiment of the present invention;

FIG. 3 is a partial top view of a display panel according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a method for forming a plurality of layers in a display panel according to an embodiment of the present invention;

fig. 5 is a test data line graph showing the correspondence between the (Cpd-Cpd')/Cst value of the display panel and the pull-in voltage between the pixel electrode and the data line for a plurality of different first distances L1.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the following detailed description of the display panel provided by the present invention is provided with reference to the accompanying drawings.

Referring to fig. 1, the present embodiment provides a display panel, which includes a substrate 1, a common electrode layer 2 and a pixel electrode layer 3 disposed on the substrate 1, and an insulating layer 4 disposed between the common electrode layer 2 and the pixel electrode layer 3, wherein the insulating layer 4 is, for example, SiN_xA layer of material; the common electrode layer 2 comprises a plurality of first electrodes 21 distributed at intervals, and the first electrodes 21 are used as common electrodes of the display panel; the pixel electrode layer 3 includes a plurality of second electrodes 31 spaced apart from each other, and the second electrodes 31 serve as pixel electrodes of the display panel. Specifically, the display panel is, for example, a large-sized Thin Film Transistor (TFT) display panel, and accordingly, in order to realize a large-format, high-resolution display effect, the large-sized display panelThe display panel has a large number of pixels and a high density, and therefore, the large-sized display panel requires a sufficiently large pixel storage capacitor because the large-sized display panel has a large charge and discharge amount during the display process.

In order to solve the above technical problem, the display panel provided by the present embodiment further includes a data line 5, and in a direction parallel to the substrate 1, the data line 5 is located between two adjacent second electrodes 31, that is, neither of the two second electrodes 31 located at both sides of the data line 5 overlaps with the data line 5; the distance from the edge of the data line 5 to the edge of the second electrode 31 located at both sides thereof is a first distance L1.

The orthographic projections of the first electrodes 21 on the substrate 1 are overlapped with the orthographic projections of the second electrodes 31 on both sides of the data lines 5 on the substrate 1 to form pixel storage capacitors between the first electrodes 21 and the second electrodes 31 for storing pixel voltages. As is apparent from the sectional view shown in fig. 1, the smaller the first distance L1 is, the larger the area where the first electrode 21 and the two second electrodes 31 located at both sides of the data line 5 overlap, under the condition that the sizes of the data line 5 and the first electrode 21 are fixed.

As shown in fig. 1, the first electrode 21 and the second electrode 31 can be regarded as a parallel plate capacitor, i.e. the overlapping part of the first electrode 21 and the second electrode 31 forms a pixel storage capacitor for storing a pixel voltage. And the capacitance value of the parallel plate capacitor is defined as:

wherein epsilon_rIs the relative dielectric constant, k is the electrostatic constant, S is the facing area of the two plates, and d is the distance between the two plates. As can be seen from the above formula, the smaller the thickness of the insulating layer 4 between the first electrode 21 and the second electrode 31 is, the larger the pixel storage capacitance is; further, the larger the overlapping area of the first electrode 21 and the second electrode 31 in the direction parallel to the substrate 1, the larger the pixel storage capacitance. However, in the case of the conventional film formation technique, the insulating layer 4 is formed between the first electrode 21 and the second electrode 31The thickness cannot be infinitely small, and specifically, the distance in the vertical direction between the first electrode 21 and the second electrode 31 is usually not more than

For example, is

Therefore, the pixel storage capacitance can be increased by increasing the overlapping area of the first electrode 21 and the second electrode 31. As can be seen from the above, the smaller the first distance L1, the larger the area of the first electrode 21 overlapping with the two second electrodes 31 located on both sides of the data line 5, and therefore, the first distance L1 can be set to a desired specified distance to make the portion of the first electrode 21 overlapping with the two second electrodes 31 reach a desired specified area, so that the pixel storage capacitance between the first electrode 21 and the second electrode 31 can reach a desired specified capacitance value to meet the charging and discharging requirements of the large-sized display panel: the voltage charged in the pixel storage capacitor can be maintained for a sufficient period of time for the display of the picture.

Based on the above theory, in order to make the pixel storage capacitance of the display panel sufficiently large, the larger the overlapping area of the first electrode 21 and the second electrode 31 is, the better, and correspondingly, the smaller the first distance L1 is, the better. However, as shown in fig. 1, although the data line 5 and the two second electrodes 31 adjacent to the data line do not overlap in the direction parallel to the substrate 1, a coupling capacitance (Cpd) is formed between the data line 5 and the second electrode 31 due to the distributed capacitance effect; when the data line 5 transmits a high frequency data signal, the coupling capacitor may interfere with the signal transmitted in the data line 5, and when the data line 5 is turned on or off, the coupling capacitor may affect the pixel voltage, thereby causing the display panel to flicker. The closer the distance between the data line 5 and the second electrode 31 is, the larger the coupling capacitance formed between the two is, and the larger the influence on the pixel voltage is; however, if the two first distances L1 from the data line 5 to the two adjacent second electrodes 31 are completely equal, the influence of the coupling capacitance generated between the data line 5 and the two second electrodes 31 on the pixel voltage can be cancelled, so that the signal crosstalk (crosstalk) between the data line 5 and the pixel electrode can be avoided. However, in an actual production process, there is an error inevitably in the distance from the data line 5 to the second electrodes 31 on both sides, i.e., the first distance L1, and therefore, the first distance L1 from the data line 5 to the second electrodes 31 on both sides is hardly equal, which may cause that the coupling capacitances formed between the data line 5 and the second electrodes 31 on both sides cannot cancel each other, and thus signal crosstalk occurs. In an actual production process, the severity of the signal crosstalk is generally represented by (Cpd-Cpd ')/Cst, where Cpd and Cpd' respectively refer to capacitance values of the coupling capacitances formed by the data line 5 and the second electrodes 31 on both sides of the data line, and thus it can be seen that the larger the difference between the coupling capacitances formed by the data line 5 and the second electrodes 31 on both sides of the data line, the more severe the signal crosstalk; and the smaller the pixel storage capacitance between the first electrode 21 and the second electrode 31, the more serious the signal crosstalk.

It can be seen that the first distance L1 is not too large to cause the pixel storage capacitance to be too small, and the first distance L1 is not too small to cause the coupling capacitance (Cpd) to be too large, thereby causing signal crosstalk between the data line 5 and the pixel electrode. In some preferred embodiments, the first distance L1 is less than or equal to 2.3 um. As shown in fig. 5, the inventor performed a plurality of simulation tests on the corresponding relationship between the (Cpd-Cpd ')/Cst value of the display panel having different first distances L1 and the pull-in voltage between the pixel electrode and the data line, specifically, the broken line a shown in fig. 5 represents the display panel having the first distance L1 of 2.3um, and the broken lines b, c, d represent the display panel having the first distance L1 gradually larger than 2.3um, respectively, and it can be seen from fig. 5 that, as the pull-in voltage between the pixel electrode and the data line increases, the (Cpd-Cpd')/Cst value of the display panel having the first distance L1 of 2.3um represented by the broken line a is the smallest, and accordingly, the signal crosstalk phenomenon is the least likely to occur.

Moreover, although the larger the overlapping area of the first electrode 21 and the second electrode 31 is, the larger the pixel storage capacitance is, in order to ensure stable transmission of the data signal, the width of the data line 5 disposed between the two second electrodes 31 cannot be too small, specifically, in some embodiments, the width of the data line 5 is, for example, 3 um.

In some embodiments, as shown in FIG. 2, the display panel further includes scan lines 6. The scanning line 6 is located on a side of the common electrode layer 2 away from the pixel electrode layer 3. Moreover, the orthographic projection of the scanning line 6 in the substrate 1 direction is located between the orthographic projections of the two adjacent second electrodes 31 in the substrate 1 direction, and the distances from the edges of the two adjacent second electrodes 31 to the edge of the scanning line 6 in the direction parallel to the substrate 1 are both the second distance L2. As can be seen from the figure, the smaller the second distance L2, the larger the area of the first electrode 21 overlapping with the two second electrodes 31 located at both sides of the data line 5, so that the larger the pixel storage capacitance formed between the first electrode 21 and the second electrode 31.

It should be noted that, as shown in fig. 3, the scan lines 6 extend laterally and are arranged at intervals in a direction parallel to the surface of the display panel; the data lines 5 extend in the longitudinal direction and are arranged at intervals. Specifically, fig. 1 is a sectional view perpendicular to the extending direction of the data line 5, fig. 2 is a sectional view perpendicular to the extending direction of the scanning line 6, and with combined reference to fig. 1 and 2, by reducing the first distance L1 and the second distance L2, the overlapping area of the first electrode 21 and the second electrode 31 can be increased from the extending direction of the data line 5 and from the extending direction of the scanning line 6, respectively, that is, the overlapping area of the first electrode 21 and the second electrode 31 can be increased from two mutually perpendicular directions, based on the same principle, thereby making the pixel storage capacitance formed between the first electrode 21 and the second electrode 31 as large as possible. Moreover, also based on the distributed capacitance effect, that is, a distributed capacitance is formed between any two insulated conductors having a voltage difference, a coupling capacitance is also formed between the second electrode 31 and the scan line 6, and when the scan line 6 transmits a high-frequency scan signal, the coupling capacitance also interferes with the signal transmitted in the scan line 6, and when the scan line 6 is turned on and off, the coupling capacitance affects the pixel voltage, thereby causing the display panel to flicker. Therefore, the second distance L2 should not be too large to cause the pixel storage capacitance to be too small, and the second distance L2 should not be too small to cause the coupling capacitance to be too large.

In some preferred embodiments, the second distance L2 is less than or equal to 1.8 um. Moreover, in order to ensure stable transmission of the scan signal, the width of the scan line 6 disposed between the two second electrodes 31 cannot be too small, and specifically, in some embodiments, the width of the data line 5 is, for example, 3.5 um.

After the inventor has performed a plurality of tests on the pixel storage capacitors of a plurality of different display panels, it is found that, under the condition that the thicknesses of the insulating layers are all equal, compared with the display panel in the prior art in which the first distance L1 is set to be 5.0um and the second distance L2 is set to be 3.0um, the pixel storage capacitor of the display panel in which the first distance L1 is set to be 2.3um and the second distance L2 is set to be 1.8um provided in this embodiment can be improved by 33.5%.

In some embodiments, the common electrode layer 2 further includes a plurality of third electrodes 22 serving as common electrodes of the display panel. The third electrodes 22 are spaced apart, and in the display panel shown in fig. 3 as an example, each of the third electrodes 22 is in a stripe shape and is spaced apart between the scan lines 6 and the data lines 5, that is, in a plurality of areas framed by the scan lines 6 and the data lines 5 that are staggered. An orthogonal projection of the third electrode 22 in the direction of the substrate base 1 overlaps an orthogonal projection of the second electrode 31 in the direction of the substrate base 1 to form a pixel storage capacitance between the second electrode 31 and the third electrode 22.

In some embodiments, the display panel further comprises an encapsulation layer 7, the encapsulation layer 7 being located on a side of the pixel electrode layer 3 remote from the insulating layer 4. Specifically, the encapsulating layer 7 is, for example, a substrate made of a resin material, and the resin substrate is disposed between the data line and the pixel electrode layer, so that a load on the data line can be reduced, power consumption of the display panel can be reduced, and especially, power consumption of a large-sized display panel can be effectively reduced.

In some embodiments, the display panel further comprises a buffer layer 8, the buffer layer 8 being located on a side of the encapsulation layer 7 remote from the pixel electrode layer 3; the data line 5 is formed on a surface of the buffer layer 8 on a side away from the encapsulation layer 7.

In some embodiments, the display panel further comprises an active layer 9(ACT), the active layer 9 being located on a side of the buffer layer 8 remote from the encapsulation layer 7; the data line 5 is formed between the opposite surfaces of the active layer 9 and the buffer layer 8.

In some embodiments, the gate insulating layer 10 is located on a side of the active layer 9 away from the data line 5. The scan line 6 is formed on a surface of the gate insulating layer 10 on a side away from the active layer 9.

In some embodiments, the pixel electrode layer 3 and the common electrode layer 2 are made of Indium Tin Oxide (ITO) material to improve the light transmittance of the display panel.

As another technical solution, as shown in fig. 4, this embodiment further provides a method for forming a plurality of film layers in a display panel, which specifically includes the following steps:

s1: forming a pattern of scan lines 6 on a base substrate 1;

s2: forming a gate insulating layer 10 on the substrate 1 on which the pattern of the scanning line 6 is formed;

s3: forming an active layer 9 on the gate insulating layer 10;

s4: forming a pattern of signal lines 5 on the active layer 9;

s5: forming a buffer layer 8 on the active layer 9 on which the pattern of the signal line 5 is formed;

s6: forming an encapsulation layer 7 on the buffer layer 8;

s7: forming a pixel electrode layer 3 including a pattern of a plurality of second electrodes 31 on the encapsulation layer 7;

s8: forming an insulating layer 4 on the pixel electrode layer 3;

s9: a common electrode layer 2 including a plurality of patterns of the first electrode 21 and the third electrode 22 is formed on the insulating layer 4.

In the display panel provided by this embodiment, the data line is located between two adjacent second electrodes in a direction parallel to the substrate, so that if the distance from the two side edges of the data line to the edges of the second electrodes located at the two sides of the data line is smaller, the overlapping area between the first electrode and the second electrode located at the two sides of the data line is larger, and vice versa. Therefore, the embodiment of the invention can adjust the capacitance value of the pixel storage capacitor formed between the first electrode and the second electrode to a desired specified capacitance value by setting the first distance to satisfy the condition that the pixel storage capacitor can reach the specified capacitance value, thereby enabling the voltage charged by the display panel to be maintained for a sufficient period of time for the display of the picture.

In the description of the embodiments of the present invention, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.

In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A display panel is characterized by comprising a substrate base plate, a common electrode layer and a pixel electrode layer which are arranged on the substrate base plate, and an insulating layer arranged between the common electrode layer and the pixel electrode layer; wherein the content of the first and second substances,

2. The display panel according to claim 1, wherein the first distance is less than or equal to 2.3 um.

3. The display panel according to claim 1, further comprising a scan line which is located on a side of the common electrode layer away from the pixel electrode layer, and an orthogonal projection of the scan line in the substrate base direction is located between orthogonal projections of adjacent two of the second electrodes in the substrate base direction;

4. The display panel according to claim 3, wherein the second distance is less than or equal to 1.8 um.

5. The display panel according to claim 1, wherein the common electrode layer further comprises a plurality of third electrodes, the third electrodes are distributed at intervals, and an orthographic projection of the third electrodes in the substrate direction overlaps with an orthographic projection of the second electrodes in the substrate direction.

6. The display panel according to claim 3, further comprising an encapsulation layer on a side of the pixel electrode layer away from the insulating layer.

7. The display panel according to claim 6, further comprising a buffer layer on a side of the encapsulation layer away from the pixel electrode layer;

8. The display panel according to claim 7, further comprising an active layer on a side of the buffer layer away from the encapsulation layer;

9. The display panel according to claim 8, further comprising a gate insulating layer on a side of the active layer away from the data line;

10. The display panel according to claim 1, wherein the pixel electrode layer and the common electrode layer are each made of an indium tin oxide material.