CN113716517A - Full-printed array reading circuit and preparation method thereof - Google Patents
Full-printed array reading circuit and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a full-printing array reading circuit and a preparation method thereof. The reading circuit comprises two electrode layers and an insulating layer, wherein the electrode layers comprise unit electrodes and flat cables, the insulating layer is arranged between the two electrode layers, and the flat cables led out from the two electrode layers are mutually vertical or parallel. The preparation method comprises the steps of firstly printing the lowest electrode layer to prepare the unit electrode, then printing the insulating layer on the lowest electrode layer, and finally printing the uppermost electrode layer on the insulating layer. The full-printing array reading circuit adopts a mode of 'electrode-insulating layer-electrode' three-time printing to construct the array reading circuit, compared with FPC printing, the cost is reduced, the problems of insufficient soldering, prolonged rise time, reduced circuit speed and the like caused by a via hole process are solved, the preparation area of the reading circuit is larger, the application range is wider, and the flexibility is better. Meanwhile, the lowest layer is an interdigital electrode, so that the crosstalk between circuit rows and columns can be effectively reduced.
Description
Technical Field
The invention relates to the field of flexible sensors, in particular to a full-printed array reading circuit and a preparation method thereof.
Background
The rapid development of the application fields of artificial intelligence, robot intelligent sensing, human body health monitoring, industrial detection and the like puts forward an urgent need for high-performance flexible sensing, wherein the requirements for large-area and arrayed flexible sensing devices are particularly obvious, the flexible large-area array device at the present stage is usually formed by arranging two force sensitive layers between two layers of flexible reading electrode circuits and then packaging, and the preparation of the reading electrode circuit usually adopts two schemes: an up-down line type readout circuit and a single-side interdigital electrode type readout circuit.
The up-down line type readout circuit is directly realized by adopting a low-cost printing process, but the array device obtained based on the readout circuit has signal crosstalk, and the sensitivity of the sensor is reduced.
The single-side interdigital electrode type array reading circuit is usually a copper-based Flexible Printed Circuit (FPC) with a Polyimide (PI) substrate, can effectively reduce row and column signal crosstalk, and improves sensitivity and response speed, but the FPC preparation relates to a series of preparation processes and equipment such as photoetching, etching, via holes, silk-screen printing and the like, and is relatively high in cost. The via holes in the FPC preparation can cause the electrodes to be easily subjected to cold joint, meanwhile, the induced capacitance can prolong the rise time of signals and reduce the speed of a circuit, and the induced inductance can weaken the contribution of the bypass capacitance and weaken the filtering effect of the whole power supply system. Moreover, the FPC preparation is difficult to realize a large-area arrayed readout circuit, and in some use scenarios in the field of flexible sensors, the PI substrate of the FPC cannot have high flexibility as leather or fabric.
The invention patent CN200610066541.X discloses a three-dimensional nano-gap grid array microelectrode biosensor chip: a group of gold electrodes are arranged on an insulating layer substrate, a layer of insulating material film with nanometer-level thickness covers the electrodes, a group of electrodes which are vertically crossed with the lower electrodes are arranged on the insulating material, and the upper electrodes and the lower electrodes form a grid structure. The crossing of the upper and lower electrodes and the insulating layer around them are removed to form a micro flow cell for analyzing biological samples. A large sample analysis cell is constructed using a polymer on the entire chip. The electrode arrays in the two planes can be combined randomly to produce the electric field needed by separation, and the upper and lower electrodes at the cross point form a nano-gap impedance test sensor. The upper and lower electrodes in the patent of the invention are vertically crossed, although a layer of insulating material film with nanometer-level thickness exists between two layers of electrodes, the cross section of the electrodes and the insulating layer around the cross section of the electrodes are removed, so that the electrodes still generate crosstalk in the actual working process, and the accuracy of signals is influenced.
The invention patent CN201910280704.1 discloses a sandwich type large-area high-density flexible array sensor and a preparation method thereof: the sensor comprises an upper polar plate, a lower polar plate, an array pressure-sensitive layer and an insulating adhesive layer, wherein the array pressure-sensitive layer and the insulating adhesive layer are arranged between the upper polar plate and the lower polar plate, corresponding array electrodes and wires are arranged on the upper polar plate and the lower polar plate, the array electrodes are of a row-line structure, each row of electrodes are connected through the wires, and the position of the insulating adhesive layer corresponding to the array pressure-sensitive layer is hollowed. The preparation method comprises preparing upper and lower polar plates by screen printing; preparing a pressure-sensitive composite material; printing an uncured pressure-sensitive composite material on the array electrode on one of the polar plates by adopting a screen printing process to form an array pressure-sensitive layer; and (4) attaching the upper and lower polar plates through insulating glue. Although the row electrodes and the column electrodes are printed by screen printing in the invention patent, the manufacturing cost is saved, but the electrodes of the upper electrode layer and the lower electrode layer are connected by a lead, so crosstalk can be generated, and the measuring precision of the sensor is reduced.
Disclosure of Invention
Aiming at the problems of the flexible sensor array reading circuit in the prior stage, the invention provides a full-printing array reading circuit and a preparation method thereof, and the flexible sensor obtained by using the circuit and the preparation method thereof has more excellent performance.
The technical scheme of the invention is as follows:
a fully printed circuit comprising two electrode layers and an insulating layer, wherein: the two electrode layers comprise an upper electrode layer and a lower electrode layer, the upper electrode layer and the lower electrode layer comprise unit electrodes, the insulating layer is arranged between the two electrode layers and comprises an insulating tape and an insulating tape between the unit electrodes on the lower electrode layer, the uppermost unit electrode of the upper electrode layer is connected with the uppermost unit electrode of the lower electrode layer, and the rest unit electrodes except the uppermost unit electrode on the upper electrode layer are arranged on the insulating tape. The full printed circuit comprises a row-column vertical row line array circuit or a row-column parallel row line array circuit.
The row-column vertical row line array circuit comprises a row electrode layer and a column electrode layer. The column electrode layer comprises column electrodes and flat cables, the column electrodes comprise unit electrodes, pins on the left sides of the unit electrodes on each column of the electrodes are sequentially connected, and the flat cables are connected with pins of the unit electrodes at the lowest ends of the column electrodes. The row electrode layer comprises row electrodes and flat cables, the row electrodes comprise unit electrodes, unit electrode pins on each row of the row electrodes are sequentially connected, and the flat cables are connected with the pins of the unit electrodes at the rightmost end of the row electrodes. The flat cable on the column electrode layer is perpendicular to the flat cable on the row electrode layer.
Further, the insulating layer is composed of a plurality of lateral insulating tapes, and the insulating tapes are arranged in the horizontal direction between the unit electrodes of the column electrodes.
Furthermore, the flat cables on the column electrode layers are arranged along the vertical direction, and the flat cables on the row electrode layers are arranged along the horizontal direction.
Furthermore, the unit electrodes on the column electrode layer comprise a forward F-shaped electrode on the left side and a reverse F-shaped electrode which is symmetrical with the forward electrode on the right side, and the upper ends of the reverse electrodes are respectively connected with the unit electrodes on the row electrodes. Two centrosymmetric F-shaped electrodes form an interdigital electrode shape.
Furthermore, the flat cables on the column electrode layers are gathered into a bundle in the vertical direction, and the flat cables on the row electrode layers are gathered into a bundle in the horizontal direction; the flat cables on the column electrode layers are respectively connected with the rivets in the vertical direction, and the flat cables on the row electrode layers are respectively connected with the rivets in the horizontal direction.
The row-column parallel flat cable array circuit comprises an interdigital electrode layer and a row-column electrode layer, wherein the interdigital electrode layer comprises row-column interdigital electrodes, the row-column interdigital electrodes comprise unit interdigital electrodes, each row-column interdigital electrode is connected with the left pins of the unit interdigital electrodes on the row-column interdigital electrodes in sequence, the row-column electrode layer comprises row electrodes and column electrodes, the row electrodes comprise unit electrodes and flat cables, the pins of the unit electrodes on each row of the row electrodes are connected in sequence, the flat cables are connected with the pins of the rightmost end unit electrodes of the row electrodes, the column electrodes comprise the unit electrodes and the flat cables, the pins of the unit electrodes on each column of the column electrodes are connected in sequence, the flat cables are connected with the pins of the rightmost end unit electrodes of the column electrodes, and an insulating layer is arranged between the interdigital electrode layer and the row-column electrode layer. The row and column electrode layers are parallel to the upper electrodes.
Furthermore, the insulating layer is composed of a plurality of transverse insulating tapes, and the insulating tapes are arranged between the unit interdigital electrodes along the horizontal direction.
Furthermore, the row electrodes and the column electrodes of the row and column electrode layers are arranged rightwards along the horizontal direction.
Furthermore, each column electrode is provided with only one unit electrode, and the unit electrodes on different column electrodes are respectively connected with the unit electrodes of the interdigital electrodes on different columns.
Furthermore, the unit electrodes on the interdigital electrode layer comprise a forward F-shaped electrode on the left side and a reverse F-shaped electrode which is symmetrical with the center of the forward electrode on the right side, the forward electrode is connected with the unit electrodes on the column electrodes, and the reverse electrodes are respectively connected with the unit electrodes on the row electrodes.
The interdigital electrode formed by two centrosymmetric F-shaped electrodes is characterized in that the interdigital electrode is a generating electrode and a collecting electrode, so that chemical oxidation-reduction cycling reaction can be realized on the interdigital electrode, the interdigital electrode is characterized by high-sensitivity CV measurement, electrochemical measurement of a small amount of samples and high-speed response, crosstalk between electrode units on a circuit is reduced, and signal transmission precision is enhanced.
Furthermore, the row and column electrode layers are bundled by the row wires of the row electrodes and the column electrodes in the horizontal direction, or the row wires of the row electrodes and the column electrodes are respectively connected with the rivets in the horizontal direction.
Furthermore, the electrode layer is formed by printing oily conductive paste, and the insulating layer is formed by printing aqueous insulating paste.
The oily conductive paste comprises silver paste and carbon paste oily conductive paste.
The water-based insulating slurry comprises polyurethane, acrylate, epoxy resin and silicon rubber water-based insulating slurry. In order to improve the electrical insulation property of the aqueous printing coating, the aqueous insulation slurry comprises 5% -15% of hydroxylated silicon dioxide nanoparticles, and the diameters of the hydroxylated silicon dioxide nanoparticles are 50-200 nm. The hydroxylated silicon dioxide nano particles and aqueous polymer dispersions such as polyurethane, acrylate, epoxy resin or silicon rubber form group chain, and the insulating layer with high dielectric property is formed by annealing treatment at 100-150 ℃.
The solvents in the oily conductive paste and the aqueous insulating paste are orthogonal solvents, and the oily conductive paste and the aqueous insulating paste are not dissolved in each other in the processes of printing and film forming, so that the electrodes of the reading circuit are not short-circuited.
Furthermore, in order to improve the breakdown resistance of the read-out circuit, the thickness and the insulating property of the insulating layer can be increased by 2-4 times of printing, and the thickness of the insulating layer is 5-20 μm.
Further, the full-printed array reading circuit is in a periodic arrangement or an aperiodic arbitrary multi-cell arrangement, and the array size is m multiplied by n, wherein m is 1,2,3 … 128, n is 1,2,3 … 128, and m multiplied by n is larger than 4.
The preparation method of the full printed circuit comprises the following steps:
(1) printing the oily conductive paste for the first time to prepare the lower electrode layer;
(2) printing the aqueous insulating slurry on the lower electrode layer to prepare the insulating layer for the second time;
(3) and printing the oily conductive paste on the insulating layer to prepare the upper electrode layer by the third printing.
When the line array circuit with the vertical rows and columns is prepared, the first printing is to print the lowest row electrode layer by using oily conductive paste; the second printing is to print an insulating layer on the lowest electrode layer; the third printing is to print a row electrode layer on the insulating layer using an oily conductive paste.
And printing unit electrodes on the column electrode layer during first printing, wherein the unit electrodes comprise a positive F-shaped electrode on the left side and a reverse F-shaped electrode which is symmetrical with the positive electrode in the center, and the row wires of column electrode pins are prepared on the column electrode layer along the vertical direction.
And printing an insulating tape in the second printing process, and printing the insulating tape between the unit electrodes on the column electrode layer along the horizontal direction.
And printing unit electrodes on the row electrode layer during third printing, connecting the unit electrodes on the row electrode layer with the upper ends of the right reverse F-shaped electrodes of the unit electrodes on the column electrode layer, and preparing a flat cable of the row electrode pins on the row electrode layer along the horizontal direction.
Particularly, the flat cables on the column electrode layers are gathered into a bundle during the first printing, and the flat cables on the row electrode layers are gathered into a bundle during the third printing; or the flat cables on the column electrode layers are respectively connected with the rivets during the first printing, and the flat cables on the row electrode layers are respectively connected with the rivets during the third printing.
When a row-column parallel flat cable array circuit is prepared, the first printing is to prepare the lowest interdigital electrode layer by using oily conductive paste to prepare a unit electrode; printing an insulating layer on the lowermost interdigital electrode layer for the second time; the third printing is to print the row and column electrode layers on the insulating layer using an oily conductive paste.
And during the first printing, printing the left side of the unit electrode in the interdigital electrode layer into a forward F-shaped electrode, and printing the right side of the unit electrode into a reverse F-shaped electrode which is symmetrical with the forward electrode in center.
And printing an insulating tape between the unit electrodes on the interdigital electrodes along the horizontal direction during the second printing.
And preparing a row line of row electrodes and column electrode pins on the row and column electrode layers along the horizontal direction during the third printing, connecting the column electrodes on the row and column electrode layers with the left ends of the unit electrodes on the interdigital electrode layer, and connecting the row electrodes on the row and column electrode layers with the right ends of the unit electrodes on the interdigital electrode layer. In particular, the flat cables on the row and column electrode layers are gathered into a bundle or respectively connected with the rivets.
Further, annealing treatment is carried out on the lower electrode layer, the insulating layer and the upper electrode layer after the first printing, the second printing and the third printing, wherein the annealing treatment is to adjust the temperature of a vacuum oven to be 100-150 ℃, and then the lower electrode layer, the insulating layer and the upper electrode layer are heated and cured.
The invention has the advantages that: compared with FPC based on PI substrate, the full printing array reading circuit is constructed by adopting a three-time printing method of 'electrode-insulating layer-electrode', the printing cost is lower, and meanwhile, a via hole process of a double-layer plate is not needed, so that the phenomenon that insufficient soldering occurs when the array circuit is used, or the rising time of a signal is prolonged and the speed of the circuit is reduced due to parasitic capacitance, or the contribution of bypass capacitance is weakened due to induced inductance and the filtering effect of the whole power supply system is weakened is avoided. The interdigital electrode is used as the lowest layer of the circuit and is matched with the middle insulating layer and the top row electrode layer or the row and column electrode layer, and compared with an up-down row and column readout circuit, the interdigital readout circuit can effectively reduce crosstalk of the circuit, so that the prepared sensor is more accurate in precision and higher in sensitivity. The three-time printing method of 'electrode-insulating layer-electrode' can make the area of the prepared array reading circuit larger, thereby having wider application range. In addition, the array reading circuit can be directly prepared on the flexible elastic substrate by the preparation method, so that the obtained sensor has better flexibility compared with other sensors prepared by common processes.
Drawings
FIG. 1 is a schematic diagram of a fully printed row-column-vertical-row-line readout circuit.
FIG. 2 is a schematic diagram of a column electrode layer of a full-printed row-column vertical-row line readout circuit.
FIG. 3 is a schematic diagram of an insulating layer of a full-printing row-column vertical-row line readout circuit.
FIG. 4 is a schematic diagram of a row electrode layer of a fully printed row-column vertical row line readout circuit.
FIG. 5 is a schematic diagram of a rivet-connected full-print-array vertical bus line readout circuit.
FIG. 6 is a schematic diagram of a rivet-connected column electrode layer of a full-print-array vertical row line readout circuit.
FIG. 7 is a schematic diagram of a row electrode layer of a rivet-connected full-print-array vertical bus line readout circuit.
FIG. 8 is a schematic diagram of a fully printed row-column parallel-row line readout circuit.
FIG. 9 is a schematic diagram of an interdigital electrode layer of a full-printed row-column parallel-row line readout circuit.
FIG. 10 is a schematic diagram of row and column electrode layers of a fully printed row-column parallel line readout circuit.
FIG. 11 is a schematic diagram of a rivet-connected full-print row-column parallel line reading circuit.
FIG. 12 is a schematic diagram of an interdigital electrode layer of a rivet-connected full-printed row-column parallel-row readout circuit.
FIG. 13 is a schematic diagram of the row and column electrode layers of the rivet-connected fully printed row-column parallel line readout circuit.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The examples are given for the purpose of better illustration of the invention, but the invention is not limited to the examples. Therefore, those skilled in the art should make insubstantial modifications and adaptations to the embodiments of the present invention in light of the above teachings and remain within the scope of the invention.
Example 1
Referring to fig. 1, a schematic diagram of a fully printed row-column-vertical-row-line readout circuit according to the present invention is shown. Specifically, the fully printed row-column vertical flat cable readout circuit of the embodiment includes two electrode layers, an insulating layer and a flat cable, the insulating layer is between the two electrodes, the electrode layers are composed of unit electrodes, and the flat cable is led out from the unit electrodes on the two electrode layers.
The two electrode layers are prepared by printing conductive paste, and are respectively a column electrode layer and a row electrode layer. Fig. 3 is a schematic view of an insulating layer. The insulating layer is horizontally arranged between the electrode units on the column electrode layer, the row electrodes are arranged on the insulating layer and are intersected with the right ends of the unit electrodes on the column electrodes, and the flat cable led out by the column electrodes is perpendicular to the flat cable led out by the row electrodes. The array size of the array circuit is 8 × 8.
As shown in fig. 2 and 4, the flat cables led out from the column electrode layers are gathered in a bundle in the vertical direction, and the flat cables led out from the row electrode layers are gathered in a bundle in the horizontal direction.
Example 2
Referring to fig. 5, a schematic diagram of a rivet-connected full-print-array vertical bus line readout circuit according to the present invention is shown. Specifically, the fully printed row-column vertical flat cable readout circuit of the embodiment includes two electrode layers, an insulating layer and a flat cable, the insulating layer is between the two electrodes, the electrode layers are composed of unit electrodes, and the flat cable is led out from the unit electrodes on the two electrode layers.
The two electrode layers are prepared by printing conductive paste, the two electrode layers are a column electrode layer and a row electrode layer respectively, the insulating layers are horizontally arranged between the electrode units on the column electrode layer, the row electrode is arranged on the insulating layers and is intersected with the right end of the unit electrode on the column electrode, and the flat cable led out by the column electrode is perpendicular to the flat cable led out by the row electrode.
The flat cables led out from the column electrode layers are connected with the rivets in the vertical direction, and the flat cables led out from the row electrode layers are connected with the rivets in the horizontal direction, which is shown in fig. 6 and 7.
Example 3
Referring to fig. 8, a schematic diagram of a fully printed row-column parallel-row line readout circuit is shown.
The full-printing row-column parallel flat cable reading circuit comprises two electrode layers, an insulating layer and a flat cable.
The insulating layer is arranged between the two electrode layers, the electrode layers are composed of unit electrodes, the flat cable is led out from the unit electrodes on the two electrode layers, and the two electrode layers are prepared by screen printing of conductive paste.
The two electrode layers are divided into an interdigital electrode layer and a row and column electrode layer, the insulating layer is horizontally arranged between unit electrodes on the interdigital electrode layer, the row and column electrode layer is arranged on the insulating layer, the column electrode is connected with the left end of the unit electrode, and the row electrode is connected with the right end of the unit electrode.
The row and column electrode layer up electrodes and the row wires led out by the column electrodes are parallel to each other, and the row and column electrode layer up electrodes and the row wires led out by the column electrodes are gathered into a bundle in the horizontal direction. The unit electrodes on the interdigital electrode layer are two centrosymmetric 'F' shapes, and refer to fig. 9 and fig. 10.
Example 4
Referring to fig. 11, a schematic diagram of a rivet-connected fully-printed row-column parallel-row line readout circuit is shown.
The full-printing row-column parallel flat cable reading circuit comprises two electrode layers, an insulating layer and a flat cable.
The insulating layer is arranged between the two electrode layers, the electrode layers are composed of unit electrodes, the flat cable is led out from the unit electrodes on the two electrode layers, and the two electrode layers are prepared by screen printing of conductive paste.
The two electrode layers are divided into an interdigital electrode layer and a row and column electrode layer, the insulating layer is horizontally arranged between unit electrodes on the interdigital electrode layer, the row and column electrode layer is arranged on the insulating layer, the column electrode is connected with the left end of the unit electrode, and the row electrode is connected with the right end of the unit electrode.
The row and column electrode layer up electrodes and the flat cables led out from the column electrodes are parallel to each other, and the row and column electrode layer up electrodes and the flat cables led out from the column electrodes are connected with the rivets in the horizontal direction. The unit electrodes on the interdigital electrode layer are two centrosymmetric 'F' shapes, and refer to fig. 12 and fig. 13.
Example 5
A method for preparing a vertical array reading circuit by three times of printing comprises the following steps:
(1) and preparing oil-based silver paste for the first printing and the third printing, and preparing aqueous polyurethane paste for the second printing. The aqueous polyurethane slurry comprises polyurethane, and 5% -15% of hydroxylated silicon dioxide nanoparticles are added to improve the electrical insulating property of the aqueous printing coating, wherein the diameters of the nanoparticles are 50-200 nm. Based on hydroxylated silica nanoparticles, to form a radical chain with the aqueous polyurethane dispersion.
(2) Printing for the first time: the method comprises the steps of screen printing oily silver paste on a substrate to prepare a lowermost row electrode layer, preparing unit electrodes on the row electrode layer and leading out flat cables, wherein the unit electrodes are in two centrosymmetric F shapes, and the flat cables are gathered into a bundle in the vertical direction.
(3) The second printing is to print an aqueous polyurethane insulating layer on the lowermost row electrode layer, and the insulating layer is horizontally printed between the unit electrodes on the row electrodes
(4) And the third printing is that the oily silver paste is silk-screen printed on the waterborne polyurethane insulating layer, the uppermost row electrode layer is prepared, and the unit electrodes and the lead-out flat cables on the row electrode layer are prepared at the same time. The unit electrodes on the row electrode layer are connected with the right ends of the unit electrodes on the column electrode layer. The flat cables of the row electrode layers are along the horizontal direction and gathered into a bundle.
(5) And after the three times of printing, putting the array circuit into a vacuum oven at 150 ℃ for heating and curing to form a film.
Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.
Claims (10)
1. A full printed array readout circuit comprising two electrode layers and an insulating layer, wherein: the two electrode layers comprise an upper electrode layer and a lower electrode layer, the upper electrode layer and the lower electrode layer comprise unit electrodes, the insulating layer is arranged between the two electrode layers and comprises an insulating tape, the insulating tape is arranged on the lower electrode layer and between the unit electrodes, the unit electrode at the uppermost end of the upper electrode layer is connected with the unit electrode at the uppermost end of the lower electrode layer, and the rest unit electrodes except the uppermost unit electrode on the upper electrode layer are arranged on the insulating tape.
2. The fully printed array readout circuit of claim 1, wherein the fully printed circuit comprises a row-column vertical rowed array circuit or a row-column parallel rowed array circuit, wherein:
the row-column vertical rowed line array circuit comprises a row electrode layer and a row electrode layer, wherein the row electrode layer comprises row electrodes and rowed lines, the row electrodes comprise unit electrodes, left pins of the unit electrodes on each row of the row electrodes are sequentially connected, the rowed lines are connected with pins of the unit electrodes at the lowest ends of the row electrodes, the row electrode layer comprises row electrodes and rowed lines, the row electrodes comprise unit electrodes, pins of the unit electrodes on each row of the row electrodes are sequentially connected, the rowed lines are connected with pins of the unit electrodes at the rightmost ends of the row electrodes, and the rowed lines on the row electrode layer are perpendicular to the rowed lines on the row electrode layer;
the row-column parallel flat cable array circuit comprises an interdigital electrode layer and a row-column electrode layer, wherein the interdigital electrode layer comprises row-column interdigital electrodes, the row-column interdigital electrodes comprise unit interdigital electrodes, each row of the row-column interdigital electrodes are sequentially connected with the left pins of the unit interdigital electrodes on the row-column interdigital electrodes, the row-column electrode layer comprises row electrodes and column electrodes, the row electrodes comprise unit electrodes, flat cables and each row of the row electrodes, the pins of the unit electrodes on the row electrodes are sequentially connected, the flat cables are connected with the pins of the unit electrodes at the rightmost end of the row electrodes, the column electrodes comprise unit electrodes, flat cables and each row of the unit electrodes on the column electrodes, the flat cables are connected with the pins of the unit electrodes at the rightmost end of the column electrodes, and the insulating layer is arranged between the interdigital electrode layer and the row-column electrode layer.
3. The fully printed array readout circuit of claim 2, wherein: in the row-column vertical array circuit, the insulating tapes are arranged between the unit electrodes of the column electrodes along the horizontal direction; the flat cables on the column electrode layers are arranged along the vertical direction, and the flat cables on the row electrode layers are arranged along the horizontal direction; the unit electrodes on the column electrode layer comprise a positive F-shaped electrode on the left side and a reverse F-shaped electrode which is symmetrical with the positive electrode in the center on the right side, and the upper ends of the reverse electrodes are respectively connected with the unit electrodes on the row electrodes; the flat cables on the column electrode layers are gathered into a bundle in the vertical direction, and the flat cables on the row electrode layers are gathered into a bundle in the horizontal direction; or the flat cables on the column electrode layers are respectively connected with the rivets in the vertical direction, and the flat cables on the row electrode layers are respectively connected with the rivets in the horizontal direction.
4. The fully printed array readout circuit of claim 2, wherein: in the row-column parallel flat cable array circuit, the row electrodes are parallel to the column electrodes; the insulating tapes are arranged between the unit interdigital electrodes along the horizontal direction; the row and column electrode layer upper electrodes and the row lines of the column electrodes are arranged along the horizontal direction; each column electrode comprises a unit electrode, and the unit electrodes of the column electrodes are respectively connected with the unit electrodes of the interdigital electrodes in different columns; the unit electrodes on the interdigital electrode layer comprise a forward F-shaped electrode on the left side and a reverse F-shaped electrode which is centrosymmetric with the forward electrode on the right side, the forward electrode is connected with the unit electrodes on the column electrodes, and the reverse electrode is respectively connected with the unit electrodes on the row electrodes; the flat cables on the row and column electrode layers are gathered into a bundle in the horizontal direction or the flat cables on the row and column electrode layers are respectively connected with the rivet in the horizontal direction.
5. The fully printed array readout circuit of claim 1, wherein the electrode layer is printed from an oil-based conductive paste and the insulating layer is printed from an aqueous-based insulating paste, wherein:
the oily conductive paste comprises silver paste and carbon paste oily conductive paste;
the water-based insulating slurry comprises polyurethane, acrylate, epoxy resin and silicon rubber, and comprises 5-15% of hydroxylated silicon dioxide nanoparticles with the diameter of 50-200 nm.
6. The fully printed array readout circuit of claim 1, wherein: the insulating layer is formed by printing the water-based insulating slurry for 2-4 times, and the thickness of the insulating layer is 5-20 mu m.
7. The fully printed array readout circuit of claim 1, wherein: the full-printed array reading circuit is in a periodic arrangement or an aperiodic arbitrary multi-cell arrangement, and the array scale is m multiplied by n, wherein m is 1,2,3 … 128, n is 1,2,3 … 128, and m multiplied by n is larger than 4.
8. The method of fabricating a fully printed array readout circuit according to any of claims 1 to 7, comprising the steps of:
(1) printing the oily conductive paste for the first time to prepare the lower electrode layer;
(2) printing the aqueous insulating slurry on the lower electrode layer to prepare the insulating layer for the second time;
(3) and printing the oily conductive paste on the insulating layer to prepare the upper electrode layer by the third printing.
9. The method of making a fully printed array readout circuit of claim 8, wherein: and (2) preparing unit electrodes on a lower electrode layer during the first printing in the step (1), wherein the unit electrodes on the lower electrode layer comprise a forward F-shaped electrode on the left side and a reverse F-shaped electrode symmetrical to the center of the forward electrode on the right side.
10. The method of making a fully printed array readout circuit of claim 8, wherein: and after the first printing, the second printing and the third printing, annealing the lower electrode layer, the insulating layer and the upper electrode layer, wherein the annealing is to adjust the temperature of a vacuum oven to be 100-150 ℃, and then heating and curing the lower electrode layer, the insulating layer and the upper electrode layer.
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