CN113702816A

CN113702816A - Boundary scanning-based register unit design method

Info

Publication number: CN113702816A
Application number: CN202110991352.8A
Authority: CN
Inventors: 孙诚
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2021-08-26
Filing date: 2021-08-26
Publication date: 2021-11-26
Anticipated expiration: 2041-08-26
Also published as: CN113702816B

Abstract

The invention relates to the technical field of integrated circuits, in particular to a boundary scanning-based register unit design method.A capture _ en signal and an update _ en signal are added on the basis of a traditional boundary scanning register unit structure to serve as enabling ends of a capture trigger and an update trigger, and in the process of gradually optimizing a circuit from a complex circuit structure, a gate circuit with optimal performance is combined as far as possible according to performance parameters of the gate circuit to form an optimized bc _2 unit; in addition, in the optimization process aiming at the bc _7 unit, a method of independent function data flow analysis is adopted, functions to be realized by a single circuit are separated one by one, a data flow path of each function is analyzed, and various independent data flows are finally combined, so that redundant signals or circuit structures in the original circuit structure are abandoned.

Description

Boundary scanning-based register unit design method

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a register unit design method based on boundary scanning.

Background

Boundary scan, as an IEEE (1149.1) or jtag (joint Test Action group) standard, aims to realize controllability and observability of chip input and output pins, and further Test internal logic and interconnection of chips.

The basic boundary scan chain structure comprises a universal data port and a test data port, wherein the universal data port is used for interaction between an external Pin (PAD) and internal logic; the test data port is used for serial in of initial test data and serial out of test feedback data.

The boundary scan register is considered as the most important register in all registers in the IEEE 1149.1 standard and is placed at the boundary of the tested core logic circuit. Register cells enter between external Pins (PAD) and the core logic ports, which can improve the controllability and observability of core logic inputs and outputs. FIG. 1 shows a conventional boundary scan register unit structure, in which DataIn and DataOut are general data ports, and ScanIn and ScanOut are test data ports.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a boundary scan-based register unit design method, and the technical problem to be solved is how to optimize a BC unit on the basis of a traditional boundary scan register unit according to the design change of signals and the number of gate circuits.

In order to solve the technical problems, the technical scheme provided by the invention is as follows: a register unit design method based on boundary scanning is characterized in that capture _ en and update _ en signals are added on the basis of the traditional boundary scanning register unit structure to serve as enabling ends of a capture trigger and an update trigger;

after the simulation mode is started, test data are serially shifted into a scan chain through bc _2 units of each stage in sequence under the control of a shift _ dr signal and a capture _ en signal, and captured test data are output from a data output port under the enabling of an update _ en signal and a mode signal. When the data output port is respectively connected with the OEN and the I end of the PAD, the output function simulation can be completed under the condition that the OEN value is 0;

under the condition that the value of the OEN end is 1, the PAD port is assigned, the value of the C port of the PAD is located at the D input end of the capture register, and then under the control of a capture _ en signal and a shift _ dr signal, data in a capture state are serially shifted out of a scan chain through ScanIn and ScanOut ports of each stage of bc _2 units, so that the data at the output end of the PAD are observed, and the input function simulation can be completed.

And analyzing the data flow direction of the input and output simulation process in the test mode by utilizing the bidirectional test function of the bc _2 unit on the PAD, and fusing the bc _7 unit and the input and output simulation process to form the bc _7 unit. After the test data is shifted, the updated output data in the bc _2 unit is used for controlling the OEN port value of the corresponding PAD, so that the simulation of the input or output function of the PAD is determined, and the bc _7 unit at the later stage simultaneously realizes the bidirectional access of the PAD port data and the internal logic data, so that the corresponding simulation is performed according to the OEN value.

The beneficial effect that this technical scheme brought is: in the technical scheme, in the process from a complex circuit structure to an optimized circuit, the gate circuits with optimal performance are combined as far as possible according to the performance parameters of the gate circuits; in addition, in the optimization process aiming at the bc _7 unit, a method of independent function data flow analysis is adopted, functions to be realized by a single circuit are separated one by one, a data flow path of each function is analyzed, and various independent data flows are finally combined, so that redundant signals or circuit structures in the original circuit structure are abandoned.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a diagram of a conventional boundary scan register cell;

FIG. 2 is a diagram of the construction of the units of the Synopsys DW series DW _ bc _ 2;

FIG. 3 is a block diagram of a bc _2 cell with an active low enable signal D flip-flop;

FIG. 4 is a block diagram of a bc _2 cell with a 4-input multiplexer;

FIG. 5 is a diagram of the optimized bc _2 unit structure in the present invention;

FIG. 6 is a diagram of the construction of the units of the Synopsys DW series DW _ bc _ 7;

FIG. 7 is a simplified bc _7 unit structure diagram;

FIG. 8 is a flow chart of output function simulation data in the present invention;

FIG. 9 is a flow diagram of input function simulation data in the present invention;

FIG. 10 is a diagram of the optimized bc _7 unit structure in the present invention;

FIG. 11 is a circuit diagram of a boundary scan chain based on a single bc _2 cell;

FIG. 12 is a circuit diagram of a boundary scan chain based on the merging of bc _2 and bc _7 cells;

FIG. 13 is a circuit diagram of a boundary scan chain optimized in the present invention.

Detailed description of the preferred embodimentsthe following description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, is intended to illustrate and explain the present invention and not to limit the same.

As shown in FIG. 2, two multiplexers are added to a Synopsys DW series BC unit DW _ BC _2, and capture _ en and update _ en signals are used as respective selection ends and respectively used as D-end inputs of a capture flip-flop and an update flip-flop.

On the basis, a multiplexer under the control of capture _ en and a capture flip-flop under the control of capture _ clk are combined to form a D flip-flop with an active low-level enable signal, and two-input multiplexers under the control of capture _ en and shift _ dr can also be combined into a four-input multiplexer. The above deformation process is shown in fig. 3 and fig. 4, respectively, and these two unit structures are two boundary scan bc _2 unit structures appearing in the current DW series.

Therefore, the multiplexers and the flip-flops can be combined to the maximum extent based on the original DW _ bc _2 unit, namely, the multiplexers under the control of capture _ en and update _ en are respectively combined with the flip-flops under the control of capture _ clk and update _ clk, and the optimized circuit is as shown in FIG. 5.

To enable bi-directional interaction between external Pins (PAD) and internal logic, another Synopsys DW series BC element DW _ BC _7 is introduced here, as shown in FIG. 6.

For the purpose of simplifying the data path, the multiplexer under the control of mode2 can be omitted, and the cell structure is the boundary scan bc _7 cell appearing in the current DW series, as shown in fig. 7.

In the simulation mode, the flow of simulation data of the output function and the input function is as shown in fig. 8 and 9, and the intermediate redundant logic is omitted in the external pin and the internal logic data interaction path; the simulation mode realizes the control and observation of bidirectional data flow in the same boundary scan register unit according to the data path in the graph, and the optimized bc _7 unit circuit is shown in fig. 10.

The two boundary scan chain circuit structure designs used in the present stage are based on a single bc _2 unit and the combination of bc _2 and bc _7 units, respectively. The former circuit configuration is shown in fig. 11. After the simulation mode is started, test data are serially shifted into a scan chain through bc _2 units of each stage in sequence under the control of a shift _ dr signal and a capture _ en signal, and captured test data are output from a data output port under the enabling of an update _ en signal and a mode signal. When the data output port is respectively connected with the OEN and the I end of the PAD, the output function simulation can be completed under the condition that the OEN value is 0; under the condition that the value of the OEN end is 1, the PAD port is assigned, the value of the C port of the PAD is located at the D input end of the capture register, and then under the control of a capture _ en signal and a shift _ dr signal, data in a capture state are serially shifted out of a scan chain through ScanIn and ScanOut ports of each stage of bc _2 units, so that the data at the output end of the PAD are observed, and the input function simulation can be completed.

In another circuit structure of the scan chain as shown in fig. 12, after the test data is shifted, the updated output data in the bc _2 unit controls the value of the OEN port corresponding to the PAD, thereby determining the simulation of the input or output function of the PAD. And the bc _7 unit of the later stage can simultaneously realize bidirectional access of the PAD port data and the internal logic data.

According to the BC unit optimization analysis before, the multiplexer selection signal of the BC _7 unit controlled by the OEN port of the PAD can be ignored, so that the boundary scan chain circuit after the final optimization is shown in FIG. 13 by combining the optimized BC _2 and BC _7 units.

In the technical scheme, in the process from a complex circuit structure to an optimized circuit, the gate circuits with optimal performance are combined as far as possible according to the performance parameters of the gate circuits; in addition, in the optimization process aiming at the bc _7 unit, a method of independent function data flow analysis is adopted, functions to be realized by a single circuit are separated one by one, a data flow path of each function is analyzed, and various independent data flows are finally combined, so that redundant signals or circuit structures in the original circuit structure are abandoned.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A register unit design method based on boundary scan is characterized in that on the basis of a traditional boundary scan register unit structure, capture _ en and update _ en signals are added to serve as enabling ends of a capture trigger and an update trigger;

after the simulation mode is started, test data are serially shifted into a scan chain through bc _2 units of each stage under the control of a shift _ dr signal and a capture _ en signal, and the captured test data are output from a data output port under the enabling of an update _ en signal and a mode signal; when the data output port is respectively connected with the OEN and the I end of the PAD, the output function simulation can be completed under the condition that the OEN value is 0;

2. The method for designing the register unit based on the boundary scan as recited in claim 1, wherein the bi-directional test function of the bc _2 unit on the PAD is utilized to analyze the data flow direction of the input and output simulation processes in the test mode, and then the data flow direction and the input and output simulation processes are fused to form a bc _7 unit;

after the test data is shifted, the updated output data in the bc _2 unit is used for controlling the OEN port value of the corresponding PAD, so that the simulation of the input or output function of the PAD is determined, and the bc _7 unit at the later stage simultaneously realizes the bidirectional access of the PAD port data and the internal logic data, so that the corresponding simulation is performed according to the OEN value.