CN113691261B - Delta-sigma modulator device and delta-sigma modulation method - Google Patents

Abstract

The delta-sigma modulator device includes a sampling circuit, a digital-to-analog converter circuit, an integrator circuit, and an analog-to-digital converter circuit. The sampling circuit is used to sample an input signal to generate a first signal. The digital-to-analog converter circuit is used to convert the first digital signal into a combination of a first reference voltage and a common-mode voltage to generate a second signal, wherein the first reference voltage is one of a positive reference voltage and a negative reference voltage. The integrator circuit is used to perform an integration operation according to the first signal and the second signal to generate a third signal. The analog-to-digital converter circuit is used to quantize the third signal into an output signal, and generate a first digital signal according to the output signal.

Description

Delta-sigma modulator device and delta-sigma modulation method

Technical Field

The present invention relates to a delta-sigma modulator, and more particularly to a delta-sigma modulator and a method thereof for reducing redundant current of a digital-to-analog converter circuit and an integrator circuit.

Background technique

In conventional delta-sigma modulators, a digital-to-analog converter circuit sets multiple reference voltages according to the digital signal generated by the quantizer to generate corresponding analog voltages. However, in most cases, the redundant reference voltages used in the conversion process will cause unnecessary load current, thereby increasing the overall system power consumption.

Summary of the invention

In some embodiments, the delta-sigma modulator device includes a sampling circuit, a digital-to-analog converter circuit, an integrator circuit, and an analog-to-digital converter circuit. The sampling circuit is used to sample an input signal to generate a first signal. The digital-to-analog converter circuit is used to convert the first digital signal into a combination of a first reference voltage and a common-mode voltage to generate a second signal, wherein the first reference voltage is one of a positive reference voltage and a negative reference voltage. The integrator circuit is used to perform an integration operation based on the first signal and the second signal to generate a third signal. The analog-to-digital converter circuit is used to quantize the third signal into an output signal and generate the first digital signal based on the output signal.

In some embodiments, the delta-sigma modulation method includes the following operations: sampling an input signal to generate a first signal; converting the first digital signal into a combination of a first reference voltage and a common-mode voltage to generate a second signal, wherein the first reference voltage is one of a positive reference voltage and a negative reference voltage; performing an integration operation based on the first signal and the second signal to generate a third signal; and quantizing the third signal into an output signal, and generating the first digital signal based on the output signal.

The features, operations and effects of the present invention are described in detail below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram showing a delta-sigma modulator device according to some embodiments of the present application;

FIG. 2 is a schematic diagram showing the operation of the mapping circuit of FIG. 1 according to some embodiments of the present application; and

FIG. 3 is a flow chart showing a delta-sigma modulation method according to some embodiments of the present invention.

Symbol Description:

100: Delta-sigma modulator device

110: Sampling circuit

111: Switching Circuit

120: Digital to Analog Converter Circuit

121: Switching Circuit

121A: Multiplexer Circuit

130: Integrator Circuit

132: Amplifier Circuit

140: Analog-to-digital converter circuit

142: Quantizer Circuit

144: Encoder circuit

146: Mapping Circuit

B0～B2、D0～D6：bit

C: Capacitance

CINT: Integral capacitor

CK1, CK2: frequency signal

CS: sampling capacitor

N1: Node

S1～S3：Signal

SD1, SD2: digital signal

SIN: Input signal

SO: Output signal

SR: Reset switch

SW1～SW5：Switch

VCM: Common mode voltage

VREFP: Positive reference voltage

VREFN: Negative reference voltage

+7,+5,+3,+1,-1,-3,-5,-7: quantization level

0~7: signal value

300: Delta-sigma modulation method

S310, S320, S330, S340: Operation

Detailed ways

All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries and the use examples of any of the words discussed herein in the content of the present application are only illustrative and should not be used to limit the scope and meaning of the present application. Similarly, the present application is not limited to the various embodiments shown in this specification.

As used herein, "coupled" or "connected" may refer to two or more components making physical or electrical contact directly with each other, or making physical or electrical contact indirectly with each other, or may refer to two or more components operating or acting on each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit, and the term "circuit" may be a device composed of at least one transistor and/or at least one active and passive component connected in a certain manner to process signals.

As used herein, the term "and/or" includes any combination of one or more of the listed associated items. In this article, the words first, second, and third are used to describe and distinguish each component. Therefore, the first component in this article can also be called the second component without departing from the original intention of the present application. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

FIG. 1 is a schematic diagram of a sigma delta modulator device 100 according to some embodiments of the present invention. The sigma delta modulator device 100 can generate an output signal SO according to an input signal SIN. In some embodiments, the sigma delta modulator device 100 includes a sampling circuit 110, a digital to analog converter (DAC) circuit 120, an integrator circuit 130, and an analog to digital converter (ADC) circuit 140.

The sampling circuit 110 samples the input signal SIN to generate a signal S1. For example, the sampling circuit 110 includes a plurality of switching circuits 111 and a reset switch SR. The reset switch SR is coupled between the node N1 and a node for receiving the common mode voltage VCM. Each switching circuit 111 includes a switch SW1, a switch SW2, and a sampling capacitor CS. The first end of the sampling capacitor CS is coupled to the switch SW1 and the switch SW2, and the second end of the sampling capacitor CS is coupled to the node N1. In the sampling phase, the switch SW1 and the reset switch SR are turned on according to the clock signal CK1, and the switch SW2 is not turned on according to the clock signal CK2. In this way, the voltage difference between the input signal SIN and the common mode voltage VCM can be stored in the sampling capacitor CS. In the integration phase, the switch SW2 is turned on according to the clock signal CK2, and the switch SW1 and the reset switch SR are not turned on according to the clock signal CK1. In this way, the sampling capacitor CS can convert the stored voltage difference into a signal S1.

The DAC circuit 120 converts the digital signal SD1 into a signal S2. In some embodiments, the DAC circuit 120 converts the digital signal SD1 into a combination of a first reference voltage and a common mode voltage VCM to generate the signal S2, wherein the first reference voltage is one of a positive reference voltage VREFP and a negative reference voltage VREFN. In some embodiments, the common mode voltage VCM is an AC ground voltage. In some embodiments, the common mode voltage VCM may be an average voltage of the positive reference voltage VREFP and the negative reference voltage VREFN. In some embodiments, the positive reference voltage VREFP may be expressed as VCM+VREF, and the negative reference voltage may be expressed as VCM-VREF, wherein VREF is a reference signal swing.

In this example, the DAC circuit 120 includes a plurality of switching circuits 121. Each of the plurality of switching circuits 121 includes a capacitor C, a switch SW3, a switch SW4, and a multiplexer circuit 121A. In some embodiments, the capacitor C and the sampling capacitor CS can be set to have the same capacitance. In some embodiments, the number of switching circuits 121 is the same as the number of switching circuits 111. The first end of the switch SW3 receives the common mode voltage VCM, and the second end of the switch SW3 is coupled to the first end of the capacitor C. The second end of the capacitor C is coupled to the node N1. The switch SW3 is turned on according to the clock signal CK1 to transmit the common mode voltage VCM to the capacitor C. In other words, in the sampling stage, the potential of the first end of the capacitor C and the potential of the second end of the capacitor C (i.e., the node N1) are reset to the common mode voltage VCM via the switch SW3 and the reset switch SR, respectively.

The first end of the switch SW4 is coupled to the multiplexer circuit 121A to receive the positive reference voltage VREFP, the negative reference voltage VREFN or the common mode voltage VCM from the multiplexer circuit 121A. The second end of the switch SW4 is coupled to the first end of the capacitor C. In the integration phase, the switch SW4 is turned on according to the clock signal CK2 to transmit the positive reference voltage VREFP, the negative reference voltage VREFN or the common mode voltage VCM from the corresponding multiplexer circuit 121A to the capacitor C. In this way, during the integration phase, the plurality of capacitors C can generate a signal S2 to the node N1 according to the received voltage. In the integration phase, if the capacitor C receives the common mode voltage VCM, the potentials at both ends of the capacitor C are equal, so the capacitor C will not perform charge transfer (i.e., the capacitor C does not generate dynamic current). On the contrary, if the capacitor C receives the first reference voltage (positive reference voltage VREFP or negative reference voltage VREFN), the capacitor C will perform charge reset (charge redistribution) to generate a corresponding signal S2 to the integration capacitor CINT described later.

Each of the multiplexer circuits 121A receives a corresponding bit of the digital signal SD1. For example, the digital signal SD1 includes 7 bits D0 to D6. The first multiplexer circuit 121A receives the first bit D0. The second multiplexer circuit 121A receives the second bit D1. Similarly, the seventh multiplexer circuit 121A receives the seventh bit D6. The multiplexer circuit 121A can transmit the positive reference voltage VREFP, the negative reference voltage VREFN or the common mode voltage VCM to the switch SW4 according to the corresponding bit in the digital signal SD1. The digital-to-analog conversion operation of the DAC circuit 120 will be described later with reference to FIG. 2.

The integrator circuit 130 is used to perform an integration operation according to the signal S1 and the signal S2 to generate a signal S3. For example, the integrator circuit 130 includes a switch SW5, an integration capacitor CINT and an amplifier circuit 132. The first end of the switch SW5 is coupled between the node N1 and the first input end (e.g., the negative input end) of the amplifier circuit 132. The second input end (e.g., the positive input end) of the amplifier circuit 132 receives the common mode voltage VCM. The integration capacitor CINT is coupled between the first input end and the output end of the amplifier circuit 132. In the integration stage, the switch SW5 is turned on according to the clock signal CK2, and the switch SW1 is not turned on according to the clock signal CK1. Under this condition, the signals stored in the multiple capacitors C coupled to the node N1 and the multiple sampling capacitors CS can be transmitted to the first input end of the amplifier circuit 132 and the integration capacitor CINT. As described above, the signal S1 corresponds to the voltage difference (SIN-VCM) sampled by the sampling capacitor CS, and the signal S2 is generated by the plurality of capacitors C according to the digital signal SD1 and in response to the received first reference voltage or common mode voltage VCM. Thus, in the integration phase, the charge corresponding to the difference between the signal S2 and the signal SIN is transferred from the sampling circuit 110 and the DAC circuit 120 to the integration capacitor CINT. The difference between the signal S2 and the signal SIN can be integrated by the amplifier circuit 132 in cooperation with the integration capacitor CINT to obtain the signal S3.

The ADC circuit 140 is used to quantize the signal S3 into an output signal SO, and generate a signal SD1 according to the output signal SO. For example, the ADC circuit 140 includes a quantizer circuit 142, an encoder circuit 144, and a mapping circuit 146. The quantizer circuit 142 quantizes the signal S3 into the output signal SO. In some embodiments, the quantizer circuit 142 may be (but not limited to) a comparator circuit. The encoder circuit 144 is used to encode the output signal SO into a digital signal SD2. For example, the output signal SO includes 3 bits B0-B2, which are binary codes. The encoder circuit 144 may encode the output signal SO into a digital signal SD2 having 7 bits, wherein the bits are thermometer codes. The mapping circuit 146 maps the digital signal SD2 into a digital signal SD1. In some embodiments, the mapping circuit 146 may include a lookup table storing a corresponding relationship as described in FIG. 2 below, so as to output a digital signal SD1 according to the digital signal SD2.

FIG. 2 is a schematic diagram showing the operation of the mapping circuit 146 of FIG. 1 according to some embodiments of the present invention. For ease of understanding, the operation of the DAC circuit 120 of FIG. 1 will be described together here. In this example, the output signal SO is set to 3 bits, and the digital signal SD2 encoded by the output signal SO is set to 7 bits. As shown in FIG. 2, the quantizer circuit 142 can quantize the output signal SO into multiple quantization levels such as +7, +5, +3, ..., -3, -5, -7, where each quantization level corresponds to 1 signal value. For example, the quantization levels +7, +5, +3, ..., -3, -5, -7 correspond to signal values 7, 6, 5, 4, ..., 1, 0, respectively. The signal value can be represented by the 3 bits B0-B2 of the output signal SO. For example, if multiple bits B0-B2 are "010", the output signal SO corresponds to a signal value of 2. Alternatively, if multiple bits B0-B2 are "101", the output signal SO corresponds to a signal value of 5.

In this example, the analog voltage represented by each unit quantization level D is the sum of the common mode voltage VCM and D/7 times the reference signal swing VREF (which can be expressed as VCM+D×VREF/7), and the common mode voltage VCM is 0 volt in this example. For example, if the plurality of bits B0-B2 are "010", the quantization level corresponding to the output signal SO is -3, and it represents that the analog voltage corresponding to the output signal SO is -3/7 times the reference signal swing VREF. Under this condition, the DAC circuit 120 outputs a signal S2 that is the same as the three negative reference voltages VREFN. Equivalently, the output signal SO is converted into a corresponding analog voltage (i.e., signal S2) via the DAC circuit 120. In some related technologies, the DAC circuit is configured to convert a digital signal into a combination of a positive reference voltage VREFP and a negative reference voltage VREFN. For example, in these technologies, if the three bits of the digital signal are "010", two capacitors (e.g., capacitors C) in the DAC circuit will receive the positive reference voltage VREFP, and five capacitors will receive the negative reference voltage VREFN. In this way, by combining two positive reference voltages VREFP and five negative reference voltages VREFN, the DAC circuit can generate an analog voltage equivalent to three negative reference voltages VREFN to express the aforementioned -3/7 times reference signal swing VREF. As previously mentioned, if capacitor C receives a positive reference voltage VREFP or a negative reference voltage VREFN, capacitor C will transfer charge and generate dynamic current consumption. In addition, in these technologies, since all capacitors C will have potential changes, the equivalent capacitance value of node N1 will increase, causing the feedback factor and bandwidth of the integrator circuit to decrease. In order to compensate for the speed of the integrator circuit, the driving current of the integrator circuit needs to be increased. As a result, the power of the delta-sigma modulator will be significantly increased.

Compared to the above-mentioned related art, in this example, if the plurality of bits B0-B2 are "010", the mapping circuit 146 can generate a corresponding digital signal SD1 according to the relationship between the quantization level corresponding to the output signal SO, the first reference voltage and the common mode voltage VCM. In response to the digital signal SD1, three capacitors C receive the negative reference voltage VREFN and the remaining capacitors C receive the common mode voltage VCM to generate a signal S2 corresponding to the three negative reference voltages VREFN. In other words, the mapping circuit 146 can generate a digital signal SD1 according to the quantization level corresponding to the output signal SO, so that the corresponding number of capacitors C receive the first reference voltage (positive reference voltage VREFP or negative reference voltage VREFN), and the remaining capacitors C receive the common mode voltage VCM. For example, if the quantization level corresponding to the output signal SO is -5, five capacitors C receive the negative reference voltage VREFN, and the remaining capacitors C receive the common mode voltage VCM. If the quantization level corresponding to the output signal SO is +3, three capacitors C receive the positive reference voltage VREFP, and the remaining capacitors C receive the common mode voltage VCM. The above correspondence relationship may be pre-set as a lookup table (not shown), and the mapping circuit 146 may search the lookup table according to the digital signal SD2 to generate a corresponding plurality of bits D0 - D6 (ie, the digital signal SD1 ).

As previously mentioned, during the integration phase, if the capacitor C receives the common-mode voltage VCM, the capacitor C will not perform charge transfer. In other words, through the above mapping relationship, the number of capacitors C that cause dynamic current consumption can be reduced during the overall conversion process. Furthermore, since some of the capacitors C will not produce potential changes, the equivalent capacitance value on the node N1 can be reduced. Under this condition, the feedback coefficient of the integrator circuit 130 can be improved, so the driving current of the integrator circuit 130 can be reduced. In this way, compared with the aforementioned related technology, the overall power consumption of the delta-sigma modulator device 100 can be reduced.

In most cases, part of the capacitor C receives the first reference voltage (i.e., the positive reference voltage VREFP or the negative reference voltage VREFN), and the remaining part of the capacitor C receives the common mode voltage VCM to reduce current consumption. In some extreme cases, if the output signal SO corresponds to the highest quantization level (e.g., +7) or the lowest quantization level (e.g., -7), all of the capacitor C will receive the positive reference voltage VREFP or the negative reference voltage VREFN. The number of components or the number of bits mentioned in FIG. 1 and/or FIG. 2 are for example only, and the present invention is not limited thereto.

FIG. 3 is a flow chart showing a delta-sigma modulation method 300 according to some embodiments of the present invention. In operation S310, the input signal SIN is sampled to generate a signal S1. In operation S320, the digital signal SD1 is converted into a combination of a first reference voltage and a common mode voltage VCM to generate a signal S2, wherein the first reference voltage is one of a positive reference voltage VREFP and a negative reference voltage VREFN. In operation S330, an integration operation is performed according to the signal S1 and the signal S2 to generate a signal S3. In operation S340, the quantized signal S3 is an output signal SO, and a digital signal SD1 is generated according to the output signal SO.

The description of the multiple operations of the above-mentioned delta-sigma modulation method 300 can refer to the above-mentioned multiple embodiments, so it will not be repeated here. The above-mentioned multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, the various operations under the delta-sigma modulation method 300 can be appropriately added, replaced, omitted or performed in a different order. Alternatively, one or more operations under the delta-sigma modulation method 300 can be performed simultaneously or partially simultaneously.

In summary, the sigma-delta modulator device and sigma-delta modulation method in some embodiments of the present invention can control the DAC circuit to receive the common mode voltage according to the quantization level corresponding to the output signal to perform digital-to-analog conversion, thereby reducing the overall system power consumption.

Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person skilled in the art may make changes to the technical features of the present invention according to the explicit or implicit contents of the present invention, but all such changes may fall within the scope of protection of the present invention. In other words, the scope of protection of the present invention shall be subject to the scope defined in the claims of the present invention application.

Claims (10)

1. A delta-sigma modulator device, characterized in that the delta-sigma modulator device comprises: A sampling circuit, used for sampling an input signal to generate a first signal; a digital-to-analog converter circuit for converting a first digital signal into a combination of a first reference voltage and a common-mode voltage using a plurality of capacitors to generate a second signal, wherein the first reference voltage is one of a positive reference voltage and a negative reference voltage, and a plurality of terminals of each of the plurality of capacitors are configured to receive the common-mode voltage during a period in which the sampling circuit samples the input signal; an integrator circuit, configured to perform an integration operation according to the first signal and the second signal to generate a third signal; and The analog-to-digital converter circuit is used to quantize the third signal into an output signal and generate the first digital signal according to the output signal. 2. The delta-sigma modulator device of claim 1 , wherein the digital-to-analog converter circuit comprises the plurality of capacitors, and each of the plurality of capacitors is configured to receive the first reference voltage or the common-mode voltage according to a corresponding bit in the first digital signal to generate the second signal. 3. The delta-sigma modulator device of claim 1 , wherein the digital-to-analog converter circuit comprises a plurality of switching circuits, and each of the plurality of switching circuits comprises: a corresponding capacitance among the plurality of capacitances; A first switch, configured to be turned on according to a first frequency signal to transmit the common mode voltage to the corresponding capacitor; a second switch, configured to be turned on according to a second frequency signal to transmit the first reference voltage or the common mode voltage to the corresponding capacitor to generate the second signal; and The multiplexer circuit is used for transmitting the first reference voltage or the common mode voltage to the second switch according to the corresponding bit in the first digital signal. 4. The delta-sigma modulator device of claim 1 , wherein the analog-to-digital converter circuit comprises: a quantizer circuit, configured to quantize the third signal into the output signal; an encoder circuit, configured to encode the output signal into a second digital signal; and A mapping circuit is used to map the second digital signal into the first digital signal. 5 . The sigma-delta modulator device as claimed in claim 4 , wherein the output signal is a binary code, and the second digital signal is a thermometer code. 6 . The delta-sigma modulator device of claim 4 , wherein the mapping circuit is used for mapping the second digital signal into the first digital signal according to a relationship between a quantization level corresponding to the output signal, the first reference voltage and the common mode voltage. 7 . The sigma-delta modulator device as claimed in claim 1 , wherein the common mode voltage is an average voltage of the positive reference voltage and the negative reference voltage. 8. A delta-sigma modulation method, characterized in that the delta-sigma modulation method comprises: sampling an input signal to generate a first signal; Converting the first digital signal into a combination of a first reference voltage and a common mode voltage using a plurality of capacitors to generate a second signal, wherein the first reference voltage is one of a positive reference voltage and a negative reference voltage, and a plurality of terminals of each of the plurality of capacitors are used to receive the common mode voltage when sampling the input signal; performing an integration operation on the first signal and the second signal to generate a third signal; and The third signal is quantized into an output signal, and the first digital signal is generated according to the output signal. 9. The delta-sigma modulation method of claim 8, wherein using the plurality of capacitors to convert the first digital signal into the combination of the first reference voltage and the common mode voltage to generate the second signal comprises: The first reference voltage or the common mode voltage is transmitted to a corresponding capacitor among the plurality of capacitors according to a corresponding bit in the first digital signal to generate the second signal. 10. The delta-sigma modulation method of claim 8, wherein quantizing the third signal into the output signal and generating the first digital signal according to the output signal comprises: quantizing the third signal into the output signal; encoding the output signal into a second digital signal; and The second digital signal is mapped to the first digital signal.