JP2010245765A - Dem (dynamic element matching) - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide DEM which can implement an accurate ΔΣ type AD type converter. <P>SOLUTION: Algorithm of the DEM used for a ΔΣ modulator shifts, by a predetermined number A, an element that comes into use in a DA converter regardless of the output values of a quantizer constituting the ΔΣ modulator and the DA converter. A is 1 or a positive integer satisfying äA<2<SP>N</SP>/4} with respect to the number N of bits of the DA converter (N is an integer ≥3). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a DEM used for a DA converter, and more particularly to a ΔΣ modulator used for a ΔΣ AD converter.

  Various types of AD converters such as a successive approximation type and an oversample type have been developed. In general, when an analog input signal is converted into a digital signal by an AD converter, the S / N (Signal to Noise Ratio) characteristics near the signal frequency can be improved by increasing the sampling frequency. The oversampling AD converter is a method in which the S / N characteristic is improved by increasing the oversampling ratio (ratio of the Nyquist frequency (1/2 of the sampling frequency) to the frequency of the signal band).

  One of the oversampled AD converters is a ΔΣ AD converter. This ΔΣ AD converter is composed of a ΔΣ modulator and a decimation filter, and the performance of the ΔΣ modulator directly affects the performance of the ΔΣ AD converter.

  The ΔΣ modulator integrates the difference between the output signal and the input signal with an integrator, and performs feedback control so that the output of the integrator is minimized. The characteristic of the ΔΣ modulator is a noise shaping characteristic. By increasing the order of the integrator, the S / N characteristic of the desired band can be further improved, and the accuracy of the ΔΣ AD converter can be improved.

  In recent years, the number of bits of the quantizer has been increased in order to realize a broadband and high-accuracy ΔΣ modulator, but if the number of bits of the quantizer is increased, the bit of the DA converter provided on the feedback path is increased. You must also increase the number. When the number of bits of the DA converter increases, a conversion error occurs due to manufacturing variations of unit elements such as a current source, a capacitive element, and a resistance element that constitute the DA converter, which is fed back to the input as it is and the accuracy of the ΔΣ modulator is increased. There is a problem of lowering.

  DEM (Dynamic Element Matching) is known as a technique for correcting a conversion error due to manufacturing variations of unit elements such as a current source, a capacitive element, and a resistance element constituting the DA converter. DEM is a technique that averages and uses the unit elements of the DA converter by shifting the output signal of the quantizer to ensure the accuracy of the DA converter.

  As prior art document information related to the invention of the present application, for example, Patent Document 1 is known.

JP 2005-26998

However, according to a study by the present researchers, in a ΔΣ modulator using a DEM of a general DWA (Data Weighted Averaging) algorithm, a DA converter of an NRZ (Non Return Zero) method is used. As a result, it has been found that there is a problem that noise called glitch occurs and the accuracy deteriorates on the contrary to improving the accuracy of the DA converter due to manufacturing variations. The DWA algorithm and glitch will be described in detail later.
An object of the present invention is to realize a highly accurate ΔΣ modulator even when an NRZ method and a DEM are used in a DA converter in a feedback path.

In order to achieve this object, in the ΔΣ modulator of the present invention, the DEM algorithm is shifted by a predetermined number A, regardless of the output values of the quantizer and DA converter. A is 1 or a positive integer satisfying {A <2 ^N / 4} with respect to the number of bits N of the DA converter (N is a positive integer of 3 or more).

  By using the A element shift algorithm, it is possible to secure the accuracy of the DA converter while suppressing glitches, and as a result, it is possible to realize high accuracy as a ΔΣ modulator.

ΔΣ modulator block diagram ΔΣ modulator block diagram Circuit diagram showing change in state of DA converter when DEM is not used Circuit diagram showing state change of DA converter when DEM using DWA algorithm is used The circuit diagram showing the state change of a DA converter at the time of using DEM using the 1 element shift algorithm of this invention Result of FFT analysis of ΔΣ modulator output when assuming that ΔΣ modulator without DEM has ideal characteristics In a delta-sigma modulator without a DEM, the result of FFT analysis of the delta-sigma modulator output when the unit elements (current source, capacitive element, resistance element, etc.) that make up the DA converter have manufacturing variations In a ΔΣ modulator with DWA algorithm controlled DEM, the ΔΣ modulation is based on the assumption that unit elements (current sources, capacitive elements, resistance elements, etc.) that make up the DA converter have manufacturing variations and no glitches occur. Of the FFT analysis of the instrument output In a delta-sigma modulator provided with a DWA controlled by a DWA algorithm, the output of the delta-sigma modulator when the unit elements (current source, capacitive element, resistive element, etc.) constituting the DA converter have manufacturing variability and further glitches occur Results of FFT analysis In a ΔΣ modulator provided with a DEM controlled by a one-element shift algorithm according to the present invention, the unit elements (current source, capacitive element, resistance element, etc.) constituting the DA converter have manufacturing variations, and further a glitch occurs. Results of FFT analysis of ΔΣ modulator output In the delta-sigma modulator provided with the DEM controlled by the two-element shift algorithm according to the present invention, the unit elements (current source, capacitive element, resistance element, etc.) constituting the DA converter have manufacturing variations, and further a glitch occurs. Results of FFT analysis of ΔΣ modulator output In the delta-sigma modulator provided with the DEM controlled by the three-element shift algorithm of the present invention, the unit elements (current source, capacitive element, resistive element, etc.) constituting the DA converter have manufacturing variations, and further a glitch occurs. Results of FFT analysis of ΔΣ modulator output In the delta-sigma modulator provided with the DEM controlled by the 4-element shift algorithm of the present invention, the unit elements (current source, capacitive element, resistive element, etc.) constituting the DA converter have manufacturing variations, and further when glitch occurs Results of FFT analysis of ΔΣ modulator output

(Embodiment 1)
Hereinafter, the ΔΣ modulator according to the first embodiment will be described.
A delta-sigma modulator 100 shown in FIG. 1 includes an adder circuit 101 that takes a difference between an analog input signal Va and a feedback signal Vb, an integrator 102 that integrates the output of the adder circuit, and an output of the integrator 102 that is quantized. It comprises a quantizer 103 that performs (digital signal conversion) and a DA converter 104 that DA-converts the output of the quantizer 103 and supplies it to the adder circuit 101.
The quantizer 103 compares the output voltage of the integrator 102 with a reference voltage of 2 N (N is a resolution of the quantizer 103 and an integer of 2 or more), and a voltage comparison circuit (not shown). And a latch circuit (not shown) for latching 2 N signals obtained from the voltage comparison circuit. Then, the output signal of the voltage comparison circuit latched in the latch circuit becomes the output signal of the ΔΣ modulator 100.

The ΔΣ modulator 200 shown in FIG. 2 is obtained by adding a DEM circuit 205 between the quantizer 103 and the DA converter 104 of the ΔΣ modulator 100 shown in FIG.
The DEM circuit 205 shown in FIG. 2 shows the manufacturing variation of unit elements (current source, capacitive element, resistance element, etc.) included in the DA converter 204 as elements (for example, R0, R1, R2,... , R7 corresponds to each element), and is used by averaging.

  Next, three operation comparisons are made when the DEM is not used, when the DEM using the most common algorithm DWA is used, and when the DEM using the A element shift algorithm of the present invention is used. As an example, a 3-bit DA converter using a resistance element will be described. Here, a description will be given using a one-element shift algorithm (A = 1) as an example of the A-element shift algorithm.

The case where the output of the quantizer changes from (00000011) → (000011111) → (00011111) will be described as an example.
When the DEM is not used (see FIG. 1), the input signal to the DA converter 104 changes from (00000011) → (000011111) → (00011111) as the output of the quantizer 103. Therefore, among the elements of the DA converter 104 (corresponding to R0, R1, R2,..., R7 in FIG. 3a), the elements to be used change as shown in FIG. 3a. As can be inferred from FIG. 3a, the frequency of use of R0 is the highest, and the frequency of use of R7 is the lowest. Therefore, when the manufacturing variation of the resistance value of R0 is large, the DA converter 104 The accuracy is greatly degraded. In a semiconductor process, since there is about 20% variation in the resistance value, it is difficult to realize a DA converter 104 with high accuracy.

  On the other hand, when the DEM using the conventional DWA algorithm is used, the input signal to the DA converter 204 changes from (00000011) → (00111100) → (11000111). For this reason, the used elements of the DA converter 204 change as shown in FIG. 3b.

  As shown in FIG. 3b, by using the DWA algorithm, each element of the DA converter 204 is averaged and used with the same probability. As a result, as in the case of the ΔΣ modulator 100 without DEM shown in FIG. 3A, the problem that the element used in the DA converter 104 is biased to R0 can be overcome.

  However, it has been found that when the NRZ DA converter 204 using the DWA algorithm is newly used, a glitch appearing at the output of the DA converter 204 becomes large. The glitch is noise generated when the output of the DA converter 204 is switched.

  The cause of the occurrence will be described with reference to FIG. In FIG. 3b, when the input signal to the DA converter 204 changes from (00000011) to (00111100), the elements used by the DA converter 204 are changed from R0, R1 to R2, R3, R4 and R5 will change to the selected state. In a period in which the selection elements are switched, there may be a case where a state in which R2, R3, R4, and R5 are selected occurs before R0 and R1 are connected to the ground. In this case, a state in which R0, R1, R2, R3, R4, and R5 are temporarily selected occurs, and a large glitch occurs in the output value of the DA converter 204.

  Furthermore, the greater the number of switching elements of the DA converter 204 (the number of switching elements in FIG. 3b), the greater the generated glitch. As a countermeasure against this, the one-element shift algorithm invented this time can reduce the number of switches in FIG. 3b and suppress the occurrence of a large glitch compared to the DWA algorithm, thereby suppressing an error in the output value of the DA converter 204. be able to.

  Next, a case where the DEM 205 using the one-element shift algorithm in Embodiment 1 of the present invention is used will be described with reference to FIG.

  When the output of the quantizer 203 in FIG. 2 (input to the DEM 205 using the one-element shift algorithm) changes from (00000011) → (000011111) → (00011111), the output of the DEM 205 (to the DA converter 204) (Input) changes from (00000011) → (00011110) → (01111100). In this case, the used elements of the DA converter 204 change as shown in FIG. In other words, as can be seen from FIG. 3c, when the output of the quantizer 203 is (00000011), the minimum bit is R0, and when the output of the quantizer 203 is (00011110), the minimum bit is R1. In other words, when the output of the quantizer 203 is (01111100), R2 is responsible for the minimum bit, and every time the output value of the quantizer 203 changes, the element of the DA converter 204 that bears the minimum bit is 1. Shift one by one. “Shifting a predetermined number A of elements to be used in the DA converter” in the claims refers to the state as described above.

  If such a one-element shift algorithm is used, it is possible to suppress the generated glitch more than the ΔΣ modulator 200 using the conventional DWA algorithm.

  For example, as shown in FIG. 3c, when the input signal to the DA converter 204 changes from (00000011) to (00011110), the elements used in the DA converter 204 are from the state in which R0 and R1 are selected. R1, R2, R3, and R4 will change to the selected state. If a state in which R2, R3, R4, and R5 are selected before R0 and R1 are connected to the ground in the period during which the selection element is switched, R0, R1, R2, R3, and R4 are temporarily changed. The state that is selected occurs. However, when the DWA algorithm is used, a state in which R0, R1, R2, R3, R4, and R5 are temporarily selected has occurred, so that the glitch can be suppressed by one element.

  Further, for example, when the input to the DEM 205 changes from (00001111) to (11110000), the glitch suppression effect is further increased.

  When the DWA algorithm is used, the input signal to the DA converter 204 changes from (000011111) to (11110000), so the elements used in the DA converter 204 are selected by R0, R1, R2, and R3. From this state, R4, R5, R6, and R7 are changed to a selected state. If a state occurs in which R4, R5, R6, and R7 are selected before R0, R1, R2, and R3 are connected to the ground during the period in which the selection element is switched, R0, R1, R2, A state in which R3, R4, R5, R6, and R7 are selected occurs, and a large glitch occurs.

  On the other hand, if the one-element shift algorithm of the present invention is used, the input signal to the DA converter 204 changes from (000011111) to (00011110), so the elements used in the DA converter 204 are R0, R1. , R2 and R3 are changed to a state where R1, R2, R3 and R4 are selected. If a state in which R1, R2, R3, and R4 are selected before R0, R1, R2, and R3 are connected to the ground in a period during which the selection element is switched, R0, R1, R2, A state occurs in which R3 and R4 are selected. However, the glitch generated at this time is as small as three elements as compared with the case where the DWA algorithm is used, and as a result, a highly accurate ΔΣ modulator 200 can be realized.

  In the above description, when the input to the DEM 205 is (00000011) → (000011111) → (00011111), if the one element shift algorithm is used, it changes as (00000011) → (00011110) → (01111100). Although an example is shown, the order of the used elements and the direction in which the use start element is shifted may be reversed such as (10000001) → (11000011) → (11000111).

  FIG. 4 shows the result of FFT (Fast Fourier Transform) analysis of the ΔΣ modulator output, assuming that the ΔΣ modulator without a DEM has ideal characteristics. The axis represents the amplitude. FIG. 4 shows an example in which the bandwidth of the ΔΣ modulator is designed to be 10 MHz and a signal of about 1 MHz is input, and it can be seen that noise of 10 MHz or less is reduced.

  FIG. 5 shows the result of FFT analysis of the output of the ΔΣ modulator when the unit elements (current source, capacitive element, resistance element, etc.) constituting the DA converter have manufacturing variations in the ΔΣ modulator without a DEM. . It can be seen that the harmonics of the input signal are observed within the 10 MHz band, and the accuracy of the ΔΣ modulator is degraded.

  FIG. 6 assumes that in a delta-sigma modulator provided with a DWA algorithm-controlled DEM, the unit elements (current source, capacitive element, resistive element, etc.) constituting the D / A converter have manufacturing variations, and further no glitch is generated. This is a result of FFT analysis of the output of the ΔΣ modulator in the case. It can be seen that the DWA algorithm controlled DEM improves the accuracy of the ΔΣ modulator.

  FIG. 7 shows a ΔΣ modulator provided with a DWA algorithm-controlled DEM, in which ΔΔ when a unit element (current source, capacitive element, resistance element, etc.) constituting the DA converter has manufacturing variations and a glitch occurs It is the result of carrying out FFT analysis of the modulator output. It can be seen that the accuracy of the ΔΣ modulator is deteriorated as compared with the case where the DEM of FIG. 5 is not provided.

  FIG. 8 shows that in a delta-sigma modulator provided with a DEM controlled by a one-element shift algorithm according to the present invention, the unit elements (current source, capacitive element, resistive element, etc.) constituting the DA converter have manufacturing variations and further glitches are generated. It is the result of FFT analysis of the ΔΣ modulator output when it occurs. Although the noise in the 10 MHz band is larger than that in the ideal state in FIG. 4, it can be seen that the noise is greatly improved in comparison with FIGS. 5 and 7.

  From the above, it can be seen that the ΔΣ modulator of the present invention has better characteristics than the conventional ΔΣ modulator provided with the DEM controlled by the DWA algorithm.

4, 5, 6, 7, 8, 9, and 10, an example in which a 4-bit DA converter is used is shown. There is no limit.
4, FIG. 5, FIG. 6, FIG. 7, and FIG. 8 are simulation results of a ΔΣ modulator provided with a DEM controlled by a one-element shift algorithm.

  On the other hand, FIG. 9 shows a simulation result of a ΔΣ modulator having a D / A converter of 4 bits and a DEM controlled by a 2-element shift algorithm. The result of FFT analysis of the ΔΣ modulator output when there is a manufacturing variation and further glitch occurs), and FIG. 10 is a simulation of a ΔΣ modulator provided with a 4-element DA converter and a DEM controlled by a three-element shift algorithm. The result is the result of FFT analysis of the ΔΣ modulator output when the unit elements (current source, capacitive element, resistance element, etc.) constituting the DA converter have manufacturing variations and further glitches occur. As can be seen from FIG. 9 and FIG. 10, even if the 2-element shift and 3-element shift algorithms are used, the influence of glitches can be reduced.

  Further, FIG. 11 shows a simulation result of a ΔΣ modulator having a 4-bit DA converter and a DEM controlled by a 4-element shift algorithm (unit elements constituting the DA converter (current source, capacitive element, resistive element, etc.). ) Shows the results of FFT analysis of the output of the ΔΣ modulator when there is manufacturing variation and further glitches occur. As can be seen from FIG. 11, when the four-element shift algorithm is used, the effect of glitches suddenly becomes apparent, and the S / N characteristics deteriorate rapidly.

  From the above, when a 4-bit DA converter is used, in order to ensure good characteristics of the ΔΣ modulator, the 1-element, 2-element, 3-element shift algorithm is effective, but the element shift amount is 4 elements. It was found that the S / N characteristic deteriorates when the element shift algorithm for shifting the above (1/4 or more of all elements of the DA converter) is used.

That is, when an N-bit DA converter is used, {A <2 ^{N with} respect to the A element shift algorithm (A is 1 or the number of bits N of the DA converter (N is a positive integer of 3 or more)). Is a positive integer such that / 4}. The reason for {A <2 ^N / 4} is that when the output voltage range of the DA converter is the same, the weight of one element differs depending on the number of bits of the DA converter, so even if the number of switching elements is the same, the bit of the DA converter This is because the generated glitch varies depending on the number.

When N = 1 and N = 2, A <1 and the element shift amount is smaller than 1. Therefore, the element shift amount = 1 having the least influence of glitch is selected. did.
In the embodiment, the DEM of the present invention is used for the ΔΣ modulator, but the present invention can also be implemented using only a DA converter and a DEM.

  If the DEM of the present invention is used, the accuracy of the ΔΣ AD converter can be improved, so that it can be used for various digital devices such as a digital television receiver.

100 conventional ΔΣ modulator 101 adder circuit 102 integrator circuit 103 quantizer circuit 104 DA converter circuit 200 ΔΣ modulator 201 adder circuit 202 integrator 203 quantizer 204 DA converter 205 DEM of the present application

Claims (2)

In DEM used for DA converter,
Regardless of the digital signal input to the D / A converter and the output value of the D / A converter, the DEM has a predetermined number of elements A (A is 1 or a bit of the D / A converter). the number N (N is a positive integer of 3 or more) DEM, characterized in that to positive integer) number shift to be {a <2 N / ^4} respect.   A ΔΣ modulator comprising the DEM according to claim 1.

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