CN113691149A - Common direct current side capacitive multilevel converter topology generation method and system - Google Patents

Common direct current side capacitive multilevel converter topology generation method and system Download PDF

Info

Publication number
CN113691149A
CN113691149A CN202110888135.6A CN202110888135A CN113691149A CN 113691149 A CN113691149 A CN 113691149A CN 202110888135 A CN202110888135 A CN 202110888135A CN 113691149 A CN113691149 A CN 113691149A
Authority
CN
China
Prior art keywords
topology
node
matrix
output
multilevel converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110888135.6A
Other languages
Chinese (zh)
Other versions
CN113691149B (en
Inventor
原露恬
郑琼林
王琛琛
薛尧
杨晓峰
邵天骢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Jiaotong University
Original Assignee
Beijing Jiaotong University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Jiaotong University filed Critical Beijing Jiaotong University
Priority to CN202110888135.6A priority Critical patent/CN113691149B/en
Publication of CN113691149A publication Critical patent/CN113691149A/en
Application granted granted Critical
Publication of CN113691149B publication Critical patent/CN113691149B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Inverter Devices (AREA)
  • Rectifiers (AREA)

Abstract

The invention provides a common direct current side capacitance type multilevel converter topology generation method and a system, wherein the method comprises the following steps: constructing a topological network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topological matrix expression model of the common direct current side capacitive multilevel converter based on the topological network diagram; traversing the topological matrix expression model based on the node connection mode and the matrix constraint condition in the topological network diagram to obtain an output coefficient matrix; and carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain a common direct current side capacitive multilevel converter topological structure. The invention realizes the innovativeness of the method for generating the common direct current side capacitive multilevel converter topology.

Description

Common direct current side capacitive multilevel converter topology generation method and system
Technical Field
The invention relates to the technical field of power electronics, in particular to a common direct current side capacitive multilevel converter topology generation method and system.
Background
The multi-level converter is widely applied to the field of high-power electric energy conversion, wherein the common direct current side capacitance type multi-level converter directly divides a direct current bus by using a capacitor, and a main circuit does not have other suspension capacitors, so that the structure and the control are simple, and the multi-level converter is widely applied to the field of medium voltage. The current proposals for multilevel converters are generally done in several ways: (1) the general topological structure derivation refers to the derivation of a novel multilevel converter topological structure from an existing general topological structure, the method still needs scientific research personnel to carry out derivation according to a certain rule, the basic unit modular combination with certain randomness (2) is provided, different multilevel topologies are obtained through series-parallel connection or other combination modes on the basis of the basic level conversion unit, the method can realize the construction of various topologies, but the method is formed by a plurality of basic structures, the new topology is difficult to realize new breakthrough (3) and is built depending on practical experience, and the topology obtained by the method has randomness, and more novel topologies are difficult to form. The general mathematical topology derivation process is not formed in the multilevel converter topology derivation method, and the generation and derivation mechanisms of the multilevel topology are not complete, so that further research and development are needed for the common direct-current side capacitive type multilevel converter topology derivation generation, the innovativeness of the topology is improved, the working efficiency of scientific researchers is improved, and more novel and practical topologies are provided.
Disclosure of Invention
The embodiment of the invention provides a method and a system for generating a common direct current side capacitive multilevel converter topology, which are used for solving the problem that the generation of the common direct current side capacitive multilevel converter topology is lack of systematicness at present.
In a first aspect, an embodiment of the present invention provides a method for generating a topology of a common-dc-side capacitive multilevel converter, including:
constructing a topological network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topological matrix expression model of the common direct current side capacitive multilevel converter based on the topological network diagram;
traversing the topological matrix expression model based on the node connection mode and the matrix constraint condition in the topological network diagram to obtain an output coefficient matrix;
and carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain a common direct current side capacitive multilevel converter topological structure.
Further, the topological network diagram is a topological network diagram with n layers of nodes corresponding to the common direct current side capacitive multilevel converter which outputs n levels; the layer 1 is a direct current bus capacitor, the layers 2 to n are power device networks, and n is a positive integer greater than 2;
the topological network diagram of the n layers of nodes comprises a dotted line, a solid line, a forward arrow, a reverse arrow, an input node, an output node, an intermediate node and a level path;
the dotted line indicates that the element connecting the two nodes is a diode;
the solid line represents that the element connecting the two nodes is a switching tube without an anti-parallel diode;
the forward arrow represents the indicated direction from the cathode to the anode of the diode;
the reverse arrow indicates the pointing direction from the anode to the cathode of the diode;
the input node represents a node of an input direct current source and is only connected with an output branch;
the output node represents a node on the output AC side and is only connected with an input branch;
the intermediate node represents a node between the power devices and is connected with an input branch and an output branch;
the level path is a path between the input node and the output node.
Further, the principle of maximum pressure bearing uniformity of the power device comprises: common DC side capacitor for outputting n levelThe DC side of the multi-level converter has (n-1) voltage sources, n nodes are arranged between the input DC sources, and each level channel Li(i ═ 1,2, … n) there are (n-1) power devices; wherein the (n-1) power devices comprise (n-i) reverse diodes and (i-1) forward diodes; the reverse diode is a diode with current from an output node to an input node, and the forward diode is a diode with current from the input node to the output node; the diode comprises an independent diode and an anti-parallel diode of the switching tube.
Further, a topology matrix expression model of the common direct current side capacitance type multilevel converter is an (n-1) layer matrix model;
first layer matrix model:
Figure BDA0003194956650000031
second layer matrix model:
Figure BDA0003194956650000032
layer (n-1) matrix model:
Figure BDA0003194956650000033
the topological matrix expression model comprises (n-1) adjacent layer coefficient matrixes and (n-2) spacing layer coefficient matrixes;
wherein, the coefficient matrix of adjacent layers is:
Figure BDA0003194956650000041
Figure BDA0003194956650000042
An-1＝[1 1]；
the spacer coefficient matrix is:
Figure BDA0003194956650000043
Figure BDA0003194956650000044
obtaining an output matrix model based on the topology matrix expression model:
Figure BDA0003194956650000045
wherein, Matrix [ Output ] is an Output coefficient Matrix.
Further, the node connection mode in the topological network diagram meets the following conditions: the power device is subjected to a voltage drop; each node has continuity and bidirectionality in energy flow;
wherein the power device being subject to a voltage drop comprises: the switch tube bears forward voltage, and the diode bears reverse voltage; a bidirectional pressure-bearing power device is arranged between the horizontal nodes to bear forward and reverse voltages;
the each node energy flow having continuity and bidirectionality comprises: the outermost bridge arm adopts a switching tube to ensure bidirectional flow of current of the outermost bridge arm; when an input node or an intermediate node selects an oblique adjacent node as an output branch, the input node or the intermediate node is provided with a current inflow arrow and a current outflow arrow at the same time; when the horizontal node is selected as the output branch circuit by the input node or the middle node, the bidirectional controllable switch tube is adopted to realize the bidirectional flow of current.
Further, the matrix constraint conditions in the topological network diagram satisfy the following corresponding relations:
when the input node or the intermediate node selects an orthorhombic adjacent node as an output branch, the weight w of the adjacent layer of connecting channels can be 0, 0.5 or 1;
the outermost bridge arm adopts a switching tube to ensure bidirectional flow of current of the outermost bridge arm, and the weight of a connecting path is 1;
when the input node or the intermediate node selects the horizontal node as the output branch, the weight b of the connection path of the spacing layer can be 0 or 1.
Further, the condition screening is carried out on the output coefficient matrix based on the output coefficient matrix constraint condition, and comprises feasibility screening, redundancy screening and/or characteristic optimization screening;
wherein, the feasibility screening is that all elements of an output coefficient matrix are more than or equal to 1;
the redundant screening is used for screening and deleting the condition that the intermediate node has no input branch;
the characteristic optimization screening comprises non-redundant path screening, symmetrical structure screening and/or power device minimum screening.
In a second aspect, an embodiment of the present invention provides a common dc side capacitive multilevel converter topology generation system, including:
the topology construction module is used for constructing a topology network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topology matrix expression model of the common direct-current side capacitance type multi-level converter based on the topology network diagram;
the topology traversal module is used for traversing the topology matrix expression model based on the node connection mode and the matrix constraint condition in the topology network graph to obtain an output coefficient matrix;
and the topology screening module is used for carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain the common direct current side capacitive multilevel converter topology structure.
In a third aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the method for generating a common-dc-side capacitive multilevel converter topology according to any one of the methods provided in the first aspect when executing the program.
In a fourth aspect, an embodiment of the present invention provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the method for generating a topology of a common dc-side capacitive multilevel converter according to any one of the methods provided in the first aspect.
The invention has the following beneficial effects:
the invention provides a method and a system for realizing systematic and mathematical topology generation by using a computer program mode aiming at a common direct current side capacitance type multilevel converter, which can improve the working efficiency of scientific research personnel, improve the innovativeness of the topology and promote more novel topologies to be explored. The invention realizes the innovativeness of the method for generating the common direct current side capacitive multilevel converter topology.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a topology generation method of a common-dc-side capacitive multilevel converter according to the present invention;
FIG. 2 is a topology network diagram of a common DC side capacitive four-level converter provided by the present invention;
FIG. 3 is a schematic diagram of a four-level topology matrix model provided by the present invention;
FIGS. 4(a) - (e) are schematic views of the node connection scheme provided by the present invention;
FIGS. 5(a) - (d) are schematic diagrams of the form of the bidirectional switch tube provided by the present invention;
FIG. 6 is a schematic diagram of the redundancy of the intermediate node without input branches provided by the present invention;
FIGS. 7(a) - (f) are schematic diagrams of symmetrical four-level topologies provided by the present invention;
FIG. 8 is a schematic diagram of a symmetrical four-level topology with a minimum number of power devices according to the present invention;
FIGS. 9(a) - (e) are schematic diagrams of three-level topologies provided by the present invention;
FIGS. 10(a) - (r) are schematic diagrams of symmetrical five-level topologies provided by the present invention;
fig. 11(a) - (g) are schematic diagrams of a symmetrical five-level topology with a minimum number of power devices according to the present invention;
fig. 12(a) - (d) are schematic diagrams of asymmetric five-level topologies with minimum number of power devices provided by the present invention;
fig. 13 is a schematic structural diagram of a topology generating system of a common dc side capacitive multilevel converter according to the present invention;
fig. 14 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following describes a method and a system for generating a common dc side capacitive multilevel converter topology according to the present invention with reference to fig. 1 to 14.
The embodiment of the invention provides a method for generating a common direct current side capacitive multilevel converter topology. Fig. 1 is a schematic flowchart of a method for generating a common-dc-side capacitive multilevel converter topology according to an embodiment of the present invention, where the method includes:
step 110, constructing a topological network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topological matrix expression model of the common direct current side capacitive multilevel converter based on the topological network diagram;
step 120, traversing the topology matrix expression model based on the node connection mode and the matrix constraint condition in the topology network graph to obtain an output coefficient matrix;
and step 130, performing condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain a common direct current side capacitive multilevel converter topological structure.
The method provided by the embodiment of the invention realizes the function of generating the common direct current side capacitance type multilevel converter topology through computer programming, can improve the working efficiency of scientific researchers, and improves the innovation of the topology.
Based on any one of the above embodiments, the topology network diagram is a topology network diagram with n layers of nodes corresponding to a common-dc-side capacitive multilevel converter outputting n levels; the layer 1 is a direct current bus capacitor, the layers 2 to n are power device networks, and n is a positive integer greater than 2;
specifically, fig. 2 is a topology network diagram of a common dc side capacitive four-level converter provided by the present invention, which has 4 layers of nodes, where the 1 st layer is a dc bus capacitor, and the 2 nd to 4 th layers are power device networks.
The topological network graph comprises a dotted line, a solid line, a forward arrow, a reverse arrow, an input node, an output node, an intermediate node and a level path;
the dotted line indicates that the element connecting the two nodes is a diode;
the solid line represents that the element connecting the two nodes is a switching tube without an anti-parallel diode; specifically, the switching tube includes GTO, GTR, MOSFET, IGBT, IGCT, or the like;
the forward arrow represents the indicated direction from the cathode to the anode of the diode;
the reverse arrow indicates the pointing direction from the anode to the cathode of the diode;
the input node represents a node of an input direct current source and is only connected with an output branch;
the output node represents a node on the output AC side and is only connected with an input branch;
the intermediate node represents a node between the power devices and is connected with an input branch and an output branch;
the level path is a path between the input node and the output node. Specifically, an input node S1The level output path to the A point of the AC side is called L1Level path, and so on, input node SnThe level output path to the A point of the AC side is called LnAnd (4) level path.
Based on any one of the above embodiments, the principle of maximum pressure-bearing uniformity of the power device includes: the common DC side capacitance type multilevel converter for outputting n levels has (n-1) voltage sources on the DC side, n nodes between the input DC sources, and each level channel Li(i ═ 1,2, … n) there are (n-1) power devices; wherein the (n-1) power devices comprise (n-i) reverse diodes and (i-1) forward diodes; the reverse diode is a diode with current from an output node to an input node, and the forward diode is a diode with current from the input node to the output node; the diode comprises an independent diode and an anti-parallel diode of the switching tube.
Specifically, as shown in fig. 2, when the common dc side capacitance type four-level converter outputs the highest level, L1Level path conduction, L2The level path has 1 forward diode bearing input node S1And S2A capacitor voltage between, L3The level path has 2 forward diodes bearing input node S1And S3Two capacitor voltages in between, L4The level path has 3 forward diodes bearing input node S1And S4Three capacitor voltages in between. When the output is at the lowest level, L4Level path conduction, L3The level path has 1 reverse diode bearing input node S3And S4A capacitor voltage between, L2The level path has 2 reverse diodes bearing input node S2And S4Two capacitor voltages in between, L1Level path has 3 reverse diodes bearing input node S1And S4Three capacitor voltages in between. I.e. the level path L1With 3 backward diodes(ii) a Level path L2There are 2 backward diodes and 1 forward diode; level path L3There are 1 backward diode and 2 forward diodes; level path L4There are 3 forward diodes; at this time, fig. 2 conforms to the principle of maximum pressure-bearing uniformity of the power devices, and the maximum bearing voltage of each power device is a capacitor voltage at the direct-current side.
Based on any one of the above embodiments, the topology matrix expression model of the common-dc-side capacitive multilevel converter is an (n-1) layer matrix model;
specifically, fig. 3 is a schematic diagram of a four-level topology matrix model provided by the present invention, and a corresponding 3-level matrix model can be represented as:
first layer matrix model:
Figure BDA0003194956650000091
second layer matrix model:
Figure BDA0003194956650000101
third layer matrix model:
Figure BDA0003194956650000102
where a represents the input of each layer, w represents the weight of the connecting path between adjacent layers, and b represents the weight of the connecting path between spacer layers. w-0 indicates that there is no path between the nodes, w-1 indicates that there is a bidirectional path for current between the nodes, and w-0.5 indicates that there is a unidirectional path for current between the nodes. And b-0 indicates that no path exists between the spacer nodes, and b-1 indicates that a current bidirectional path exists between the spacer nodes. Wherein a isijRepresenting the jth node of the ith layer.
Figure BDA0003194956650000103
Weight indicating connection path between ith layer and (i +1) th layerValues where x in the subscript represents the sequence number of the (i +1) th level node and y represents the sequence number of the ith level node.
Figure BDA0003194956650000104
And representing the weight of a connection path between the ith layer and the (i +2) th layer, wherein x in the subscript represents the serial number of the (i +2) th layer node, and y represents the serial number of the ith layer node. For example,
Figure BDA0003194956650000105
represents the weight of the connection path between the 1 st layer and the 2 nd layer, and particularly represents the 1 st node a of the second layer21With the 2 nd node a of the first layer12The weight of the connection path.
Figure BDA0003194956650000106
Represents the weight of the connection path between the 1 st layer and the 3 rd layer, and particularly represents the 1 st node a of the third layer31With the 2 nd node a of the first layer12The weight of the connection path.
The four-level topological matrix expression model comprises 3 adjacent layer coefficient matrixes and 2 spacing layer coefficient matrixes;
wherein, the coefficient matrix of adjacent layers is:
Figure BDA0003194956650000107
A3＝[1 1]； (4)
spacer coefficient matrix:
Figure BDA0003194956650000111
obtaining an output matrix model based on the topology matrix model:
Figure BDA0003194956650000112
wherein, ((A)3*A2+B2)*A1+A3*B1) Is an output systemNumber matrix representing output node a41To input nodes a, respectively11、a12、a13、a14The path information of (1).
Based on any of the above embodiments, as shown in fig. 4(a) to (e), the node connection method provided by the present invention is a schematic diagram, and the node connection method in the topological network diagram satisfies the following conditions: the power device is subjected to a voltage drop; each node has continuity and bidirectionality in energy flow;
the power device being subject to a voltage drop comprises: the switch tube bears forward voltage, and the diode bears reverse voltage; and bidirectional pressure-bearing power devices are arranged between the horizontal nodes to bear forward and reverse voltages. In fig. 4, the forward direction arrow of the switch tube always points from the point where the virtual potential is high to the point where the virtual potential is low, and the reverse direction arrow of the diode always points from the point where the virtual potential is low to the point where the virtual potential is high. The horizontal branch indicates that the branch needs to be able to bear forward and reverse voltages, so a bidirectional voltage-bearing power device needs to be added between horizontal nodes, as shown in fig. 4.
The each node energy flow having continuity and bidirectionality comprises: the outermost bridge arm adopts a switching tube to ensure bidirectional flow of current of the outermost bridge arm; when an input node or an intermediate node selects an oblique adjacent node as an output branch, the input node or the intermediate node has a current inflow arrow and a current outflow arrow at the same time, that is, one of the connection conditions shown in fig. 4(a) to (d) needs to be satisfied; when the horizontal node is selected as the output branch from the input node or the intermediate node, a bidirectional controllable switch tube is adopted to realize bidirectional flow of current, that is, the connection condition shown in fig. 4(e) needs to be satisfied, wherein the bidirectional controllable switch tube can adopt the switch forms shown in fig. 5(a) to (d), and the bidirectional controllable switch tube is respectively of a common collector type, a common emitter type, an inverse parallel type and a bridge type.
Based on any of the above embodiments, the matrix constraint condition in the topological network diagram satisfies the following correspondence:
when the input node or the intermediate node selects an orthorhombic adjacent node as an output branch, the weight w of the adjacent layer of connecting channels can be 0, 0.5 or 1;
specifically, w-0 indicates that there is no path between nodes, w-1 indicates that there is a bidirectional current path between nodes, and w-0.5 indicates that there is a unidirectional current path between nodes;
the outermost bridge arm adopts a switching tube to ensure bidirectional flow of current of the outermost bridge arm, and the weight of a connecting path is 1;
when the input node or the intermediate node selects the horizontal node as the output branch, the weight b of the connection path of the spacing layer can be 0 or 1.
Specifically, b-0 indicates that there is no path between the spacer nodes, and b-1 indicates that there is a bidirectional current path between the spacer nodes.
Specifically, the input node a in FIG. 312For example, the corresponding relationship between the node connection mode and the matrix constraint condition is illustrated, and the matrix corresponding to the node connection mode in fig. 4(a) is expressed as
Figure BDA0003194956650000121
The matrix corresponding to the node connection mode in FIG. 4(b) is expressed as
Figure BDA0003194956650000122
The matrix corresponding to the node connection mode in FIG. 4(c) is expressed as
Figure BDA0003194956650000123
The matrix corresponding to the node connection mode in FIG. 4(d) is expressed as
Figure BDA0003194956650000124
The matrix corresponding to the node connection mode in FIG. 4(e) is expressed as
Figure BDA0003194956650000125
And is
Figure BDA0003194956650000126
Based on any one of the above embodiments, the condition screening is performed on the output coefficient matrix based on the output coefficient matrix constraint condition, including feasibility screening, redundancy screening, and/or characteristic optimization screening;
wherein, the feasibility screening is that all elements of an output coefficient matrix are more than or equal to 1;
the redundant screening is used for screening and deleting the condition that the intermediate node has no input branch;
the characteristic optimization screening comprises non-redundant path screening, symmetrical structure screening and/or power device minimum screening. That is, the characteristic optimization screening may select specific screening conditions and combinations thereof according to actual situations, and not every screening condition must be satisfied.
Specifically, the output coefficient matrix constraint condition screening includes a first condition, a second condition and a third condition screening. The first condition screening is feasibility screening, and all elements of an output coefficient matrix need to be more than or equal to 1. And the second condition screening is redundancy screening, and screening and deleting the redundancy condition that the intermediate node has no input branch. Fig. 6 is a schematic diagram of a redundancy situation in which the intermediate node has no input branch, and if the intermediate node has no input branch but the output branch still traverses, an invalid branch as shown in fig. 6 may occur and should be deleted. The third condition screening is characteristic optimization screening, and specifically comprises the following steps:
1) non-redundant path screening:
the output coefficient matrix is required to satisfy all the elements being 1. Specifically, common DC side capacitance type four-level converter output matrix model [ a ]41]＝[1 1 1 1][a11 a12 a13 a14]TOutput coefficient Matrix Output]＝[1 1 1 1]This indicates the output node a41To the input node a11、a12、a13、a14There is only one bidirectional current path between them, and the topology is an effective multi-level topology without redundant paths.
2) Screening symmetrical structures:
each adjacent layer coefficient matrix and the spacing layer coefficient matrix are centrosymmetric matrixes. Specifically, fig. 7(a) - (f) are schematic diagrams of symmetrical four-level topology provided by the present invention, and coefficient matrix a of adjacent layers of the capacitive four-level converter on the common dc side is constrained1、A2And a spacer coefficient matrix B1、B2Symmetric topological structures are screened by central symmetric matrixes to obtain four-level topological structures of 6 symmetric non-redundant paths.
3) Screening the minimum number of power devices:
the number (g +2h) of power devices of the converter topology can be obtained by detecting the number g of non-zero elements in the coefficient matrix of the adjacent layer and the number h of non-zero elements in the coefficient matrix of the spacing layer, so that the converter topology with the least number of used power devices is obtained. Specifically, fig. 8 is a schematic diagram of a symmetrical four-level topology structure with the least number of power devices, where a topology matrix expression model is as follows:
Figure BDA0003194956650000131
the output matrix model is [ a ]41]＝[1 1 1 1][a11 a12 a13 a14]T。 (8)
Wherein the output node a41To the input node a11、a12、a13、a14There is one and only one bi-directional current path between them. And each coefficient matrix is a central symmetry matrix, which indicates that the four-level topology is a symmetrical multi-level topology structure, the four-level output can be realized by 8 switching tubes in total, and the withstand voltage of each switching tube is the voltage of a single direct-current side capacitor.
In order to facilitate understanding of the technical solution of the present invention, the following examples respectively take three levels and five levels as examples.
(1) Three-level topology generation example
According to the topology generation method of the common direct current side capacitive multilevel converter, a topology network diagram is constructed based on the principle of maximum pressure bearing uniformity of a power device, a topology matrix expression model is constructed based on a three-level topology network diagram, and a 2-layer matrix model of the three-level topology is as follows:
first layer matrix model:
Figure BDA0003194956650000141
second layer matrix model:
Figure BDA0003194956650000142
wherein, the coefficient matrix of adjacent layers is:
Figure BDA0003194956650000143
A2＝[1 1] (11)
spacer coefficient matrix:
Figure BDA0003194956650000144
the output matrix model is then:
Figure BDA0003194956650000145
traversing the topology matrix expression model based on the node connection mode and the matrix constraint condition in the topology network graph, and performing condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition, specifically:
fig. 9(a) - (d) are schematic diagrams of redundancy-free path type three-level topology structures provided by the present invention. By constraining the output matrix model [ a ]31]＝[1 1 1][a11 a12 a13]TScreening of the converter structure without redundant paths can obtain 4 three-level topologies, as shown in fig. 9(a) - (d).
Fig. 9(c) - (e) are schematic diagrams of symmetrical three-level topologies provided by the present invention. By constraining the coefficient matrix A of adjacent layers1And a spacer coefficient matrix B1All the three-level topology are centrosymmetric matrixes to screen symmetric topology structures to obtain 3 symmetric three-level topologiesThe structure is shown in FIGS. 9(c) to (e).
The number (g +2h) of power devices of the converter topology can be obtained by detecting the number g of non-zero elements in the coefficient matrix of the adjacent layer and the number h of non-zero elements in the coefficient matrix of the spacing layer, so that the converter topology with the least number of used power devices is obtained. Specifically, fig. 9(a) - (b) are schematic diagrams of three-level topologies with the least number of power devices according to the present invention.
(2) Five-level topology generation example
According to the method for generating the common direct current side capacitive multilevel converter topology, a 4-layer matrix model of a five-level topology is as follows:
first layer matrix model:
Figure BDA0003194956650000151
second layer matrix model:
Figure BDA0003194956650000152
third layer matrix model:
Figure BDA0003194956650000161
fourth layer matrix model:
Figure BDA0003194956650000162
wherein, the coefficient matrix of adjacent layers is:
Figure BDA0003194956650000163
Figure BDA0003194956650000164
A4＝[1 1]； (18)
spacer coefficient matrix:
Figure BDA0003194956650000165
the output matrix model is:
Figure BDA0003194956650000166
traversing the topology matrix expression model based on the node connection mode and the matrix constraint condition in the topology network graph, and performing condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition, specifically:
fig. 10(a) - (r) are schematic diagrams of partially symmetric five-level topologies provided by the present invention. By constraining the coefficient matrix A of adjacent layers1、A2、A3And a spacer coefficient matrix B1、B2、B3All the five-level topologies are centrosymmetric matrixes to screen symmetric five-level topologies, as shown in fig. 10(a) - (r).
On the basis of the symmetrical five-level topology shown in fig. 10, 7 symmetrical five-level converter topologies with the least number of power devices are obtained by detecting the value of (g +2h) in the coefficient matrix, and as shown in fig. 11(a) - (g), 14 power devices are needed.
If the symmetry of the structure is not considered, an asymmetric five-level topology structure with the minimum number of power devices can be obtained by detecting the value of (g +2h) in the coefficient matrix, and as shown in fig. 12(a) to (d), 12 power devices are required in total. According to the method for generating the common direct current side capacitance type multilevel converter topology, the novel common direct current side capacitance type multilevel converter topology which is few in power devices and simple in structure is obtained.
The following describes a topology generation system of a common dc side capacitive multilevel converter provided by the present invention, and the following description and the above-described topology generation method of a common dc side capacitive multilevel converter may be referred to in correspondence.
Fig. 13 is a schematic structural diagram of a topology generating system of a common-dc-side capacitive multilevel converter according to an embodiment of the present invention, and as shown in fig. 13, the system includes a topology constructing module, a topology traversing module, and a topology screening module;
the topology construction module is used for constructing a topology network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a common direct-current side capacitance type multi-level converter topology network diagram and a topology matrix expression model based on the topology network diagram;
the topology traversal module is used for traversing the topology matrix expression model based on the node connection mode and the matrix constraint condition in the topology network graph to obtain an output coefficient matrix;
and the topology screening module is used for carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain the common direct current side capacitive multilevel converter topology structure.
The system provided by the embodiment of the invention realizes the function of carrying out topology derivation and generation of the common direct current side capacitance type multilevel converter through computer programming, can improve the working efficiency of scientific researchers, and improves the innovation of the topology.
In summary, the method and the system provided by the invention construct a topology network diagram and a topology matrix expression model of the common-dc-side capacitive multilevel converter, traverse the topology matrix expression model based on a node connection mode and a matrix constraint condition in the topology network diagram, and perform condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition, so as to obtain a novel common-dc-side capacitive multilevel converter topology with fewer power devices and a simple structure. Meanwhile, the common direct current side capacitive multilevel converter follows the principle of maximum pressure bearing uniformity of the switching tube, the maximum voltage borne by each power device is the voltage of one capacitor at the direct current side, and the consistency of the power devices is improved. The method and the system for generating the common direct current side capacitive multilevel converter topology can systematically obtain various common direct current side capacitive multilevel converter topologies, and provide a new idea for generating the multilevel converter topology.
Fig. 14 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 14, the electronic device may include: a processor (processor)1410, a communication Interface (Communications Interface)1420, a memory (memory)1430 and a communication bus 1440, wherein the processor 1410, the communication Interface 1420 and the memory 1430 communicate with each other via the communication bus 940. Processor 1410 may invoke logic instructions in memory 1430 to perform a common dc side capacitive multilevel converter topology generation method comprising: constructing a topological network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topological matrix expression model of the common direct current side capacitive multilevel converter based on the topological network diagram; traversing the topological matrix expression model based on the node connection mode and the matrix constraint condition in the topological network diagram to obtain an output coefficient matrix; and carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain a common direct current side capacitive multilevel converter topological structure.
In addition, the logic instructions in the memory 1430 may be implemented in software functional units and stored in a computer readable storage medium when sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, an embodiment of the present invention further provides a computer program product, where the computer program product includes a computer program stored on a non-transitory computer-readable storage medium, where the computer program includes program instructions, and when the program instructions are executed by a computer, the computer is capable of executing the method for generating a topology of a common dc-side capacitive multilevel converter provided by the above methods, where the method includes: constructing a topological network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topological matrix expression model of the common direct current side capacitive multilevel converter based on the topological network diagram; traversing the topological matrix expression model based on the node connection mode and the matrix constraint condition in the topological network diagram to obtain an output coefficient matrix; and carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain a common direct current side capacitive multilevel converter topological structure.
In another aspect, an embodiment of the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program is implemented by a processor to execute the above-mentioned methods for generating a common dc side capacitive multilevel converter topology, where the method includes: constructing a topological network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topological matrix expression model of the common direct current side capacitive multilevel converter based on the topological network diagram; traversing the topological matrix expression model based on the node connection mode and the matrix constraint condition in the topological network diagram to obtain an output coefficient matrix; and carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain a common direct current side capacitive multilevel converter topological structure.
The above described embodiments of the apparatus are merely illustrative, wherein the steps or unit modules may or may not be physically separated, i.e. may be located in one place, or may also be distributed over a plurality of network units. Some or all of the steps or unit modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A method for generating a common direct current side capacitive multilevel converter topology is characterized by comprising the following steps:
constructing a topological network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topological matrix expression model of the common direct current side capacitive multilevel converter based on the topological network diagram;
traversing the topological matrix expression model based on the node connection mode and the matrix constraint condition in the topological network diagram to obtain an output coefficient matrix;
and carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain a common direct current side capacitive multilevel converter topological structure.
2. The method for generating topology of common-dc-side capacitive multilevel converter according to claim 1, wherein the topology network diagram is a topology network diagram with n layers of nodes corresponding to the common-dc-side capacitive multilevel converter outputting n levels; the layer 1 is a direct current bus capacitor, the layers 2 to n are power device networks, and n is a positive integer greater than 2;
the topological network diagram of the n layers of nodes comprises a dotted line, a solid line, a forward arrow, a reverse arrow, an input node, an output node, an intermediate node and a level path;
the dotted line indicates that the element connecting the two nodes is a diode;
the solid line represents that the element connecting the two nodes is a switching tube without an anti-parallel diode;
the forward arrow represents the indicated direction from the cathode to the anode of the diode;
the reverse arrow indicates the pointing direction from the anode to the cathode of the diode;
the input node represents a node of an input direct current source and is only connected with an output branch;
the output node represents a node on the output AC side and is only connected with an input branch;
the intermediate node represents a node between the power devices and is connected with an input branch and an output branch;
the level path is a path between the input node and the output node.
3. The method for generating the topology of the common-dc-side capacitive multilevel converter according to claim 1, wherein the principle of maximum pressure-bearing uniformity of the power device comprises: the common DC side capacitance type multilevel converter for outputting n levels has (n-1) voltage sources on the DC side, n nodes between the input DC sources, and each level channel Li(i ═ 1,2, … n) there are (n-1) power devices; wherein the (n-1) power devices comprise (n-i) reverse diodes and (i-1) forward diodes; the reverse diode is a diode for current flow from the output node to the input node, and the forward diode is electricA diode flowing from the input node to the output node; the diode comprises an independent diode and an anti-parallel diode of the switching tube.
4. The method for generating topology of a common dc side capacitive multilevel converter according to claim 1, wherein the topology matrix expression model of the common dc side capacitive multilevel converter is an (n-1) layer matrix model;
first layer matrix model:
Figure FDA0003194956640000021
second layer matrix model:
Figure FDA0003194956640000022
layer (n-1) matrix model:
Figure FDA0003194956640000023
the topological matrix expression model comprises (n-1) adjacent layer coefficient matrixes and (n-2) spacing layer coefficient matrixes;
wherein, the coefficient matrix of adjacent layers is:
Figure FDA0003194956640000031
Figure FDA0003194956640000032
An-1＝[1 1]；
the spacer coefficient matrix is:
Figure FDA0003194956640000033
Figure FDA0003194956640000034
obtaining an output matrix model based on the topology matrix expression model:
Figure FDA0003194956640000035
wherein, Matrix [ Output ] is an Output coefficient Matrix.
5. The method for generating the topology of the common-dc-side capacitive multilevel converter according to claim 1, wherein a node connection manner in the topology network diagram satisfies the following condition: the power device is subjected to a voltage drop; each node has continuity and bidirectionality in energy flow;
wherein the power device being subject to a voltage drop comprises: the switch tube bears forward voltage, and the diode bears reverse voltage; a bidirectional pressure-bearing power device is arranged between the horizontal nodes to bear forward and reverse voltages;
the each node energy flow having continuity and bidirectionality comprises: the outermost bridge arm adopts a switching tube to ensure bidirectional flow of current of the outermost bridge arm; when an input node or an intermediate node selects an oblique adjacent node as an output branch, the input node or the intermediate node is provided with a current inflow arrow and a current outflow arrow at the same time; when the horizontal node is selected as the output branch circuit by the input node or the middle node, the bidirectional controllable switch tube is adopted to realize the bidirectional flow of current.
6. The method for generating the topology of the common-dc-side capacitive multilevel converter according to claim 1, wherein the matrix constraint condition in the topology network diagram satisfies the following correspondence:
when the input node or the intermediate node selects an orthorhombic adjacent node as an output branch, the weight w of the adjacent layer of connecting channels can be 0, 0.5 or 1;
the outermost bridge arm adopts a switching tube to ensure bidirectional flow of current of the outermost bridge arm, and the weight of a connecting path is 1;
when the input node or the intermediate node selects the horizontal node as the output branch, the weight b of the connection path of the spacing layer can be 0 or 1.
7. The method for generating the topology of the common-DC-side capacitive multilevel converter according to claim 1, wherein the condition screening is performed on the output coefficient matrix based on output coefficient matrix constraint conditions, and includes feasibility screening, redundancy screening and/or characteristic optimization screening;
wherein, the feasibility screening is that all elements of an output coefficient matrix are more than or equal to 1;
the redundant screening is used for screening and deleting the condition that the intermediate node has no input branch;
the characteristic optimization screening comprises non-redundant path screening, symmetrical structure screening and/or device quantity minimum screening.
8. A common DC side capacitive multilevel converter topology generation system is characterized by comprising:
the topology construction module is used for constructing a topology network diagram based on the target level number and the maximum pressure-bearing uniformity principle of the power device, and constructing a topology matrix expression model of the common direct-current side capacitance type multi-level converter based on the topology network diagram;
the topology traversal module is used for traversing the topology matrix expression model based on the node connection mode and the matrix constraint condition in the topology network graph to obtain an output coefficient matrix;
and the topology screening module is used for carrying out condition screening on the output coefficient matrix based on the output coefficient matrix constraint condition to obtain the common direct current side capacitive multilevel converter topology structure.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor when executing the program implements the steps of the method of generating a common dc side capacitive multilevel converter topology according to any of claims 1 to 7.
10. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the steps of the method for generating a common dc side capacitive multilevel converter topology according to any of claims 1 to 7.
CN202110888135.6A 2021-08-03 2021-08-03 Topology generation method and system for common direct current side capacitor type multi-level converter Active CN113691149B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110888135.6A CN113691149B (en) 2021-08-03 2021-08-03 Topology generation method and system for common direct current side capacitor type multi-level converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110888135.6A CN113691149B (en) 2021-08-03 2021-08-03 Topology generation method and system for common direct current side capacitor type multi-level converter

Publications (2)

Publication Number Publication Date
CN113691149A true CN113691149A (en) 2021-11-23
CN113691149B CN113691149B (en) 2023-09-26

Family

ID=78578668

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110888135.6A Active CN113691149B (en) 2021-08-03 2021-08-03 Topology generation method and system for common direct current side capacitor type multi-level converter

Country Status (1)

Country Link
CN (1) CN113691149B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040172603A1 (en) * 2003-02-14 2004-09-02 Iwatt Multi-output power supply design system
CN108768182A (en) * 2018-06-29 2018-11-06 浙江大学 Multilevel matrix converter and its clamping capacitor voltage control method suitable for high power density occasion
CN111046254A (en) * 2019-12-11 2020-04-21 北京交通大学 Programmable non-isolated DC-DC converter topology searching method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040172603A1 (en) * 2003-02-14 2004-09-02 Iwatt Multi-output power supply design system
CN108768182A (en) * 2018-06-29 2018-11-06 浙江大学 Multilevel matrix converter and its clamping capacitor voltage control method suitable for high power density occasion
CN111046254A (en) * 2019-12-11 2020-04-21 北京交通大学 Programmable non-isolated DC-DC converter topology searching method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LIPING MO等: ""From Components to Converters: A Fundamental Topology Derivation Method for Single-Inductor Multi-Input Multi-Output Converters Based on Graph Theory"" *

Also Published As

Publication number Publication date
CN113691149B (en) 2023-09-26

Similar Documents

Publication Publication Date Title
Saeedian et al. Cascaded multilevel inverter based on symmetric–asymmetric DC sources with reduced number of components
CN108476000B (en) Single-phase four-level inverter topology circuit and three-phase four-level inverter topology circuit
CN102577072A (en) Modified voltage source converter structure
WO2013143037A1 (en) Topological method of modular multilevel converter structure based on loop nesting mechanism
Tian et al. Review, classification and loss comparison of modular multilevel converter submodules for HVDC applications
CN110460100B (en) Micro-grid dynamic compensation control method and system based on distributed residual error generator
CN105515590A (en) Successive cancellation list polarization code decoding algorithm with effective low complexity based on random binary data flows and decoding structural frame thereof
Choupan et al. A simple unit cell structure for an efficient sketch of series‐connected multilevel inverters
Aguilera et al. Model predictive control of cascaded H-bridge inverters based on a fast-optimization algorithm
CN104038052B (en) Modularization multi-level converter voltage balance control method
CN113691149B (en) Topology generation method and system for common direct current side capacitor type multi-level converter
CN113708655B (en) Inverter switching tube fault tolerance control method based on self-adaptive SVPWM
Taheri et al. A multilevel inverter using switched capacitors with reduced components
Sen Goopta et al. Asymmetrically switched CHB multilevel inverters with harmonic mitigation techniques applied to photovoltaic power generation
Taha et al. Red Deer Algorithm-Based Optimal Total Harmonic Distortion Minimization for Multilevel Inverters
Shehadeh et al. Photovoltaic multi-level inverters technology
CN115842484B (en) Single-phase four-bridge arm modularized multi-level converter and regulation and control method thereof
CN109120174B (en) Capacitance voltage balancing method based on dual MMC module
Fang et al. Symmetries in power electronics
CN115603605A (en) Hybrid multi-level inverter prediction control method
Kumar et al. A novel topology of fifteen level multilevel inverter with harmonic elimination using GASHE
CN211656011U (en) Three-phase-single-phase power electronic converter system
Kapustin et al. An overview of main multilevel inverter topologies
CN117134639B (en) Converter bridge arm circuit control method and device, electronic equipment and computer equipment
CN114765427B (en) MMC capacitor voltage balance control method based on switching state matrix grouping rotation

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant