WO2013143037A1

WO2013143037A1 - Topological method of modular multilevel converter structure based on loop nesting mechanism

Info

Publication number: WO2013143037A1
Application number: PCT/CN2012/000608
Authority: WO
Inventors: 赵成勇; 刘兴华; 彭茂兰; 张宝顺
Original assignee: 华北电力大学
Priority date: 2012-03-31
Filing date: 2012-05-07
Publication date: 2013-10-03
Also published as: CN102611345A

Abstract

A topological method of a modular multilevel converter structure based on a loop nesting mechanism. First, according to a requirement on the number of output levels, the number of loop nesting layers and the number of sub-modules at each layer are selected. Next, according to an output direct current bus voltage (U_dc) and the determined number of nesting layers and number of sub-modules at each layer, capacitance and voltage rated values of the sub-modules at each layer are set. Further, sub-modules classified according to the layer are all serially connected, and are serially connected to a commutation reactor (L) that is used as a converter bridge arm of the modular multilevel converter. The method can ensure that the number of required sub-modules is obviously reduced under the condition that the number of output voltage levels and the output direct current voltage are fixed, so as to reduce the redundancy of the primary system and the complexity of a control system.

Description

Topological method based on cyclic embedded multi-level converter structure

Technical field

The invention belongs to the technical field of transmission and distribution, and particularly relates to a topology method of a modular multi-electron converter structure based on a loop nesting mechanism.

Background technique

In recent years, high-voltage and high-power fully-controlled power electronic devices (such as IGBTs and IGCTs) have been widely used in power transmission systems and low-voltage distribution networks. The main application areas are high-voltage DC based on voltage source converters. Transmission (VSC-HVDC) technology. Compared with the traditional two-level and three-level VSC-HVDC, the modular multi-level converter proposed by Siemens ~~ MMC (sub-module is half-bridge structure) topology has a large number of IGBTs without direct connection, the device withstands the voltage The rate of change is low, and the electromagnetic interference is small; At the same time, at the same voltage level, since it requires twice the switching device and needs to perform voltage balance control on the dispersed sub-module capacitors, the system state quantity information that the control system needs to collect and process will be greatly increased, thereby controlling it. The system has become very complicated.

The world's first commercial operation of the MMC-HVDC project is the US's Transit Bell (TBC) project, which has a rated capacity of 400 dc, a DC voltage of ±200 kV, and 216 sub-modules in each inverter arm. In addition, built in 2013 to Spain, France MC- HVDC project INELFE, rated capacity of 2X 1000MW _o practical engineering, in order to meet the DC bus voltage, AC output voltage harmonic content requirements, etc., we need to adopt a higher level The number of submodules required has also increased significantly. For example, in the TBC project, 216 X6=1296 submodules are required for single-ended. In order to meet the sub-module voltage equalization requirements, it is necessary to collect 1296 sub-module capacitor voltages and output 2592 trigger pulses, which results in a system that is very complicated and the control system is very complicated.

Alstom proposes a topology in which a modular multilevel converter is combined with a two-level VSC to effectively avoid energy exchange between the DC side and the AC side when the DC side of the converter is shorted. Under the same level requirement, the number of sub-modules required is halved. However, since the sub-module is used in the H-bridge structure, the amount of the device is unchanged. If the switching device required for the two-level VSC is considered, the amount of the IJ device will be Increased, so the control system simplification effect is not obvious.

Summary of the invention The object of the present invention is to solve the technical problem that the primary multi-level converter realizes a high level, the primary system is too complicated, and the control system is too complicated. A modular multi-level switching based on the loop nesting mechanism is proposed. The topology method of the streamer structure is characterized in that the topology steps of the modular multilevel converter structure are as follows: Step 1, according to the requirements of the harmonic content of the output voltage of the AC side of the converter, determine the number of output levels that meet the requirements (N _tat ). The number of loop nesting layers (H), the number of sub-modules (Mi) and the number of output levels (N _lout ) satisfy the following relationship, and there are many kinds of Mi (i=l, 2, ..., H) Value combination.

Step 2: According to the output DC bus voltage (U _dc ) of the converter and the number of loop nesting layers obtained in step 1 and the number of sub-modules in each layer, the sub-module capacitor voltage rating to be set for each sub-module is obtained. Calculated as follows:

U^ U^ _(i+ o X (Mi+1) (i=l, 2, ···, Nl) (2) U _dc II LX ( Π(Μ _{ί +} 1)-1) (3) where: Indicates the sub-module capacitor voltage rating of the lowest level nested neutron module;

LI represents the sub-module capacitor voltage rating of the i-th nest, where the i-th layer is the parent nesting layer of the (i+1)th layer;

U _i+1 ) represents the sub-module capacitor voltage rating of the (i+1)th layer (the sub-level nesting layer of the i-th layer); the other symbols in the formula have the same meanings as in the formula (1);

Step 3: All the sub-modules classified by layer are connected in series, and a commutation reactance is connected in series, and is used as a module; the commutating bridge arm of the t-yao multi-level converter forms a new modular multi-level converter Topology.

The beneficial effects of the present invention are the proposed topology method of the modular multilevel converter structure based on the loop nesting mechanism, which can ensure that the required sub-reduction is significantly reduced under the condition that the output voltage level and the output DC voltage are constant. The number of modules reduces the complexity of the system and the complexity of the control system. The above topology method does not define the specific configuration of the sub-modules. Therefore, sub-modules of different structures, such as a half-bridge structure, an H-bridge structure, etc. Both apply to this topology method.

DRAWINGS

Figure 1 is a diagram showing the general structure of the new modular multilevel converter topology.

Figure 2 is an explanatory diagram of the i-th nested structure in the topology.

Figure 3 is an illustration of a 2-layer nested 36-level topology of the topology.

Figure 4 is an explanatory diagram of the first layer nested structure of the topology.

Figure 5 is. A description of the second-level nested structure of the topology.

Symbols in the figure: A, B, C in Figure 1 represent the three-phase AC side of the MMC converter; NL„ NL ₂ , ..., NLH, respectively indicate the first layer of nesting in a bridge arm, the second layer is embedded Set, ..., nth nesting; L means bridge arm reactor; represents the voltage difference between the MMC positive and negative DC bus.

In Figure 2, SMi represents the i-th nest; SM„ SM ₂ , ..., SM^ represents the first sub-module of the MMC i-th nest, the second module, ..., the m-th sub-module.

In Figure 3, A, B, and C represent the three-phase AC side of the MMC inverter; it indicates that the first layer of the MMC is nested, that is, the parent nesting, and NL ₂ represents the second layer of the bridge arm of the 匪C. , that is, sub-level nesting; L means bridge arm reactor; represents the voltage difference between the MMC positive and negative DC bus. '

In Figure 4, L represents the first layer of nesting, that is, the parent nesting; SM>, SM ₂ , ···, SMs respectively represent the first submodule of the MMC layer nesting, the second submodule, ···, The fifth sub-module; I ^ represents the rated capacitance voltage of the sub-module in the sub-nesting, 6X0» represents the rated capacitance voltage of the sub-module in the parent nesting, g|1⁄2 times the sub-module neutron module capacitor voltage.

In Figure 5, NL ₂ represents the second layer nesting, that is, the child nesting; the rest of the symbols have the same meaning as in Fig. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a topology method of a modular multilevel converter structure based on a loop nesting mechanism. The novel modular multilevel converter topology of the present invention will be described in detail below with reference to the accompanying drawings. . Figure 1 shows a general structure of the new modular multilevel converter topology; Figure 2 shows An illustration of the i-th nested structure in the topology. In Figure 1, A, B, and C represent the three-phase AC side of the MMC inverter; N NL ₂ , ..., NL _H , which represent the first layer nesting in the MMC arm, the second layer nesting, ..., η Layer nesting; L means bridge arm reactor; represents the voltage difference between the MMC positive and negative DC bus.

In Fig. 2, SMi indicates the i-th layer nesting; SM, SM ₂ , ···, SM» respectively indicate the first sub-module in the c-th layer nesting, the second row module, ···, the m-th module . Step 1: According to the requirements of the harmonic content of the output voltage of the AC side of the inverter, determine the number of output levels (N _tat ) that meet the requirements. According to the topology diagram shown in FIG. 1 and FIG. 2, the number of loop nesting layers (H), the number of sub-modules of each layer (Mi) and the number of output levels (N _lout ) satisfy the following relationship, and H and (i= l, 2, ..., H) There are multiple combinations of values.

Step 2: According to the inverter output DC bus voltage ( ), the number of loop nesting layers (H) and the number of sub-modules in each layer), the sub-module capacitor voltage rating to be set for each sub-module can be obtained. Calculated as follows:

U _sm . _H = - (3)

H o X (M _i+1 +1) (i=l,2, ···, Hl) (2)

Where: represents the sub-module capacitor voltage rating of the lowest nested neutron module;

Indicates the sub-module capacitor voltage rating of the i-th nest, where the i-th layer is the parent of the (i+1)th layer

U ( _i+1 ) represents the sub-module capacitor voltage rating of the (i+1)th layer (the sub-level nesting layer of the i-th layer); the other symbols in the formula have the same meaning as in the equation (1).

Step 3: All the sub-modules classified by layer are connected in series, and a commutation reactance is connected in series, which is used as a commutating bridge arm of the modular multi-level converter to form a new modular multi-level converter topology. Structure (as shown in Figure 1). The specific topology and parameters of the inverter can be determined by the number of nesting layers determined in steps 1 and 2, the ± modulus of each layer, and the capacitor voltage rating of each sub-module. The first layer of the MMC is nested in the first layer U, the second layer is nested NL ₂ ,..., the nth layer is nested NL _{n in} series, and then the bridge arm reactor L is connected to form a commutating bridge arm, which can be determined The topology of the overall converter.

Figure 3 shows an illustration of a 2-layer nested 36-level topology of the topology. In the figure, A, B, C represent the three-phase three-phase of the MMC inverter; NL represents the first layer of nesting in the MMC arm, that is, the parent nesting, and NL ₂ represents the second layer nesting in the arm of the MMC. That is, sub-level nesting; L means bridge arm reactor; represents the voltage difference between the MMC positive and negative DC bus. The modules of the first and second nests each have 5 submodules: t Yao multilevel converter topology; Figure 4 shows the topology of the first layer nested structure diagram, Figure 5 A description of the second-level nested structure shown as a topology; that is, the representation of the topology represents the first layer of nesting, that is, the parent nesting and the second layer nesting, that is, the specific structure within the child nesting Figure. In the figure, SM, SM ₂ , ..., SMa respectively represent the first sub-module of the MMC nesting layer, the second sub-module, ···, the fifth sub-module; IL represents the rated capacitance of the sub-module in the sub-level nesting The voltage, 6XIL, represents the nominal capacitance voltage of the sub-module in the parent nested, g卩6 times the sub-module neutron module capacitor voltage. As can be seen from equation (1), the number of levels that the topology can output is 36 levels. It can be known from equation (3) that the topology output DC voltage is 35 XIL indicating the sub-module capacitor voltage rating of the sub-module.

Claims

Claim

A topology method of a modular multilevel converter structure based on a loop nesting mechanism, characterized in that the topology steps of the modular multilevel converter structure are as follows: Step 1, according to the AC side of the converter The output voltage harmonic content is required to determine the number of output levels (N _lout ) that meet the requirements. The number of loop nesting layers (H), the number of sub-modules in each layer (M and the number of output levels (N _la J satisfies the following relationship, and there are many different combinations with Mi (i=l, 2, ..., H) Combination of values.

Step 2: According to the output DC bus voltage of the converter (I and the number of loop nesting layers obtained in step 1 and the number of sub-modules in each layer, the sub-module capacitor voltage rating to be set for each sub-module is obtained, and the calculation formula is calculated. as follows:

H ₊₁₎ X (M _i+1 +1 ) (i=l,2, ···, Hl ) (3)

Where: 11^ indicates the capacitor voltage rating of the lowest nested neutron module;

I] represents the sub-module capacitor voltage rating of the i-th layer nested, where the i-th layer is the parent nesting layer of the (i+1)th layer;

Indicates the sub-module capacitor voltage rating of the (i+1)th layer (the sub-level nesting layer of the i-th layer); the other symbols in the formula have the same meaning as in the formula (1);

Step 3: All the sub-modules classified by layer are connected in series, and a commutating reactance is connected in series, and is used as a commutating bridge arm of the modulo ± multi-level converter, thereby forming a novel modular multi-level converter topology. .