CN115603605A - Hybrid multi-level inverter prediction control method - Google Patents

Hybrid multi-level inverter prediction control method Download PDF

Info

Publication number
CN115603605A
CN115603605A CN202211295777.6A CN202211295777A CN115603605A CN 115603605 A CN115603605 A CN 115603605A CN 202211295777 A CN202211295777 A CN 202211295777A CN 115603605 A CN115603605 A CN 115603605A
Authority
CN
China
Prior art keywords
voltage
level inverter
space vector
control method
bridge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211295777.6A
Other languages
Chinese (zh)
Inventor
邢相洋
周广涛
刘畅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong University
Original Assignee
Shandong University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong University filed Critical Shandong University
Priority to CN202211295777.6A priority Critical patent/CN115603605A/en
Publication of CN115603605A publication Critical patent/CN115603605A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/123—Suppression of common mode voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2300/00—Systems for supplying or distributing electric power characterised by decentralized, dispersed, or local generation
    • H02J2300/20—The dispersed energy generation being of renewable origin
    • H02J2300/22—The renewable source being solar energy
    • H02J2300/24—The renewable source being solar energy of photovoltaic origin
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention provides a hybrid multilevel inverter prediction control method, which utilizes a discrete model predicted by a single vector model to establish a value function without a weight factor, and utilizes the predicted voltage at the minimum value of the value function to replace a reference voltage to carry out space vector modulation. The fault-tolerant control method comprises the steps of establishing a seven-level voltage space vector diagram, removing coordinates lost due to the fact that H bridge units are removed by fault bypasses in the space vector diagram, and continuously performing space vector modulation by using the remaining coordinates. The method utilizes single vector model prediction, reduces the calculated amount of a value function while ensuring the accuracy, and reduces the common mode voltage of the system by using a common mode reduction method, so that the method can be applied to the photovoltaic industry to prevent larger common mode voltage from damaging other devices.

Description

Hybrid multi-level inverter prediction control method
Technical Field
The invention belongs to the technical field of inverter control, and relates to a hybrid multi-level inverter prediction control method.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
In photovoltaic power generation, with the gradual use of a multi-level inverter, the number of switching devices is increased, the system is more complex, and the difficulty of the regulation and control technology is greatly increased. In addition, when the switching device fails, the output waveform and the output voltage quality are affected slightly, and the power supply system fails to work seriously, which will cause irreversible influence on aspects such as life and property safety. Therefore, research into fault-tolerant control of multi-level inverters is very important.
The hybrid topology seven-level inverter is formed by connecting a T-type three-level inverter and three H-bridge units in series. Therefore, the topology combines the advantages of both topologies, the T-inverter as the main topology only transmits active power at three levels of the output voltage, and the H-bridge unit only transmits reactive power. In addition, the peak-to-peak value of the topology is 6E, which is 1.5 times of the T-shaped three-level peak-to-peak value, which is equivalent to increasing the direct-current input voltage, and further increasing the utilization rate of the direct-current voltage. Compared with a cascade H-bridge seven-level inverter, the topology has the advantages that fewer switching devices are used, the modulation method is simpler, and the failure probability of the switching devices is lower.
However, the hybrid topology seven-level inverter has more switching devices, so that the switching devices are prone to malfunction when output voltage modulation is performed, and the switching devices in the H-bridge unit section have higher malfunction probability due to higher frequency of use.
The topology has 7 output voltage levels which correspond to 12 switching modes respectively, wherein only the output voltage is +/-3E and corresponds to one switching mode, and the other output voltage states correspond to two switching modes. Thus, fault-tolerant control of relatively slight faults can also be achieved by exploiting the switched redundancy of the output voltages of the topology. However, when the switching device has more faults and the output voltage waveform has serious distortion, other fault-tolerant control methods are needed.
Disclosure of Invention
The invention provides a hybrid multi-level inverter prediction control method for solving the problems, which utilizes single vector model prediction to reduce the calculated amount of a value function while ensuring the accuracy, and uses a common mode reduction method to reduce the common mode voltage of a system, so that the method can be applied to the photovoltaic industry to prevent larger common mode voltage from damaging other devices.
According to some embodiments, the invention adopts the following technical scheme:
a hybrid multilevel inverter predictive control method comprises the following steps:
establishing a value function without a weight factor by using a discrete model predicted by a single vector model, and performing space vector modulation by using a voltage vector selected when the value function is minimum to replace a reference voltage vector;
when a certain phase H bridge unit fails, fault-tolerant control is carried out, the H bridge unit is entirely bypassed, and the hybrid topology seven-level inverter in normal work is converted into a T-type three-level inverter in failure work to maintain the normal work of the system.
As an alternative embodiment, the construction process of the discrete model predicted by the single vector model comprises the following steps: according to a kirchhoff voltage law, obtaining output voltage of the hybrid topology inverter, converting the voltage into a current form, deducing a mathematical model of the output voltage under an alpha-beta orthogonal coordinate system by using Clarke transformation, representing a continuous model as a discrete model according to a sampling period, and predicting a reference voltage vector of a control target at the next moment.
As an alternative embodiment, a cost function without a weighting factor is constructed, a basic voltage vector closest to the voltage predicted by the model is selected through calculation of the cost function to replace a reference voltage vector for space vector modulation, and the switching state of the switching device is further controlled to output the voltage.
Further, the fault-tolerant control method is to establish a seven-level voltage space vector diagram, remove the coordinates lost by bypassing the H-bridge unit due to faults in the space vector diagram, and continue to perform space vector modulation by using the remaining coordinates.
Further, when the H-bridge unit is bypassed, the coordinates corresponding to the fault phase in the space vector diagram are screened, the coordinates which do not meet the fault-tolerant control method are removed, and the remaining coordinates are used for space vector modulation.
Furthermore, the coordinate with the minimum common-mode voltage corresponding to each point in the space vector diagram is calculated through the definition of the common-mode voltage, and the space vector modulation is carried out by using the voltage vector corresponding to the coordinate.
A mixed topology seven-level inverter comprises three-phase bridge arms which are connected in parallel, wherein each phase of bridge arm comprises one bridge arm and one H-bridge unit of a T-type three-level inverter, one bridge arm of the T-type three-level inverter is formed by connecting two switching tubes which are reversely connected in series with one half-bridge unit, and two ends of the half-bridge unit are connected with two ends of two capacitors which are connected in series with a direct current link;
the H-bridge unit consists of two-level half-bridge units formed by connecting four switching tubes in series end to end, and the upper and lower midpoints of an H-bridge unit circuit are connected with two ends of the flying capacitor; the middle points of the two half-bridge units are respectively connected with a front-stage T-type three-level inverter and a rear-stage power grid;
the control is performed using the predictive control method described above.
A computer readable storage medium having stored therein a plurality of instructions adapted to be loaded by a processor of a terminal device and to carry out the steps of the method.
A control device comprising a processor and a computer readable storage medium, the processor for implementing instructions; the computer readable storage medium is used for storing a plurality of instructions adapted to be loaded by a processor and to perform the steps of the method.
Compared with the prior art, the invention has the beneficial effects that:
(1) The output voltage before the fault is seven levels, compared with a T-type three-level inverter, the method is equivalent to improving the direct current input voltage, so that the utilization rate of the direct current voltage is improved, and the waveform of the output voltage is more accurate sine wave.
(2) The method utilizes single vector model prediction, and reduces the calculation amount of the cost function while ensuring the accuracy.
(3) According to the method, after a certain switching tube of the H-bridge unit fails, the output voltage of a fault phase is reduced from seven levels to three levels, the voltage is not distorted, and the normal work of the inverter can be maintained.
(4) The method reduces the common mode voltage of the system by using a common mode reduction method, so that the method can be applied to the photovoltaic industry and can prevent the generation of larger common mode voltage from damaging other devices.
(5) The method is applied to the photovoltaic industry, the coordinate with the minimum common-mode voltage absolute value of each point in the space vector diagram is selected through calculation of the common-mode voltage to carry out space vector modulation, and the common-mode voltage of the system is reduced by adopting the common-mode voltage reduction method.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
Fig. 1 is a schematic diagram of a hybrid topology seven-level inverter topology according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of model prediction using voltage vectors according to an embodiment of the present invention.
Fig. 3 is a spatial vector diagram for normal operation of the a-minus common mode according to an embodiment of the present invention.
Fig. 4 is a space vector diagram of a minus a common mode H-bridge cell failure according to an embodiment of the present invention.
Fig. 5 (a) is a simulation diagram of the output voltage of the a-phase in normal operation after common mode reduction according to an embodiment of the present invention.
Fig. 5 (b) is a simulation diagram of output voltage after fault-tolerant control when the a-phase H-bridge unit fails after common mode reduction processing according to an embodiment of the present invention.
Fig. 5 (c) is a simulation diagram of the output line voltage when the AB two phases after common mode reduction work normally according to an embodiment of the present invention.
Fig. 5 (d) is a simulation diagram of output line voltages after fault-tolerant control when a phase a H bridge unit fails and a phase B operates normally after common mode reduction according to an embodiment of the present invention.
Fig. 5 (e) is a simulation diagram of three-phase output current in normal operation after common mode reduction according to an embodiment of the present invention.
Fig. 5 (f) is a three-phase output current simulation diagram after fault-tolerant control at a failure of an a-phase H-bridge unit after common-mode reduction processing according to an embodiment of the present invention.
Fig. 5 (g) is a simulation diagram of the common mode voltage during normal operation after common mode reduction according to an embodiment of the invention.
Detailed Description
The invention is further described with reference to the following figures and examples.
It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
The invention provides a hybrid topological structure which comprises three-phase bridge arms connected in parallel, wherein each phase of bridge arm comprises an H-bridge unit and one bridge arm of a T-type inverter. One bridge arm of the T-type inverter consists of two parts of units, wherein the first unit is formed by reversely connecting two IGBT switching tubes in series, and the second unit is formed by forwardly connecting two IGBT switching tubes in series to form a two-level half-bridge unit. The head end and the tail end of the second unit are required to be respectively connected with capacitors with the capacitance value of 2E, the two capacitors are connected in series, one end of the first unit is connected with the connection point of the two capacitors, and the other end of the first unit is connected with the midpoint of the second unit, so that a bridge arm of the T-shaped three-level inverter is formed. The H-bridge unit comprises two parallel two-level half-bridge units formed by connecting four IGBT switching tubes in series end to end, and a capacitor with a capacitance value of E is connected with the two half-bridge units in parallel to form the H-bridge unit. The topology is formed by connecting a connecting point of a first unit and a second unit in a bridge arm of the T-type three-level inverter with a midpoint of one of two half-bridge units in the H-bridge unit. Each cell is grounded via a capacitor through a star connection.
In some embodiments, the maximum voltages borne by different switch tubes are different, so that the switch tubes in different positions can adopt different voltage levels or types of power devices, so as to save hardware cost.
According to the control method of the hybrid topology seven-level inverter, a discrete model predicted by a single vector model is utilized to establish a value function without a weight factor, and space vector modulation is carried out by utilizing the predicted voltage when the value function is the minimum value.
In some embodiments, fault-tolerant control after a fault of a certain IGBT switching tube in the H-bridge unit is implemented by bypassing the H-bridge unit, an original hybrid topology seven-level inverter is converted into a T-type three-level inverter, and the output voltage of a fault phase is reduced from seven levels to three levels to maintain the normal operation of the inverter.
In some embodiments, the fault tolerance method is to establish a seven-level voltage space vector diagram, remove the coordinates lost by bypassing the H-bridge unit due to the fault in the space vector diagram, and continue to perform space vector modulation using the remaining coordinates.
The topology is applied to the photovoltaic industry, and the coordinate with the minimum common-mode voltage absolute value of each point in the space vector diagram is selected through the calculation of the common-mode voltage to perform space vector modulation.
In some embodiments, after removing the lost coordinates in the space vector diagram due to the fault bypassing the H-bridge unit, the lost coordinates in the space vector diagram for reducing the common mode voltage are removed, and the space vector modulation is continued by using the remaining coordinates.
As an exemplary embodiment of the present invention, a hybrid topology seven-level inverter topology is provided. As shown in figure 1, the hybrid topology is formed by connecting one bridge arm of a T-type three-level inverter and one H-bridge unit in series, S x1 -S x8 Is 8 full-controlled switching devices, V cd1 And V cd2 Respectively, the DC link upper and lower capacitor voltages, U fx Flying capacitor voltage, (x = a, b, c). The voltage across Cd1 and Cd2 is 2E, the DC link voltage is constant at 4E, and the flying capacitor voltage is E. S. the x1 And S x2 Bear the whole direct currentVoltage of power supply (4E), S x3 And S x4 The voltage born by the device is half (2E), S of the direct current power supply x5 -S x8 Bears the voltage (E) of the flying capacitor. i all right angle Cx Is a current flowing into the flying capacitor Cx, i mx Is the current flowing from the midpoint of the dc link. For T-type three-level inverter, S x1 And S x2 、S x3 And S x4 The driving signals are complementary, and the T-type topology can generate three levels of-2E, 0 and 2E by controlling the on and off of the four switching devices, so that the T-type inverter is a three-level topology. For H-bridge units, the upper and lower switching devices of each side bridge arm are complementarily conducted, namely S x5 And S x6 、S x7 And S x8 The driving signals are complementary, and the H-bridge unit can generate three levels of-E, 0 and E by controlling the on-off of the four switching devices, so that the H-bridge unit is also a three-level topology. Will S x1 And S x2 Midpoint and S x5 And S x6 The obtained mixed topology can output seven output levels of-3E to +3E, so that the cascade topology structure is a seven-level inverter. The seven levels from-3E to 3E correspond to 12 different conduction paths, wherein when the output voltage is +/-3E, only one conduction path is corresponded, and when the output voltage is-2E- +2E, each output voltage corresponds to two conduction paths. Table I gives the switch states and output voltage states for the different conduction paths.
Table I output voltage state and switch state table
Figure BDA0003902645280000091
According to the invention, a control method using the topology structure is also provided.
In FIG. 2, a space vector modulated reference voltage V is obtained by model prediction MPC according to an embodiment of the present invention ab And then the voltage is used for PWM modulation to control the switching state of the switching device.
The concrete method of model prediction is to obtain a mixed topology according to kirchhoff voltage lawThe output voltage of the inverter is converted into a current form, and a mathematical model of the output voltage under an alpha beta orthogonal coordinate system is deduced by Clarke transformation. Let the sampling period Ts, the resistance R, and the inductance to ground L, V α (k)V β (k) Voltage, i, for conversion of a discrete model at time k into two phases α β α (k)i β (k) Current, i, transformed into two phases of alpha beta for a discrete model at time k α (k-1)i β (k-1) a current for converting the discrete model at the time of k-1 into two phases of alpha and beta, e α (k)e β (k) For the transformation of the k-time discrete model into the power grid voltage of alpha beta two phases, the continuous model is expressed as a discrete model, and the discrete model is expressed as follows:
Figure BDA0003902645280000101
after the ABC three phases are changed into alpha beta two phases through Clarke transformation, the current i (k) at the moment k and the change rate of the current i (k) at the moment are used for predicting the current i (k + 1) at the next moment, and then the current is converted into voltage to obtain the predicted reference voltage.
In order to realize the optimal current tracking performance, a current tracking cost function g of the MPC based on the voltage model is provided as follows:
Figure BDA0003902645280000102
wherein,
Figure BDA0003902645280000103
the k +1 moment discrete model is transformed into alpha beta two phases, and the voltage V is obtained through model prediction α V β And converting the discrete model into each voltage vector after alpha and beta phases.
Substituting the coordinates of the voltage vector in the space vector diagram and the voltage obtained from the discrete mathematical model into the calculation of the cost function, and substituting the voltage vector corresponding to the minimum value of the obtained cost function for the reference voltage to perform space vector modulation.
According to one embodiment of the inventionIn the embodiment, when the a-phase normally operates, the number of vectors is 7 × 7=343 due to the seven-level inverter. Each voltage vector may be represented by (x, y, z), where x, y, z represent numbers corresponding to voltage values of the three-phase outputs a, B, and C, respectively. For example, the voltage vectors corresponding to the origin coordinates (3, 3) are voltage vectors of which the three-phase output voltages A, B and C are all 0. Only considering the condition that the H bridge unit has a fault, when a certain switching tube of the H bridge unit has a fault, the whole H bridge unit is bypassed, namely the original T-type cascade H bridge hybrid topology inverter is converted into only one T-type three-level inverter for output, and the DC link voltage V is output cd1 And V cd2 The output voltage after bypassing the H bridge unit is 2E, the output voltage has only three levels of-2E, 0 and 2E, the corresponding coordinate value is 1,3 and 5, and the other levels of voltages cannot be output, and the inverter is reduced from the original seven level to three level to maintain normal operation. If a certain switch tube of the A-phase H-bridge unit fails, only the coordinates of the vector are kept to be (x, y, z) (x =1,3, 5) after fault-tolerant processing, at this time, the number of the residual space vectors is 147, and the number of the residual coordinates is 97. Because the equipment is applied to photovoltaic grid connection, the safety of the equipment is ensured by reducing common-mode leakage current by reducing common-mode voltage of the equipment. And calculating the common-mode voltage of the 343 vectors one by one, and marking the coordinate with the minimum common-mode voltage absolute value in the coordinate corresponding to each calculated vector in a space vector diagram.
The common-mode voltage of the inverter can be expressed as
V CMV ＝(V an +V bn +V cn )/3
V an ，V bn ，V cn Voltages of ABC three phases, V CMV Is the common mode voltage.
The topology has seven output levels combined with the above, which are respectively 3V dc /4”、“-V dc /2”、“-V dc /4”、“0”、“V dc /4”、“V dc /2”、“3V dc /4". Seven output voltage level values of three-phase output are substituted into the formula, and 19 possible values of the common-mode voltage are obtained, wherein the possible values are as follows: "-3V dc /4”、“-2V dc /3”、“-7V dc /12”、“-V dc /2”“-5V dc /12”、“-V dc /3”、“-V dc /4”、“-V dc /6”、“-V dc /12”、“0”、“V dc /12”、“V dc /6”、“V dc /4”、“V dc /3”“5V dc /12”、“V dc /2”、“7V dc /12”、“2V dc /3”、“3V dc /4' where V dc The voltage for the entire dc power supply =4E. The common mode reducing method used by the invention is to perform space vector modulation by only adopting the coordinate with the minimum common mode voltage, wherein the minimum common mode voltage is 0 or +/-1/12V dc By the method, the common-mode voltage of the system can be reduced, and the common-mode leakage current caused by the common-mode voltage is reduced to reduce unnecessary loss.
According to an embodiment of the present invention, when the H-bridge cell fault is bypassed, the remaining voltage vector has coordinates (x, y, z) (x =1,3, 5), and the vectors and coordinates after the common mode reduction screening process are shown in fig. 4, where the number of the remaining vectors and coordinates is 53, the output voltage level is reduced from seven to three, and the common mode voltage is also reduced to ± 1/12V dc In between.
According to an embodiment of the invention, a fault tolerance method of a hybrid topology seven-level inverter is simulated, and fig. 5 (a) shows that when the direct current bus voltage is 580V, namely, V dc And =580V, the output voltage of the a-phase in normal operation after common mode reduction processing. The output voltage has seven levels and the amplitude of the output voltage is +/-3/4V dc Within the range. FIG. 5 (b) shows the output voltage after fault-tolerant control when the A-phase H-bridge unit fails after common mode reduction, the output voltage is reduced from seven levels to three levels, and the amplitude of the output voltage is reduced to +/-1/2V dc And (4) the following steps. Fig. 5 (c) shows the output line voltage after common reduction processing when the AB two phases operate normally, which is slightly distorted from nine significant levels compared with the output line voltage after fault-tolerant control when the a-phase H-bridge unit fault B phase operates normally shown in fig. 5 (d). FIG. 5 (e)) And fig. 5 (f) shows that the three-phase output current is stable and has a good waveform when the three-phase output current is normally operated after common mode reduction processing, and the three-phase output current is subjected to fault-tolerant control when the a-phase H-bridge unit fails after common mode reduction processing, and the output current fluctuates to some extent when the a-phase H-bridge unit fails, and the fluctuation is most obvious when the peak value is reached. FIG. 5 (g) shows the common-mode voltage after common-mode reduction processing, and the common-mode voltage is suppressed to + -1/12V by applying the common-mode reduction method dc Within the range. From this it can be concluded that: the common-mode reduction fault-tolerant control method has the function of inhibiting the common-mode voltage, namely, the absolute value of the original maximum common-mode voltage is 3/4V dc Reduced to 1/12V dc The common mode voltage within the system is greatly reduced.
The invention also provides the following product examples:
a control apparatus comprising a processor and a computer readable storage medium, the processor being configured to implement instructions; the computer readable storage medium is used for storing a plurality of instructions adapted to be loaded by a processor and to perform the steps of the method.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.

Claims (10)

1. A prediction control method for a hybrid topology seven-level inverter is characterized by comprising the following steps:
establishing a value function without a weight factor by using a discrete model predicted by a single vector model, and performing space vector modulation by using a predicted voltage at the minimum value of the value function to replace a reference voltage;
when a certain phase H bridge unit fails, fault-tolerant control is carried out, the H bridge unit is entirely bypassed, and the hybrid topology seven-level inverter in normal work is converted into a T-type three-level inverter in failure work to maintain the normal work of the system.
2. The predictive control method of a hybrid topology seven-level inverter according to claim 1, wherein the fault-tolerant control method is to create a seven-level voltage space vector diagram, remove the coordinates lost by bypassing the H-bridge unit due to the fault in the space vector diagram, and continue the space vector modulation using the remaining coordinates.
3. The predictive control method of a hybrid topology seven-level inverter according to claim 1, wherein when the H-bridge unit is bypassed, coordinates corresponding to a failure phase in the space vector diagram are screened to remove coordinates that do not satisfy the fault-tolerant control method, and the remaining coordinates are used for space vector modulation.
4. The predictive control method of the hybrid topology seven-level inverter according to claim 3, wherein a coordinate of the minimum common mode voltage corresponding to each point in the space vector diagram is calculated through definition of the common mode voltage, and space vector modulation is performed by using a voltage vector corresponding to the coordinate.
5. The predictive control method of the hybrid topology seven-level inverter according to claim 1, wherein the construction process of the discrete model of the single vector model prediction comprises: obtaining the output voltage of the hybrid topology inverter according to kirchhoff voltage law, converting the voltage into a current form, deducing a mathematical model of the output voltage under an alpha and beta orthogonal coordinate system by using Clarke transformation, representing a continuous model as a discrete model according to a sampling period, and predicting a reference voltage vector of a control target at the next moment.
6. The predictive control method of the hybrid topology seven-level inverter according to claim 5, wherein a cost function without weighting factors is constructed, and a basic voltage vector closest to the voltage predicted by the model is selected by calculating the cost function as a reference voltage vector to perform space vector modulation, thereby controlling the switching state of the switching device to output the voltage.
7. A mixed topology seven-level inverter comprises three-phase bridge arms which are connected in parallel, wherein each phase of bridge arm comprises one bridge arm and one H-bridge unit of a T-type three-level inverter;
the H-bridge unit consists of two-level half-bridge units formed by connecting four switching tubes in series end to end, and the upper and lower midpoints of an H-bridge unit circuit are connected with two ends of the flying capacitor; the middle points of the two half-bridge units are respectively connected with a T-shaped three-level inverter at the front stage and a power grid at the rear stage;
control using the predictive control method of any one of claims 1-6.
8. The hybrid topology seven-level inverter according to claim 7, wherein the switching tubes located at different positions have different voltage levels or types.
9. A computer readable storage medium having stored therein a plurality of instructions adapted to be loaded by a processor of a terminal device and to perform the steps of the method of any one of claims 1-6.
10. A control device comprising a processor and a computer readable storage medium, the processor being configured to implement instructions; the computer readable storage medium is for storing a plurality of instructions adapted to be loaded by a processor and to perform the steps of the method of any of claims 1-6.
CN202211295777.6A 2022-10-21 2022-10-21 Hybrid multi-level inverter prediction control method Pending CN115603605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211295777.6A CN115603605A (en) 2022-10-21 2022-10-21 Hybrid multi-level inverter prediction control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211295777.6A CN115603605A (en) 2022-10-21 2022-10-21 Hybrid multi-level inverter prediction control method

Publications (1)

Publication Number Publication Date
CN115603605A true CN115603605A (en) 2023-01-13

Family

ID=84848913

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211295777.6A Pending CN115603605A (en) 2022-10-21 2022-10-21 Hybrid multi-level inverter prediction control method

Country Status (1)

Country Link
CN (1) CN115603605A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116436329A (en) * 2023-05-10 2023-07-14 苏州大学 Three-phase four-bridge arm hybrid seven-level energy storage converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116436329A (en) * 2023-05-10 2023-07-14 苏州大学 Three-phase four-bridge arm hybrid seven-level energy storage converter

Similar Documents

Publication Publication Date Title
US10263535B2 (en) Method and device for voltage balancing of DC bus capacitors of neutral-point clamped four-level inverter
CN109863677B (en) Control of DC to AC modular multilevel converter
CN103580522A (en) Intelligent level transition systems and methods for transformerless uninterruptible power supply
CN112003491B (en) Control method and system of modular parallel three-phase three-level inverter
CN112910297B (en) Three-level SNPC converter system and two-stage model prediction control method
CN113193766B (en) Direct prediction control method and system for circulating current suppression of parallel converter cluster
Liu et al. An improved model predictive control method using optimized voltage vectors for vienna rectifier with fixed switching frequency
CN115603605A (en) Hybrid multi-level inverter prediction control method
CN109951097B (en) MMC space vector modulation method based on submodule recombination and having fault tolerance
CN115133798A (en) Discrete space vector modulation three-level inverter low common mode prediction control method
CN113746108B (en) T-type three-level SAPF open circuit fault sequence model prediction fault tolerance control method
Li et al. Operation, analysis and experiments of DC transformers based on modular multilevel converters for HVDC applications
CN113708655B (en) Inverter switching tube fault tolerance control method based on self-adaptive SVPWM
Lewicki et al. Structure and the space vector modulation for a medium‐voltage power‐electronic‐transformer based on two seven‐level cascade H‐bridge inverters
CN106972773A (en) A kind of three level grid-connected inverter constant switching frequency model predictive control methods
CN112701944B (en) Topology structure and control strategy of multi-level converter based on split power unit
CN105337522A (en) Double-carrier-wave modulation method of modular multilevel converter
Babaie et al. Self training intelligent predictive control for grid-tied transformerless multilevel converters
Li et al. An optimum PWM Strategy for 5-level active NPC (ANPC) converter based on real-time solution for THD minimization
CN114301321B (en) Reconfigurable fault-tolerant control method for hysteresis SVPWM of single-phase voltage source multi-level inverter
Kou et al. DC-link capacitor voltage balancing technique for phase-shifted PWM-based seven-switch five-level ANPC inverter
CN116247723A (en) PWM (pulse-width modulation) method and system for restraining zero-sequence circulation of parallel converter cluster
Cortés et al. Model predictive control of cascaded H-bridge multilevel inverters
Hussein et al. Modeling and control of a three-level dual output voltage converter
Rao et al. Model predictive control for cascaded multilevel inverter based on lyapunov function

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination